Subversion Repositories zxusbnet

Rev

Blame | Last modification | View Log | Download | RSS feed | ?url?

  1. #ifndef _W5300_H_
  2. #define _W5300_H_
  3. /**
  4.  * \file    w5300.h
  5.  *    Definition register of W5300 and basic I/O functions.
  6.  *
  7.  * This file defines the memory map and values of W5300 register.\n
  8.  * Also, it defines the basic I/O function to access register of W5300.
  9.  *
  10.  * \author MidnightCow
  11.  * \date 15/05/2008
  12.  * \version 1.1.0
  13.  *
  14.  * ----------  -------  -----------  ----------------------------
  15.  * Date        Version  Author       Description
  16.  * ----------  -------  -----------  ----------------------------
  17.  * 24/03/2008  1.0.0    MidnigthCow  Release with W5300 launching
  18.  * ----------  -------  -----------  ----------------------------
  19.  * 01/05/2008  1.0.1    MidnightCow  Modify a logical error in iinchip_irq(). Refer to M_01052008
  20.  * ----------  -------  -----------  ----------------------------
  21.  * 15/05/2008  1.1.0    MidnightCow  Refer to M_15052008
  22.  *                                   Delete getSn_DPORTR() because \ref Sn_DPORTR is write-only.
  23.  *                                   Replace 'Sn_DHAR2' with 'Sn_DIPR' in \ref getSn_DIPR().
  24.  * ----------  -------  -----------  ----------------------------
  25.  * 08/08/2008  1.2.0    MidnightCow  Refer to M_08082008
  26.  *                                   Add IINCHIP_CRITICAL_SECTION_ENTER() & IINCHIP_CRITICAL_SECTION_EXIT() to wiz_read_buf() and wiz_write_buf().
  27.  *                                   Modify the description of \ref Sn_SSR and \ref close().</td>
  28.  * ----------  -------  -----------  ----------------------------
  29.  * 15/03/2012  1.2.1    Dongeun      Solution of ARP problem
  30.  *                                   Add ApplySubnet() & ClearSubnet()
  31.  *                                   Modify getSUBR() & setSUBR()
  32.  * ----------  -------  -----------  ----------------------------
  33.  */
  34.  
  35.  
  36. #include "iinchip_conf.h"
  37. #include "types.h"
  38.  
  39.  
  40.  
  41. /**
  42.  *  Mode register.
  43.  */
  44. #define MR              (__DEF_IINCHIP_MAP_BASE__)
  45. #define MR0             MR
  46. #define MR1             (MR + 1)
  47.  
  48. /**
  49.   *  Indirect mode address register.
  50.  */
  51. #define IDM_AR          (__DEF_IINCHIP_MAP_BASE__ + 0x02)
  52. #define IDM_AR0         IDM_AR
  53. #define IDM_AR1         (IDM_AR + 1)
  54.  
  55. /**
  56.   *  Indirect mode data register.
  57.  */
  58. #define IDM_DR          (__DEF_IINCHIP_MAP_BASE__ + 0x04)
  59. #define IDM_DR0         (__DEF_IINCHIP_MAP_BASE__ + 0x04)
  60. #define IDM_DR1         (IDM_DR + 1)
  61.  
  62. /**
  63.  *  Interrupt register
  64.  */
  65. #define IR              (COMMON_REG_BASE + 0x02)
  66. #define IR0             IR
  67. #define IR1             (IR + 1)
  68.  
  69. /**
  70.  *  Interrupt mask register
  71.  */
  72. #define IMR             (COMMON_REG_BASE + 0x04)
  73. #define IMR0            IMR
  74. #define IMR1            (IMR + 1)
  75.  
  76.  
  77. //#define ICFGR           (COMMON_REG_BASE + 0x06)
  78. //#define ICFGR0          ICFGR
  79. //#define ICFGR1          (ICFGR0 + 1)
  80.  
  81. /**
  82.  *  Source hardware address register
  83.  */
  84. #define SHAR            (COMMON_REG_BASE + 0x08)
  85. #define SHAR0           SHAR
  86. #define SHAR1           (SHAR + 1)
  87. #define SHAR2           (SHAR + 2)
  88. #define SHAR3           (SHAR + 3)
  89. #define SHAR4           (SHAR + 4)
  90. #define SHAR5           (SHAR + 5)
  91.  
  92.  
  93. /**
  94.  *  Gateway IP address register
  95.  */
  96. #define GAR             (COMMON_REG_BASE + 0x10)
  97. #define GAR0            GAR
  98. #define GAR1            (GAR + 1)
  99. #define GAR2            (GAR + 2)
  100. #define GAR3            (GAR + 3)
  101.  
  102. /**
  103.  *  Subnet mask register
  104.  */
  105. #define SUBR            (COMMON_REG_BASE + 0x14)
  106. #define SUBR0           SUBR
  107. #define SUBR1           (SUBR + 1)
  108. #define SUBR2           (SUBR + 2)
  109. #define SUBR3           (SUBR + 3)
  110.  
  111. /**
  112.  *  Source IP address register
  113.  */
  114. #define SIPR            (COMMON_REG_BASE + 0x18)
  115. #define SIPR0           SIPR
  116. #define SIPR1           (SIPR + 1)
  117. #define SIPR2           (SIPR + 2)
  118. #define SIPR3           (SIPR + 3)
  119.  
  120. /**
  121.  *  Retransmittion timeout-period register
  122.  */
  123. #define RTR             (COMMON_REG_BASE + 0x1C)
  124. #define RTR0            RTR
  125. #define RTR1            (RTR + 1)
  126.  
  127. /**
  128.  *  Retransmittion retry count reigster
  129.  */
  130. #define RCR             (COMMON_REG_BASE + 0x1E)
  131. #define RCR0            RCR
  132. #define RCR1            (RCR + 1)
  133.  
  134. /**
  135.  *  Transmit memory size of each SOCKET reigster
  136.  */
  137. #define TMS01R          (COMMON_REG_BASE + 0x20)
  138. #define TMS23R          (TMS01R + 2) /**< Refer to TMS01R. */
  139. #define TMS45R          (TMS01R + 4) /**< Refer to TMS01R. */
  140. #define TMS67R          (TMS01R + 6) /**< Refer to TMS01R. */
  141.  
  142. #define TMSR0           TMS01R
  143. #define TMSR1           (TMSR0 + 1)
  144. #define TMSR2           (TMSR0 + 2)
  145. #define TMSR3           (TMSR0 + 3)
  146. #define TMSR4           (TMSR0 + 4)
  147. #define TMSR5           (TMSR0 + 5)
  148. #define TMSR6           (TMSR0 + 6)
  149. #define TMSR7           (TMSR0 + 7)
  150.  
  151.  
  152. /**
  153.  *  Transmit memory size of each SOCKET reigster
  154.  */
  155. #define RMS01R          (COMMON_REG_BASE + 0x28)
  156. #define RMS23R          (RMS01R + 2)   /**< Refer to RMS01R. */
  157. #define RMS45R          (RMS01R + 4)   /**< Refer to RMS01R. */
  158. #define RMS67R          (RMS01R + 6)   /**< Refer to RMS01R. */
  159.  
  160. #define RMSR0           RMS01R
  161. #define RMSR1           (RMSR0 + 1)
  162. #define RMSR2           (RMSR0 + 2)
  163. #define RMSR3           (RMSR0 + 3)
  164. #define RMSR4           (RMSR0 + 4)
  165. #define RMSR5           (RMSR0 + 5)
  166. #define RMSR6           (RMSR0 + 6)
  167. #define RMSR7           (RMSR0 + 7)
  168.  
  169.  
  170.  
  171. /**
  172.  *  Memory type register
  173.  */
  174. #define MTYPER          (COMMON_REG_BASE + 0x30)
  175. #define MTYPER0         MTYPER
  176. #define MTYPER1         (MTYPER + 1)
  177.  
  178. /**
  179.  *  Authentication type register
  180.  */
  181. #define PATR            (COMMON_REG_BASE + 0x32)
  182. #define PATR0           PATR
  183. #define PATR1           (PATR + 1)
  184.  
  185. //#define PPPALGOR      (COMMON_REG_BASE + 0x34)
  186. //#define PPPALGOR0     PPPALGOR
  187. //#define PPPALGOR1     (PPPALGOR + 1)
  188.  
  189. /**
  190.  *  PPP link control protocol request timer register
  191.  */
  192. #define PTIMER          (COMMON_REG_BASE + 0x36)
  193. #define PTIMER0         PTIMER
  194. #define PTIMER1         (PTIMER + 1)
  195.  
  196. /**
  197.  *  PPP LCP magic number register
  198.  */
  199. #define PMAGICR         (COMMON_REG_BASE + 0x38)
  200. #define PMAGICR0        PMAGICR
  201. #define PMAGICR1        (PMAGICR + 1)
  202.  
  203. //#define PSTATER       (COMMON_REG_BASE + 0x3A)
  204. //#define PSTATER0      PSTATER
  205. //#define PSTATER1      (PSTATER + 1)
  206.  
  207. /**
  208.  *  PPPoE session ID register
  209.  */
  210. #define PSIDR           (COMMON_REG_BASE + 0x3C)
  211. #define PSIDR0          PSIDR
  212. #define PSIDR1          (PSIDR + 1)
  213.  
  214. /**
  215.  *  PPPoE destination hardware address register
  216.  */
  217. #define PDHAR           (COMMON_REG_BASE + 0x40)
  218. #define PDHAR0          PDHAR
  219. #define PDHAR1          (PDHAR + 1)
  220. #define PDHAR2          (PDHAR + 2)
  221. #define PDHAR3          (PDHAR + 3)
  222. #define PDHAR4          (PDHAR + 4)
  223. #define PDHAR5          (PDHAR + 5)
  224.  
  225. /**
  226.  *  Unreachable IP address register
  227.  *
  228.  * RESET : 0.0.0.0 \n
  229.  * When trying to transmit UDP data to destination port number which is not open,
  230.  * W5300 can receive ICMP (Destination port unreachable) packet. \n
  231.  * In this case, IR(IR_DPUR) becomes '1'.
  232.  * And destination IP address and unreachable port number of ICMP packet
  233.  * can be acquired through UIPR and UPORTR.
  234.  */
  235. #define UIPR            (COMMON_REG_BASE + 0x48)
  236. #define UIPR0           UIPR
  237. #define UIPR1           (UIPR + 1)
  238. #define UIPR2           (UIPR + 2)
  239. #define UIPR3           (UIPR + 3)
  240.  
  241. /**
  242.  *  Unreachable port number register
  243.  */
  244. #define UPORTR          (COMMON_REG_BASE + 0x4C)
  245. #define UPORTR0         UPORTR
  246. #define UPORTR1         (UPORTR + 1)
  247.  
  248.  
  249.  
  250. /**
  251.  *  Fragment MTU register
  252.  */
  253. #define FMTUR           (COMMON_REG_BASE + 0x4E)
  254. #define FMTUR0          FMTUR
  255. #define FMTUR1          (FMTUR + 1)
  256.  
  257. //#define Sn_RTCR(n)      (COMMON_REG_BASE + 0x50 + n*2)
  258. //#define Sn_RTCR0(n)     Sn_RTCR(n)
  259. //#define Sn_RTCR1(n)     (Sn_RTCR(n)+1)
  260.  
  261. /**
  262.  *  PIN 'BRDYn' configure register
  263.  */
  264. #define Pn_BRDYR(n)     (COMMON_REG_BASE + 0x60 + n*4)
  265. #define Pn_BRDYR0(n)    Pn_BRDYR(n)
  266. #define Pn_BRDYR1(n)    (Pn_BRDYR(n) + 1)
  267.  
  268. /**
  269.  *  PIN 'BRDYn' buffer depth Register
  270.  */
  271. #define Pn_BDPTHR(n)    (COMMON_REG_BASE + 0x60 + n*4 + 2)
  272. #define Pn_BDPTHR0(n)   Pn_BDPTHR(n)
  273. #define Pn_BDPTHR1(n)   (Pn_BDPTHR(n) + 1)
  274.  
  275. /**
  276.  *  W5300 identification register
  277.  */
  278. #define IDR             (COMMON_REG_BASE + 0xFE)
  279. #define IDR0            (COMMON_REG_BASE + 0xFE)
  280. #define IDR1            (IDR + 1)
  281.  
  282.  
  283. /**
  284.  *  SOCKETn mode register
  285.  */
  286. #define Sn_MR(n)        (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x00)
  287. #define Sn_MR0(n)       Sn_MR(n)
  288. #define Sn_MR1(n)       (Sn_MR(n)+1)
  289.  
  290. /**
  291.  *  SOCKETn command register
  292.  */                        
  293. #define Sn_CR(n)        (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x02)
  294. #define Sn_CR0(n)       Sn_CR(n)
  295. #define Sn_CR1(n)       (Sn_CR(n) + 1)  
  296.  
  297. /**
  298.  *  SOCKETn interrupt mask register
  299.  */
  300. #define Sn_IMR(n)       (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x04)
  301. #define Sn_IMR0(n)      Sn_IMR(n)
  302. #define Sn_IMR1(n)      (Sn_IMR(n)+1)
  303.  
  304. /**
  305.  *  SOCKETn interrupt register
  306.  */
  307. #define Sn_IR(n)        (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x06)
  308. #define Sn_IR0(n)       Sn_IR(n)
  309. #define Sn_IR1(n)       (Sn_IR(n)+1)
  310.  
  311. /**
  312.  *  SOCKETn status register
  313.  */
  314. #define Sn_SSR(n)       (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x08)
  315. #define Sn_SSR0(n)      Sn_SSR(n)
  316. #define Sn_SSR1(n)      (Sn_SSR(n)+1)
  317.  
  318. /**
  319.  *  SOCKETn source port register
  320.  */
  321. #define Sn_PORTR(n)     (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x0A)
  322. #define Sn_PORTR0(n)    Sn_PORTR(n)
  323. #define Sn_PORTR1(n)    (Sn_PORTR(n)+1)
  324.  
  325. /**
  326.  *  SOCKETn destination hardware address register
  327.  */
  328. #define Sn_DHAR(n)      (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x0C)
  329. #define Sn_DHAR0(n)     Sn_DHAR(n)
  330. #define Sn_DHAR1(n)     (Sn_DHAR(n)+1)
  331. #define Sn_DHAR2(n)     (Sn_DHAR(n)+2)
  332. #define Sn_DHAR3(n)     (Sn_DHAR(n)+3)
  333. #define Sn_DHAR4(n)     (Sn_DHAR(n)+4)
  334. #define Sn_DHAR5(n)     (Sn_DHAR(n)+5)
  335.  
  336. /**
  337.  *  SOCKETn destination port register
  338.  */
  339. #define Sn_DPORTR(n)    (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x12)
  340. #define Sn_DPORTR0(n)   Sn_DPORTR(n)
  341. #define Sn_DPORTR1(n)   (Sn_DPORTR(n)+1)
  342.  
  343.  
  344. /**
  345.  *  SOCKETn destination IP address register
  346.  */
  347. #define Sn_DIPR(n)      (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x14)
  348. #define Sn_DIPR0(n)     Sn_DIPR(n)
  349. #define Sn_DIPR1(n)     (Sn_DIPR(n)+1)
  350. #define Sn_DIPR2(n)     (Sn_DIPR(n)+2)
  351. #define Sn_DIPR3(n)     (Sn_DIPR(n)+3)
  352.  
  353. /**
  354.  *  SOCKETn maximum segment size register
  355.  */
  356. #define Sn_MSSR(n)      (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x18)
  357. #define Sn_MSSR0(n)     Sn_MSSR(n)
  358. #define Sn_MSSR1(n)     (Sn_MSSR(n)+1)
  359.  
  360. /**
  361.  *  SOCKETn protocol of IP header field register
  362.  */
  363. #define Sn_PROTOR(n)            (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x1A)
  364. #define Sn_PROTOR0(n)           Sn_PROTOR(n)
  365. #define Sn_PROTOR1(n)   (Sn_PROTOR(n)+1)
  366. /**
  367.  *  SOCKETn keep alive timer register
  368.  */
  369. #define Sn_KPALVTR(n)   Sn_PROTOR(n)
  370.  
  371. /**
  372.  *  SOCKETn IP type of service(TOS) register
  373.  */
  374. #define Sn_TOSR(n)      (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x1C)
  375. #define Sn_TOSR0(n)     Sn_TOSR(n)
  376. #define Sn_TOSR1(n)     (Sn_TOSR(n)+1)
  377.  
  378. /**
  379.  *  SOCKETn IP time to live(TTL) register
  380.  */
  381. #define Sn_TTLR(n)      (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x1E)
  382. #define Sn_TTLR0(n)     Sn_TTLR(n)
  383. #define Sn_TTLR1(n)     (Sn_TTLR(n)+1)
  384.  
  385. /**
  386.  *  SOCKETn TX write size register
  387.  */
  388. #define Sn_TX_WRSR(n)           (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x20)
  389. #define Sn_TX_WRSR0(n)          Sn_TX_WRSR(n)
  390. #define Sn_TX_WRSR1(n)          (Sn_TX_WRSR(n) + 1)
  391. #define Sn_TX_WRSR2(n)          (Sn_TX_WRSR(n) + 2)
  392. #define Sn_TX_WRSR3(n)          (Sn_TX_WRSR(n) + 3)
  393.  
  394. /**
  395.  *  SOCKETn TX free size register
  396.  */
  397. #define Sn_TX_FSR(n)       (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x0024)
  398. #define Sn_TX_FSR0(n)      Sn_TX_FSR(n)
  399. #define Sn_TX_FSR1(n)      (Sn_TX_FSR(n) + 1)
  400. #define Sn_TX_FSR2(n)      (Sn_TX_FSR(n) + 2)
  401. #define Sn_TX_FSR3(n)      (Sn_TX_FSR(n) + 3)
  402.  
  403. /**
  404.  *  SOCKETn RX received size register
  405.  */
  406. #define Sn_RX_RSR(n)       (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x0028)
  407. #define Sn_RX_RSR0(n)      Sn_RX_RSR(n)
  408. #define Sn_RX_RSR1(n)      (Sn_RX_RSR(n) + 1)
  409. #define Sn_RX_RSR2(n)      (Sn_RX_RSR(n) + 2)
  410. #define Sn_RX_RSR3(n)      (Sn_RX_RSR(n) + 3)
  411.  
  412. /**
  413.  *  SOCKETn fragment register
  414.  */
  415. #define Sn_FRAGR(n)        (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x002C)
  416. #define Sn_FRAGR0(n)       Sn_FRAGR(n)
  417. #define Sn_FRAGR1(n)       (Sn_FRAGR(n) + 1)
  418.  
  419. /**
  420.  *  SOCKETn TX FIFO register
  421.  */
  422. #define Sn_TX_FIFOR(n)     (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x2E)
  423. #define Sn_TX_FIFOR0(n)    Sn_TX_FIFOR(n)
  424. #define Sn_TX_FIFOR1(n)    (Sn_TX_FIFOR(n) + 1)
  425.  
  426. /**
  427.  *  SOCKET n RX FIFO register
  428.  */
  429. #define Sn_RX_FIFOR(n)     (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x30)
  430. #define Sn_RX_FIFOR0(n)    Sn_RX_FIFOR(n)
  431. #define Sn_RX_FIFOR1(n)    (Sn_RX_FIFOR(n) + 1)
  432.  
  433.  
  434. //#define Sn_TX_SADR(n)      (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x32)
  435. //#define Sn_TX_SADR0(n)     Sn_TX_SADR(n)
  436. //#define Sn_TX_SADR1(n)     (Sn_TX_SADR(n) + 1)
  437.  
  438. //#define Sn_RX_SADR(n)      (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x34)
  439. //#define Sn_RX_SADR0(n)     Sn_RX_SADR(n)
  440. //#define Sn_RX_SADR1(n)     (Sn_RX_SADR(n) + 1)
  441.  
  442. //#define Sn_TX_RD(n)        (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x36)
  443. //#define Sn_TX_RD0(n)       (Sn_TX_RD(n) + 1)
  444. //#define Sn_TX_RD1(n)       (Sn_TX_RD(n) + 1)
  445.  
  446. //#define Sn_TX_WR(n)        (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x38)
  447. //#define Sn_TX_WR0(n)       Sn_TX_WR(n)
  448. //#define Sn_TX_WR1(n)       (Sn_TX_WR(n) + 1)
  449.  
  450. //#define Sn_TX_ACK(n)       (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x3A)
  451. //#define Sn_TX_ACK0(n)      (Sn_TX_ACK(n) + 1)
  452. //#define Sn_TX_ACK1(n)      (Sn_TX_ACK(n) + 1)
  453.  
  454. //#define Sn_RX_RD(n)           (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x3C)
  455. //#define Sn_RX_RD0(n)        Sn_RX_RD(n)
  456. //#define Sn_RX_RD1(n)        (Sn_RX_RD(n) + 1)
  457.  
  458. //#define Sn_RX_WR(n)        (SOCKET_REG_BASE + n * SOCKET_REG_SIZE + 0x3E)
  459. //#define Sn_RX_WR0(n)        Sn_RX_WR(n)
  460. //#define Sn_RX_WR1(n)       (Sn_RX_WR(n) + 1)
  461.  
  462.  
  463.  
  464. /************************************/
  465. /* The bit of MR regsiter defintion */
  466. /************************************/
  467. #define MR_DBW             (1 << 15)            /**< Data bus width bit of MR. */
  468. #define MR_MPF             (1 << 14)            /**< Mac layer pause frame bit of MR. */
  469. #define MR_WDF(X)          ((X & 0x07) << 11)   /**< Write data fetch time bit of  MR. */
  470. #define MR_RDH             (1 << 10)            /**< Read data hold time bit of MR. */
  471. #define MR_FS              (1 << 8)             /**< FIFO swap bit of MR. */
  472. #define MR_RST             (1 << 7)             /**< S/W reset bit of MR. */
  473. #define MR_MT              (1 << 5)             /**< Memory test bit of MR. */
  474. #define MR_PB              (1 << 4)             /**< Ping block bit of MR. */
  475. #define MR_PPPoE           (1 << 3)             /**< PPPoE bit of MR. */
  476. #define MR_DBS             (1 << 2)             /**< Data bus swap of MR. */
  477. #define MR_IND             (1 << 0)             /**< Indirect mode bit of MR. */
  478.  
  479.  
  480. /************************************/
  481. /* The bit of IR regsiter defintion */
  482. /************************************/
  483. #define IR_IPCF            (1 << 7)             /**< IP conflict bit of IR. */
  484. #define IR_DPUR            (1 << 6)             /**< Destination port unreachable bit of IR. */
  485. #define IR_PPPT            (1 << 5)             /**< PPPoE terminate bit of IR. */
  486. #define IR_FMTU            (1 << 4)             /**< Fragment MTU bit of IR. */
  487. #define IR_SnINT(n)        (0x01 << n)          /**< SOCKETn interrupt occurrence bit of IR. */
  488.  
  489. /*****************************************/
  490. /* The bit of Pn_BRDYR regsiter defintion*/
  491. /*****************************************/
  492. #define Pn_PEN             (1 << 7)             /**< PIN 'BRDYn' enable bit of Pn_BRDYR. */
  493. #define Pn_MT              (1 << 6)             /**< PIN memory type bit of Pn_BRDYR. */
  494. #define Pn_PPL             (1 << 5)             /**< PIN Polarity bit of Pn_BRDYR. */
  495. #define Pn_SN(n)           ((n & 0x07) << 0)    /**< PIN Polarity bit of Pn_BRDYR. */
  496.  
  497.  
  498. /***************************************/
  499. /* The bit of Sn_MR regsiter defintion */
  500. /***************************************/
  501. #define Sn_MR_ALIGN        (1 << 8)             /**< Alignment bit of Sn_MR. */
  502. #define Sn_MR_MULTI        (1 << 7)             /**< Multicasting bit of Sn_MR. */
  503. #define Sn_MR_MF           (1 << 6)             /**< MAC filter bit of Sn_MR. */
  504. #define Sn_MR_IGMPv        (1 << 5)             /**< IGMP version bit of Sn_MR. */
  505. #define Sn_MR_ND           (1 << 5)             /**< No delayed ack bit of Sn_MR. */
  506. #define Sn_MR_CLOSE        0x00                 /**< Protocol bits of Sn_MR. */
  507. #define Sn_MR_TCP          0x01                 /**< Protocol bits of Sn_MR. */
  508. #define Sn_MR_UDP          0x02                 /**< Protocol bits of Sn_MR. */
  509. #define Sn_MR_IPRAW        0x03                 /**< Protocol bits of Sn_MR. */
  510. #define Sn_MR_MACRAW       0x04                 /**< Protocol bits of Sn_MR. */
  511. #define Sn_MR_PPPoE        0x05                 /**< Protocol bits of Sn_MR. */
  512.  
  513.  
  514. /******************************/
  515. /* The values of CR defintion */
  516. /******************************/
  517. #define Sn_CR_OPEN         0x01                 /**< OPEN command value of Sn_CR. */
  518. #define Sn_CR_LISTEN       0x02                 /**< LISTEN command value of Sn_CR. */
  519. #define Sn_CR_CONNECT      0x04                 /**< CONNECT command value of Sn_CR. */
  520. #define Sn_CR_DISCON       0x08                 /**< DISCONNECT command value of Sn_CR. */
  521. #define Sn_CR_CLOSE        0x10                 /**< CLOSE command value of Sn_CR. */
  522. #define Sn_CR_SEND         0x20                 /**< SEND command value of Sn_CR. */
  523. #define Sn_CR_SEND_MAC     0x21                 /**< SEND_MAC command value of Sn_CR. */
  524. #define Sn_CR_SEND_KEEP    0x22                 /**< SEND_KEEP command value of Sn_CR */
  525. #define Sn_CR_RECV         0x40                 /**< RECV command value of Sn_CR */
  526. #define Sn_CR_PCON         0x23                 /**< PCON command value of Sn_CR */
  527. #define Sn_CR_PDISCON      0x24                 /**< PDISCON command value of Sn_CR */
  528. #define Sn_CR_PCR          0x25                 /**< PCR command value of Sn_CR */
  529. #define Sn_CR_PCN          0x26                 /**< PCN command value of Sn_CR */
  530. #define Sn_CR_PCJ          0x27                 /**< PCJ command value of Sn_CR */
  531.  
  532.  
  533. /*********************************/
  534. /* The values of Sn_IR defintion */
  535. /*********************************/
  536. #define Sn_IR_PRECV        0x80                 /**< PPP receive bit of Sn_IR */
  537. #define Sn_IR_PFAIL        0x40                 /**< PPP fail bit of Sn_IR */
  538. #define Sn_IR_PNEXT        0x20                 /**< PPP next phase bit of Sn_IR */
  539. #define Sn_IR_SENDOK       0x10                 /**< Send OK bit of Sn_IR */
  540. #define Sn_IR_TIMEOUT      0x08                 /**< Timout bit of Sn_IR */
  541. #define Sn_IR_RECV         0x04                 /**< Receive bit of Sn_IR */
  542. #define Sn_IR_DISCON       0x02                 /**< Disconnect bit of Sn_IR */
  543. #define Sn_IR_CON          0x01                 /**< Connect bit of Sn_IR */
  544.  
  545. /**********************************/
  546. /* The values of Sn_SSR defintion */
  547. /**********************************/
  548. #define SOCK_CLOSED        0x00                 /**< SOCKETn is released */
  549. #define SOCK_ARP           0x01                 /**< ARP-request is transmitted in order to acquire destination hardware address. */
  550. #define SOCK_INIT          0x13                 /**< SOCKETn is open as TCP mode. */
  551. #define SOCK_LISTEN        0x14                 /**< SOCKETn operates as "TCP SERVER" and waits for connection-request (SYN packet) from "TCP CLIENT". */
  552. #define SOCK_SYNSENT       0x15                 /**< Connect-request(SYN packet) is transmitted to "TCP SERVER". */
  553. #define SOCK_SYNRECV       0x16                 /**< Connect-request(SYN packet) is received from "TCP CLIENT". */
  554. #define SOCK_ESTABLISHED   0x17                 /**< TCP connection is established. */
  555. #define SOCK_FIN_WAIT      0x18                 /**< SOCKETn is closing. */
  556. #define SOCK_CLOSING       0x1A                 /**< SOCKETn is closing. */
  557. #define SOCK_TIME_WAIT     0x1B                 /**< SOCKETn is closing. */
  558. #define SOCK_CLOSE_WAIT    0x1C                 /**< Disconnect-request(FIN packet) is received from the peer. */
  559. #define SOCK_LAST_ACK      0x1D                 /**< SOCKETn is closing. */
  560. #define SOCK_UDP           0x22                 /**< SOCKETn is open as UDP mode. */
  561. #define SOCK_IPRAW         0x32                 /**< SOCKETn is open as IPRAW mode. */
  562. #define SOCK_MACRAW        0x42                 /**< SOCKET0 is open as MACRAW mode. */
  563. #define SOCK_PPPoE         0x5F                 /**< SOCKET0 is open as PPPoE mode. */
  564.  
  565. /* IP PROTOCOL */
  566. #define IPPROTO_IP         0   /* Dummy for IP */
  567. #define IPPROTO_ICMP       1   /* Control message protocol */
  568. #define IPPROTO_IGMP       2   /* Internet group management protocol */
  569. #define IPPROTO_GGP        3   /* Gateway^2 (deprecated) */
  570. #define IPPROTO_TCP        6   /* TCP */
  571. #define IPPROTO_PUP        12  /* PUP */
  572. #define IPPROTO_UDP        17  /* UDP */
  573. #define IPPROTO_IDP        22  /* XNS idp */
  574. #define IPPROTO_ND         77  /* UNOFFICIAL net disk protocol */
  575. #define IPPROTO_RAW        255 /* Raw IP packet */
  576.  
  577. /***********************
  578.  * Basic I/O  Function *
  579.  ***********************/
  580. /**
  581.  * It reads a value from a register
  582.  */
  583. uint8 IINCHIP_READ(uint16 addr);
  584.  
  585. /**
  586.  * It writes a value to a register
  587.  */
  588. void     IINCHIP_WRITE(uint16 addr,uint8 data);
  589.  
  590. /**
  591.  * It gets MR value.
  592.  */
  593. uint16   getMR(void);
  594.  
  595. /**
  596.  * It sets MR value
  597.  */
  598. void     setMR(uint16 val);
  599.  
  600.  
  601. /***********************************
  602.  * COMMON Register Access Function *
  603.  ***********************************/
  604.  
  605. /**
  606.  * It gets IR value
  607.  */
  608. uint16   getIR(void);
  609.  
  610. /**
  611.  * It sets IR value
  612.  */
  613. void     setIR(uint16 val);
  614.  
  615. /**
  616.  * It gets IMR value
  617.  */
  618. uint16   getIMR(void);
  619.  
  620. /**
  621.  * It sets IMR value
  622.  */
  623. void     setIMR(uint16 mask);
  624.  
  625. /**
  626.  * It gets the source hardware address
  627.  */
  628. void     getSHAR(uint8 * addr);
  629.  
  630. /**
  631.  * It sets the source hardware address
  632.  */
  633. void     setSHAR(uint8 * addr);
  634.  
  635. /**
  636.  * It gets the gateway IP address
  637.  */
  638. void     getGAR(uint8 * addr);
  639.  
  640. /**
  641.  * It sets the gateway IP address
  642.  */
  643. void     setGAR(uint8 * addr);    // set gateway address
  644.  
  645. /**
  646.  * It gets the subnet mask address
  647.  */
  648. void     getSUBR(uint8 * addr);
  649.  
  650. /**
  651.  * It sets the subnet mask address to global variable
  652.  */
  653. void     setSUBR(uint8 * addr); // set subnet mask address
  654.  
  655. /**
  656.  * It sets the subnet mask address from global variable
  657.  */
  658. void     ApplySubnet(); // set subnet mask address to SUBR
  659.  
  660. /**
  661.  * It sets the subnet mask address "0.0.0.0"
  662.  */
  663. void     ClearSubnet(); // set subnet mask address "0.0.0.0"
  664.  
  665. /**
  666.  * It gets the source IP address
  667.  */
  668. void     getSIPR(uint8 * addr);
  669.  
  670. /**
  671.  * It sets the source IP address
  672.  */
  673. void     setSIPR(uint8 * addr); // set local IP address
  674.  
  675. /**
  676.  * It gets RTR value
  677.  */
  678. uint16   getRTR(void);
  679.  
  680. /**
  681.  * It sets RTR value
  682.  */
  683. void     setRTR(uint16 timeout); // set retry duration for data transmission, connection, closing ...
  684.  
  685. /**
  686.  * It gets RCR value
  687.  */
  688. uint8    getRCR(void);
  689. /**
  690.  * It sets RCR value
  691.  */
  692. void     setRCR(uint8 retry);
  693.  
  694. /**
  695.  * It gets PATR value
  696.  */
  697. uint16   getPATR(void);
  698.  
  699. /**
  700.  * It gets PTIMER value
  701.  */
  702. uint8    getPTIMER(void);
  703.  
  704. /**
  705.  * It sets PTIMER value
  706.  */
  707. void     setPTIMER(uint8 time);
  708.  
  709. /**
  710.  * It gets PMAGICR value
  711.  */
  712. uint8    getPMAGICR(void);
  713.  
  714. /**
  715.  * It sets PTIMER value
  716.  */
  717. void     setPMAGICR(uint8 magic);
  718.  
  719. /**
  720.  *  It gets PSIDR value
  721.  */
  722. uint16   getPSIDR(void);
  723.  
  724. /**
  725.  *  It gets the PPPoE server hardware address
  726.  */
  727. void     getPDHAR(uint8* addr);
  728.  
  729. /**
  730.  *  It gets the unreachable destination IP address of ICMP message.
  731.  */
  732. void     getUIPR(uint8* addr);
  733.  
  734. /**
  735.  *  It gets the unreachable destination port number of ICMP message.
  736.  */
  737. uint16   getUPORTR(void);
  738.  
  739. /**
  740.  *  It gets the fragmented MTU value of ICMP message.
  741.  */
  742. uint16   getFMTUR(void);
  743.  
  744. /**
  745.  *  It gets Pn_BRDYR value.
  746.  */
  747. uint8    getPn_BRDYR(uint8 p);
  748.  
  749. /**
  750.  *  It sets Pn_BRDYR value.
  751.  */
  752. void     setPn_BRDYR(uint8 p, uint8 cfg);
  753.  
  754. /**
  755.  *  It gets the buffer depth of PIN "BRDYn".
  756.  */
  757. uint16   getPn_BDPTHR(uint8 p);
  758.  
  759. /**
  760.  *  It sets the buffer depth of PIN "BRDYn".
  761.  */
  762. void     setPn_BDPTHR(uint8 p, uint16 depth);
  763.  
  764. /**
  765.  *  It gets the ID of W5300.
  766.  */
  767. uint16   getIDR(void);
  768.  
  769.  
  770.  
  771. /***********************************
  772.  * SOCKET Register Access Function *
  773.  ***********************************/
  774.  
  775. /**
  776.  *  It gets Sn_MR value.
  777.  */
  778. uint16   getSn_MR(SOCKET s);
  779.  
  780. /**
  781.  *  It sets Sn_MR value.
  782.  */
  783. void     setSn_MR(SOCKET s, uint16 mode);
  784.  
  785. /**
  786.  *  It gets Sn_CR value.
  787.  */
  788. uint8    getSn_CR(SOCKET s);
  789. /**
  790.  *  It sets Sn_CR value.
  791.  */
  792. void     setSn_CR(SOCKET s, uint8 com);
  793.  
  794. /**
  795.  *  It gets Sn_IMR value.
  796.  */
  797. uint8    getSn_IMR(SOCKET s);
  798.  
  799. /**
  800.  *  It sets Sn_IMR value.
  801.  */
  802. void     setSn_IMR(SOCKET s, uint8 mask);
  803.  
  804. /**
  805.  *  It gets Sn_IR value.
  806.  */
  807. uint8    getSn_IR(SOCKET s);
  808.  
  809. /**
  810.  *  It sets Sn_IR value.
  811.  */
  812. void     setSn_IR(SOCKET s, uint8 ir);
  813.  
  814. /**
  815.  *  It gets Sn_SSR value.
  816.  */
  817. uint8    getSn_SSR(SOCKET s);
  818.  
  819. /**
  820.  *  It gets Sn_DHAR value.
  821.  */
  822. void     getSn_DHAR(SOCKET s, uint8* addr);
  823.  
  824. /**
  825.  *  It sets Sn_DHAR value.
  826.  */
  827. void     setSn_DHAR(SOCKET s, uint8* addr);
  828.  
  829. // M_15052008 : Delete this function.
  830. /*
  831.  *  It gets Sn_DPORTR value.
  832.  */
  833. //uint16   getSn_DPORTR(SOCKET s);
  834.  
  835. /**
  836.  *  It sets Sn_DPORTR value.
  837.  */
  838. void     setSn_DPORTR(SOCKET s, uint16 port);
  839.  
  840. /**
  841.  *  It gets Sn_DIPR value.
  842.  */
  843. void     getSn_DIPR(SOCKET s, uint8* addr);
  844.  
  845. /**
  846.  *  It sets Sn_DIPR value.
  847.  */
  848. void     setSn_DIPR(SOCKET s, uint8* addr);
  849.  
  850. /**
  851.  *  It gets Sn_MSSR value.
  852.  */
  853. uint16   getSn_MSSR(SOCKET s);
  854.  
  855. /**
  856.  *  It sets Sn_MSSR value.
  857.  */
  858. void     setSn_MSSR(SOCKET s, uint16 mss);
  859.  
  860. /**
  861.  *  It gets Sn_KPALVTR value.
  862.  */
  863. uint8    getSn_KPALVTR(SOCKET s);
  864.  
  865. /**
  866.  *  It sets Sn_KPALVTR value.
  867.  */
  868. void     setSn_KPALVTR(SOCKET s, uint8 time);
  869.  
  870. /**
  871.  *  It gets Sn_TX_WRSR value.
  872.  */
  873. uint32   getSn_TX_WRSR(SOCKET s);
  874.  
  875. /**
  876.  *  It gets Sn_KPALVTR value.
  877.  */
  878. void     setSn_TX_WRSR(SOCKET s, uint32 size);
  879.  
  880. /**
  881.  *  It gets Sn_TX_FSR value.
  882.  */
  883. uint32   getSn_TX_FSR(SOCKET s);
  884.  
  885. /**
  886.  *  It gets Sn_RX_RSR value.
  887.  */
  888. uint32   getSn_RX_RSR(SOCKET s);
  889.  
  890. /**
  891.  *  It sets Sn_TX_FIFOR value.
  892.  */
  893. void     setSn_TX_FIFOR(SOCKET s, uint16 data);
  894.  
  895. /**
  896.  *  It gets Sn_RX_FIFOR value.
  897.  */
  898. uint16   getSn_RX_FIFOR(SOCKET s);
  899.  
  900. /**
  901.  *  It gets Sn_PROTOR value.
  902.  */
  903. uint8    getSn_PROTOR(SOCKET s);
  904.  
  905. /**
  906.  *  It sets Sn_PROTOR value.
  907.  */
  908. void     setSn_PROTOR(SOCKET s, uint8 pronum);
  909.  
  910. /**
  911.  *  It gets Sn_TOSR value.
  912.  */
  913. uint8    getSn_TOSR(SOCKET s);
  914.  
  915. /**
  916.  *  It sets Sn_TOSR value.
  917.  */
  918. void     setSn_TOSR(SOCKET s, uint8 tos);
  919.  
  920. /**
  921.  *  It gets Sn_TTLR value.
  922.  */
  923. uint8    getSn_TTLR(SOCKET s);
  924.  
  925. /**
  926.  *  It sets Sn_TTLR value.
  927.  */
  928. void     setSn_TTLR(SOCKET s, uint8 ttl);
  929.  
  930. /**
  931.  *  It gets Sn_FRAGR value.
  932.  */
  933. uint8    getSn_FRAGR(SOCKET s);
  934. /**
  935.  *  It sets Sn_FRAGR value.
  936.  */
  937. void     setSn_FRAGR(SOCKET s, uint8 frag);
  938.  
  939.  
  940.  
  941. /*******
  942.  * ETC *
  943.  *******/
  944.  
  945. /* Initialization & Interrupt request routine */
  946.  
  947. /**
  948.  *  It initializes W5300.
  949.  */
  950. void     iinchip_init(void);
  951.  
  952. /**
  953.  *  It handles the interrupt of W5300.
  954.  */
  955. #ifdef __DEF_IINCHIP_INT__
  956.    void     iinchip_irq(void);
  957. #endif
  958.  
  959.  
  960. /* Interanl memory operation */
  961.  
  962. /**
  963.  *  It allocate internal TX/RX meory of each SOCKET.
  964.  */
  965. uint8    sysinit(uint8* tx_size, uint8* rx_size); // setting tx/rx buf size
  966.  
  967.  
  968. /**
  969.  *  It copies data to interna TX memory
  970.  */
  971. uint32   wiz_write_buf(SOCKET s,uint8* buf,uint32 len);
  972.  
  973.  
  974. /**
  975.  *  It copies data to your buffer from interna RX memory
  976.  */
  977. uint32   wiz_read_buf(SOCKET s, uint8* buf,uint32 len);
  978.  
  979.  
  980. /**
  981.  *  It gets the max size of internal TX memory of each SOCKET
  982.  */
  983. uint32   getIINCHIP_TxMAX(SOCKET s);
  984.  
  985. /**
  986.  *  It gets the max size of internal RX memory of each SOCKET
  987.  */
  988. uint32   getIINCHIP_RxMAX(SOCKET s);
  989.  
  990.  
  991.  
  992. #ifdef __DEF_IINCHIP_PPP__
  993.    /**
  994.     *  It initializes to PPPoE of W5300
  995.     */
  996.    uint8    pppinit(uint8 *id, uint8 idlen, uint8 *passwd, uint8 passwdlen);
  997.    /**
  998.     *  It terminates PPPoE connection
  999.     */  
  1000.    void    pppterm(uint8 *mac, uint16 sessionid);
  1001. #endif
  1002.  
  1003. /**
  1004.  *  Delay function
  1005.  */
  1006. void  wait_1us(uint32 us);
  1007. /**
  1008.  *  Delay function
  1009.  */
  1010. void  wait_1ms(uint32 ms);
  1011. /**
  1012.  *  Delay function
  1013.  */
  1014. void  wait_10ms(uint32 ms);
  1015. #endif
  1016.