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ifndef __regf64xxinc__regf64xxinc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File F64xx.INC *;* *;* Contains Bit & Register Definitions for Z8encore F64xx *;* Source: Z8 Encore! XP F64xx Series Product Specification, PS019926-1114*;* *;****************************************************************************include "ez8com.inc";----------------------------------------------------------------------------; System Control;----------------------------------------------------------------------------; Flash OptionsOPTIONS0 label 0000hWDT_RES __z8cbit OPTIONS0,7 ; Watchdog Timer ResetWDT_AO __z8cbit OPTIONS0,6 ; Watchdog Timer Always OnOSC_SEL __z8cbfield OPTIONS0,4,2 ; Oscillator Mode SelectionVBO_AO __z8cbit OPTIONS0,3 ; Voltage Brown-Out Protection Always OnFRP __z8cbit OPTIONS0,2 ; (Flash) Read ProtectFWP __z8cbit OPTIONS0,0 ; Flash Write ProtectOPTIONS1 label 0001h;----------------------------------------------------------------------------; Interrupts VectorsRESET_vect label 0002h ; Reset (not an interrupt)WDT_vect label 0004h ; Watchdog TimerILL_INST_vect label 0006h ; Illegal Instruction Trap (not an interrupt)TIMER2_vect label 0008h ; Timer 2TIMER1_vect label 000ah ; Timer 1TIMER0_vect label 000ch ; Timer 0UART0_RX_vect label 000eh ; UART0 ReceiverUART0_TX_vect label 0010h ; UART0 TransmitterI2C_vect label 0012h ; I2CSPI_vect label 0014h ; SPIADC_vect label 0016h ; ADCA7_vect label 0018h ; Port A7 or Port D7, selectable rising or falling input edgeA6_vect label 001ah ; Port A6 or Port D6, selectable rising or falling input edgeA5_vect label 001ch ; Port A5 or Port D5, selectable rising or falling input edgeA4_vect label 001eh ; Port A4 or Port D4, selectable rising or falling input edgeA3_vect label 0020h ; Port A3 or Port D3, selectable rising or falling input edgeA2_vect label 0022h ; Port A2 or Port D2, selectable rising or falling input edgeA1_vect label 0024h ; Port A1 or Port D1, selectable rising or falling input edgeA0_vect label 0026h ; Port A0 or Port D0, selectable rising or falling input edgeif __hastimer3TIMER3_vect label 0028h ; Timer 3endifUART1_RX_vect label 002ah ; UART0 ReceiverUART1_TX_vect label 002ch ; UART0 TransmitterDMA_vect label 002eh ; DMAC3_vect label 0030h ; Port C3, both input edgesC2_vect label 0032h ; Port C2, both input edgesC1_vect label 0034h ; Port C1, both input edgesC0_vect label 0036h ; Port C0, both input edges;----------------------------------------------------------------------------; Interrupts__defirq macro NUM,BaseIRQ{NUM} sfr Base+0 ; Interrupt Request nIRQ{NUM}ENH sfr Base+1 ; IRQn Enable High BitIRQ{NUM}ENL sfr Base+2 ; IRQn Enable Low Bitendm__defirq "0",0fc0h__defirq "1",0fc3h__defirq "2",0fc6hT2I __z8bit IRQ0,7 ; Timer 2 Interrupt RequestT1I __z8bit IRQ0,6 ; Timer 1 Interrupt RequestT0I __z8bit IRQ0,5 ; Timer 0 Interrupt RequestU0RXI __z8bit IRQ0,4 ; UART 0 Receiver Interrupt RequestU0TXI __z8bit IRQ0,3 ; UART 0 Transmitter Interrupt RequestI2CI __z8bit IRQ0,2 ; I2C Interrupt RequestSPII __z8bit IRQ0,1 ; SPI Interrupt RequestADCI __z8bit IRQ0,0 ; ADC Interrupt RequestT2ENH __z8bit IRQ0ENH,7 ; Timer 1 Interrupt Enable & PriorityT2ENL __z8bit IRQ0ENL,7T1ENH __z8bit IRQ0ENH,6 ; Timer 1 Interrupt Enable & PriorityT1ENL __z8bit IRQ0ENL,6T0ENH __z8bit IRQ0ENH,5 ; Timer 0 Interrupt Enable & PriorityT0ENL __z8bit IRQ0ENL,5U0RENH __z8bit IRQ0ENH,4 ; UART 0 Receive Interrupt Enable & PriorityU0RENL __z8bit IRQ0ENL,4U0TENH __z8bit IRQ0ENH,3 ; UART 0 Transmit Interrupt Enable & PriorityU0TENL __z8bit IRQ0ENL,3I2CENH __z8bit IRQ0ENH,2 ; I2C Interrupt Enable & PriorityI2CENL __z8bit IRQ0ENL,2SPIENH __z8bit IRQ0ENH,1 ; SPI Interrupt Enable & PrioritySPIENL __z8bit IRQ0ENL,1ADCENH __z8bit IRQ0ENH,0 ; ADC Interrupt Enable & PriorityADCENL __z8bit IRQ0ENL,0PA7DI __z8bit IRQ1,7 ; Port A7 or Port D7 Interrupt RequestPA6DI __z8bit IRQ1,6 ; Port A6 or Port D6 Interrupt RequestPA5DI __z8bit IRQ1,5 ; Port A5 or Port D5 Interrupt RequestPA4DI __z8bit IRQ1,4 ; Port A4 or Port D4 Interrupt RequestPA3DI __z8bit IRQ1,3 ; Port A3 or Port D3 Interrupt RequestPA2DI __z8bit IRQ1,2 ; Port A2 or Port D2 Interrupt RequestPA1DI __z8bit IRQ1,1 ; Port A1 or Port D1 Interrupt RequestPA0DI __z8bit IRQ1,0 ; Port A0 or Port D0 Interrupt RequestPAD7ENH __z8bit IRQ1ENH,7 ; Port A7 or Port D7 Interrupt Enable & PriorityPAD7ENL __z8bit IRQ1ENL,7PAD6ENH __z8bit IRQ1ENH,6 ; Port A6 or Port D6 Interrupt Enable & PriorityPAD6ENL __z8bit IRQ1ENL,6PAD5ENH __z8bit IRQ1ENH,5 ; Port A5 or Port D5 Interrupt Enable & PriorityPAD5ENL __z8bit IRQ1ENL,5PAD4ENH __z8bit IRQ1ENH,4 ; Port A4 or Port D4 Interrupt Enable & PriorityPAD4ENL __z8bit IRQ1ENL,4PAD3ENH __z8bit IRQ1ENH,3 ; Port A3 or Port D3 Interrupt Enable & PriorityPAD3ENL __z8bit IRQ1ENL,3PAD2ENH __z8bit IRQ1ENH,2 ; Port A2 or Port D2 Interrupt Enable & PriorityPAD2ENL __z8bit IRQ1ENL,2PAD1ENH __z8bit IRQ1ENH,1 ; Port A1 or Port D1 Interrupt Enable & PriorityPAD1ENL __z8bit IRQ1ENL,1PAD0ENH __z8bit IRQ1ENH,0 ; Port A0 or Port D0 Interrupt Enable & PriorityPAD0ENL __z8bit IRQ1ENL,0T3I __z8bit IRQ2,7 ; Timer 3 Interrupt RequestU1RXI __z8bit IRQ2,6 ; UART 1 Receiver Interrupt RequestU1TXI __z8bit IRQ2,5 ; UART 1 Transmitter Interrupt RequestDMAI __z8bit IRQ2,4 ; DMA Interrupt RequestPC3I __z8bit IRQ2,3 ; Port C3 Interrupt RequestPC2I __z8bit IRQ2,2 ; Port C2 Interrupt RequestPC1I __z8bit IRQ2,1 ; Port C1 Interrupt RequestPC0I __z8bit IRQ2,0 ; Port C0 Interrupt RequestT3ENH __z8bit IRQ2ENH,7 ; Timer 3 Interrupt Enable & PriorityT3ENL __z8bit IRQ2ENL,7U1RENH __z8bit IRQ2ENH,6 ; UART 1 Receive Interrupt Enable & PriorityU1RENL __z8bit IRQ2ENL,6U1TENH __z8bit IRQ2ENH,5 ; UART 1 Transmit Interrupt Enable & PriorityU1TENL __z8bit IRQ2ENL,5DMAENH __z8bit IRQ2ENH,4 ; DMA Interrupt Enable & PriorityDMAENL __z8bit IRQ2ENL,4C3ENH __z8bit IRQ2ENH,3 ; Port C3 Interrupt Enable & PriorityC3ENL __z8bit IRQ2ENL,3C2ENH __z8bit IRQ2ENH,2 ; Port C2 Interrupt Enable & PriorityC2ENL __z8bit IRQ2ENL,2C1ENH __z8bit IRQ2ENH,1 ; Port C1 Interrupt Enable & PriorityC1ENL __z8bit IRQ2ENL,1C0ENH __z8bit IRQ2ENH,0 ; Port C0 Interrupt Enable & PriorityC0ENL __z8bit IRQ2ENL,0IRQES sfr 0fcdh ; Interrupt Edge SelectIRQPS sfr 0fceh ; Interrupt Port Select RegisterPAD7S __z8bit IRQPS,7 ; PAx/PDx SelectionPAD6S __z8bit IRQPS,6PAD5S __z8bit IRQPS,5PAD4S __z8bit IRQPS,4PAD3S __z8bit IRQPS,3PAD2S __z8bit IRQPS,2PAD1S __z8bit IRQPS,1PAD0S __z8bit IRQPS,0IRQCTL sfr 0fcfh ; Interrupt ControlIRQE __z8bit IRQCTL,7 ; Interrupt Request Enable;----------------------------------------------------------------------------; Flash Memory ControlFCTL sfr 0ff8h ; Flash ControlFCMD __z8bfield FCTL,0,8 ; Flash CommandFSTAT sfr 0ff8h ; Flash StatusFPS sfr 0ff9h ; Flash Page SelectINFO_EN __z8bit FPS,7 ; Information Area EnablePAGE __z8bfield FPS,0,7 ; Page SelectFPROT sfr 0ff9h ; Flash Sector ProtectFFREQH sfr 0ffah ; Flash Programming Frequency High ByteFFREQL sfr 0ffbh ; Flash Programming Frequency Low ByteFFREQ sfr FFREQH;----------------------------------------------------------------------------; GPIO__defgpio "A",0fd0h__defgpio "B",0fd4h__defgpio "C",0fd8h__defgpio "D",0fdch__defgpio "E",0fe0h__defgpio "F",0fe4h__defgpio "G",0fe8h__defgpio "H",0fech;----------------------------------------------------------------------------; Timer__deftimer "0",0f00h,0,1__deftimer "1",0f08h,0,1__deftimer "2",0f10h,0,1if __hastimer3__deftimer "3",0f18h,0,1endif;----------------------------------------------------------------------------; UART__defuart "0",0f40h__defuart "1",0f48h;----------------------------------------------------------------------------; I2C__defi2c 0f50h;----------------------------------------------------------------------------; SPI__defspi 0f60h;----------------------------------------------------------------------------; Analog/Digital ConverterADCCTL sfr 0f70h ; ADC Control 0CEN __z8bit ADCCTL,7 ; Conversion EnableVREF __z8bit ADCCTL,5 ; Voltage ReferenceCONT __z8bit ADCCTL,4 ; Continuous ConversionANAIN __z8bfield ADCCTL,0,3 ; Analog Input SelectADCD_H sfr 0f72h ; ADC Data High ByteADCD_L sfr 0f73h ; ADC Data Low BitsOVF __z8bit ADCD_L,0 ; Overflow StatusADCD sfr ADCD_H;----------------------------------------------------------------------------; DMA__defdma macro NUM,BaseDMA{NUM}CTL sfr Base+0 ; DMA ControlDMA{NUM}DEN __z8bit DMA{NUM}CTL,7 ; DMA EnableDMA{NUM}DLE __z8bit DMA{NUM}CTL,6 ; DMA Loop EnableDMA{NUM}DDIR __z8bit DMA{NUM}CTL,5 ; DMA Data Transfer DirectionDMA{NUM}IRQEN __z8bit DMA{NUM}CTL,4 ; DMA Interrupt EnableDMA{NUM}WSEL __z8bit DMA{NUM}CTL,3 ; Word SelectDMA{NUM}RSS __z8bfield DMA{NUM}CTL,0,3 ; Request Trigger Source SelectDMA{NUM}IO sfr Base+1 ; DMA I/O AddressDMA{NUM}H sfr Base+2 ; DMA End/Start Address High NibbleDMA{NUM}_END_H __z8bfield DMA{NUM}H,4,4 ; DMA End Address High NibbleDMA{NUM}_START_H __z8bfield DMA{NUM}H,0,4 ; DMA Start/Current Address High NibbleDMA{NUM}START sfr Base+3 ; DMA Start Address Low ByteDMA{NUM}END sfr Base+4 ; DMA End Address Low Byteendm__defdma "0",0fb0h__defdma "1",0fb8h;----------------------------------------------------------------------------; Watchdog TimerWDTCTL sfr 0ff0h ; Watchdog Timer ControlWDTU sfr 0ff1h ; Watchdog Timer Reload Upper ByteWDTH sfr 0ff2h ; Watchdog Timer Reload High ByteWDTL sfr 0ff3h ; Watchdog Timer Reload Low Byte;----------------------------------------------------------------------------restoreendif ; __regf64xxinc