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ifndef stddef60inc ; avoid multiple inclusionstddef60inc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - STDDEF60.INC *;* *;* Contains Macro Definitions for PowerPC *;* *;****************************************************************************if MOMPASS=1message "PowerPC Macro Definitions (C) 1994,2012 Alfred Arnold"switch MOMCPUNAMEcase "RS6000"message "Target System RS6000"case "MPC601"message "Target System MPC601"case "MPC505"message "Target System MPC505"case "PPC403"message "Target System PPC403"case "PPC403GC"message "Target System PPC403GC"case "MPC821"message "Target System MPC821"elsecasefatal "Wrong target selected: only MPC601, MPC505, PPC403[GC], MPC821 or RS6000 allowed"endcaseendif;============================================================================; Device Control Register__defdcr macro NAME,val,{NoExpand}NAME equ valmt{"NAME"} macro regmtdcr NAME,regendmmf{"NAME"} macro regmfdcr reg,NAMEendmendmif (MOMCPU=0x403)||(MOMCPU=0x403c)__defdcr BEAR,0x90 ; Bus Error Address__defdcr BESR,0x91 ; Bus Error Syndrome__defdcr BR0,0x80 ; Bank Registers 0..7__defdcr BR1,0x81__defdcr BR2,0x82__defdcr BR3,0x83__defdcr BR4,0x84__defdcr BR5,0x85__defdcr BR6,0x86__defdcr BR7,0x87__defdcr DMACC0,0xc4 ; DMA Chain Counter__defdcr DMACR0,0xc0 ; DMA Control Register Channel 0..3__defdcr DMACR1,0xc8__defdcr DMACR2,0xd0__defdcr DMACR3,0xd8__defdcr DMACT0,0xc1 ; DMA Count Register Channel 0..3__defdcr DMACT1,0xc9__defdcr DMACT2,0xd1__defdcr DMACT3,0xd9__defdcr DMADA0,0xc2 ; DMA Target Address Channel 0..3__defdcr DMADA1,0xca__defdcr DMADA2,0xd2__defdcr DMADA3,0xda__defdcr DMASA0,0xc3 ; DMA Source Address Channel 0..3__defdcr DMASA1,0xcb__defdcr DMASA2,0xd3__defdcr DMASA3,0xdb__defdcr DMASR,0xe0 ; DMA Status Register__defdcr EXISR,0x40 ; External Interrupt Status Register__defdcr EXIER,0x42 ; External Interrupt Enable Register__defdcr IOCR,0xa0 ; I/O Configurationendif;============================================================================; Special Purpose Registers__defspr macro NAME,val,{NoExpand}NAME equ valmt{"NAME"} macro regmtspr NAME,regendmmf{"NAME"} macro regmfspr reg,NAMEendmendm__defspr XER,0x001 ; Integer Exception Register__defspr LR,0x008 ; Link Register__defspr CTR,0x009 ; Count Register__defspr SRR0,0x01a ; Save/Restore Register__defspr SRR1,0x01b__defspr SPRG0,0x110 ; Special Purpose Register__defspr SPRG1,0x111__defspr SPRG2,0x112__defspr SPRG3,0x113switch MOMCPUcase 0x403,0x403c__defspr DAC1,0x3f6 ; Data Address Compare Register__defspr DAC2,0x3f7__defspr DBCR,0x3f2 ; Debug Control Register__defspr DBSR,0x3f0 ; Debug Status Register__defspr DCCR,0x3fa ; Data Cache Control Register__defspr DEAR,0x3d5 ; Data Exception Addresse Register__defspr ESR,0x3d4 ; Exception Syndrome Datea Access__defspr EVPR,0x3d6 ; Exception Vector Prefix__defspr IAC1,0x3f4 ; Code Address Compare Register__defspr IAC2,0x3f5__defspr ICCR,0x3fb ; Instruction Cache Control Register__defspr PBL1,0x3fc ; Lower Bounds__defspr PBL2,0x3fe__defspr PBU1,0x3fd ; Upper Bounds__defspr PBU2,0x3ff__defspr PIT,0x3db ; Timer__defspr PVR,0x11f ; Processor Version__defspr SRR2,0x3de ; Save Restore Registers__defspr SRR3,0x3df__defspr TBHI,0x3dc ; Time Base__defspr TBLO,0x3dd__defspr TCR,0x3da ; Timer Control Register__defspr TSR,0x3d8 ; Timer Status Register__defspr SGR,0x3b9 ; ????case 0x505__defspr TBL,268 ; Time Base__defspr TBU,269__defspr DSISR,18 ; Reason for Alignment Exceptions__defspr DAR,19 ; Erroneous Data Address after Exception__defspr DEC,22 ; counts @ 1 MHz__defspr EIE,80 ; External Interrupt Enable__defspr EID,81 ; External Interrupt Disable__defspr NRE,82 ; Non Recoverable Exception__defspr TBL_S,284 ; another Time Base ?!__defspr TBU_S,285__defspr PVR,287 ; Processor Version__defspr ICCST,560 ; Instruction Cache Control & Status__defspr ICADR,561 ; Instruktion Cache Address Register__defspr ICDAT,562 ; Instruktion Cache Data Register__defspr FPECR,1022 ; Floating Point Exception__defspr CMPA,144 ; Comparison Value A..D__defspr CMPB,145__defspr CMPC,146__defspr CMPD,147__defspr ECR,148 ; Debug Exception Cause__defspr DER,149 ; Debug Enable Register__defspr COUNTA,150 ; Breakpoint Counter__defspr COUNTB,151__defspr CMPE,152 ; Comparison Value E..H__defspr CMPF,153__defspr CMPG,154__defspr CMPH,155__defspr LCTRL1,156 ; Debug Control Comparator L Bus__defspr LCTRL2,157__defspr ICTRL,158 ; Debug Control I-Bus__defspr BAR,159 ; Breakpoint Address__defspr DPDR,630 ; Development Port Data__defspr DPIR,631 ; " " Instructionscase 0x601__defspr RTCU,0x004 ; Counter__defspr RTCL,0x005__defspr DEC,0x006__defspr DSISR,0x012__defspr DAR,0x013__defspr DEC2,0x016__defspr SDR1,0x019__defspr EAR,0x11a__defspr BAT0U,0x210__defspr BAT0L,0x211__defspr BAT1U,0x212__defspr BAT1L,0x213__defspr BAT2U,0x214__defspr BAT2L,0x215__defspr BAT3U,0x216__defspr BAT3L,0x217__defspr HID0,0x3f0__defspr HID1,0x3f1__defspr HID2,0x3f2__defspr HID5,0x3f5__defspr HID15,0x3ffcase 0x6000__defspr MQ,0x000 ; Upper Half Divident/Productcase 0x821__defspr EIE,80 ; External Interrupts Enable__defspr EID,81 ; External Interrupts Disable__defspr NRI,82 ; Non Recoverable Exception__defspr NRE,82 ; (alias)__defspr CMPA,144 ; Comparison Value A..D__defspr CMPB,145__defspr CMPC,146__defspr CMPD,147__defspr ICR,148 ; Debug Exception Cause__defspr ECR,148 ; (alias)__defspr DER,149 ; Debug Feature Enable__defspr COUNTA,150 ; Breakpoint Counter__defspr COUNTB,151__defspr CMPE,152 ; Comparison Value E..H__defspr CMPF,153__defspr CMPG,154__defspr CMPH,155__defspr LCTRL1,156 ; Debug Control Comparator L-Bus__defspr LCTRL2,157__defspr ICTRL,158 ; Debug Control I-Bus__defspr BAR,159 ; Breakpoint Address__defspr DPDR,630 ; Development Port Data__defspr DPIR,631 ; " " Instructions__defspr IMMR,638__defspr IC_CST,560 ; Instruktion Cache Control & Status Control & Status__defspr ICCST,560 ; (alias)__defspr ICCSR,560 ; (alias)__defspr IC_ADR,561 ; Instruktion Cache Control & Status Address Register__defspr ICADR,561 ; (alias)__defspr IC_DAT,562 ; Instruktion Cache Control & Status Data Register__defspr ICDAT,562 ; (alias)__defspr DC_CST,568 ; Steuerung & Status Data Cache__defspr DCCST,568 ; (alias)__defspr DCCSR,568 ; (alias)__defspr DC_ADR,569 ; Data Cache Address Register__defspr DCADR,569 ; (alias)__defspr DC_DAT,570 ; Data Cache Data Register__defspr DCDAT,570 ; (alias)__defspr MI_CTR,784__defspr MICTR,784__defspr MI_AP,786__defspr MIAP,786__defspr MI_EPN,787__defspr MIEPN,787__defspr MI_TWC,789__defspr MITWC,789__defspr MIL1DL2P,789 ; (alias)__defspr MI_RPN,790__defspr MIRPN,790__defspr MI_DBCAM,816__defspr MICAM,816__defspr MI_DBRAM0,817__defspr MIRAM0,817__defspr MI_DBRAM1,818__defspr MIRAM1,818__defspr MD_CTR,792__defspr MDCTR1,792__defspr M_CASID,793__defspr MCASID,793__defspr MD_AP,794__defspr MDAP,794__defspr MD_EPN,795__defspr MDEPN,795__defspr M_TWP,796__defspr MDTWB,796__defspr MDL1P,796 ; (alias)__defspr MD_TWC,797__defspr MDTWC,797__defspr MDL1DL2P,797 ; (alias)__defspr MD_RPN,798__defspr MDRPN,798__defspr M_TW,799__defspr MDTW,799__defspr MDSAVE,799 ; (alias)__defspr MD_DBCAM,824__defspr MDCAM,824__defspr MD_DBRAM0,825__defspr MDRAM0,825__defspr MD_DBRAM1,826__defspr MDRAM1,826endcaseif MOMCPU=0x403c__defspr pid, 0x3b1endif;============================================================================; Serial Port PPC403:if (MOMCPU=0x403)||(MOMCPU=0x403c)spls equ 0x40000000 ; Line Statesphs equ 0x40000002 ; State of Handshake Linesbrdh equ 0x40000004 ; Baud Raten Dividerbrdl equ 0x40000005spctl equ 0x40000006 ; Control Registersprc equ 0x40000007 ; Command Register Receiversptc equ 0x40000008 ; Command Register Transmittersprb equ 0x40000009 ; Transmit/Receive Buffersptb equ sprbendif;============================================================================; SIU MPC505:; erinnert irgendwie an die vom 6833x...if MOMCPU=0x505siumcr equ 0x8007fc00 ; Base Control Registersiutest1 equ 0x8007fc04memmap equ 0x8007fc20 ; Memory Layoutspecaddr equ 0x8007fc24 ; Allow/Block Speculative Loadsspecmask equ 0x8007fc28termstat equ 0x8007fc2cpicsr equ 0x8007fc40 ; Periodic Interrupts Controlpit equ 0x8007fc44 ; Periodic Interrupt Timer Count Valuebmcr equ 0x8007fc48 ; Bus Monitor Controlrsr equ 0x8007fc4c ; Reset Statussccr equ 0x8007fc50 ; System Clock Controlsccsr equ 0x8007fc54 ; System Clock Statusportbase equ 0x8007fc60ddrm equ portbase+0x00 ; Data Direction Register Port Mpmpar equ portbase+0x04 ; Pin Assignment Port Mportm equ portbase+0x08 ; Data Register Port Mpapar equ portbase+0x24 ; Pin Assignment Port A+Bpbpar equ paparporta equ portbase+0x28 ; Data Register Port A+Bportb equ portaddri equ portbase+0x38 ; Data Direction Register Port I..Lddrj equ ddriddrk equ ddriddrl equ ddripipar equ portbase+0x38 ; Pin Assignment Port I..Lpjpar equ piparpkpar equ piparplpar equ piparporti equ portbase+0x40 ; Data Register Port I..Lportj equ portiportk equ portiportl equ porticsbase equ 0x8007fd00csbtbar equ csbase+0xf8 ; Base Address Boot EPROMcsbtsbbar equ csbase+0xf0csbar1 equ csbase+0xe0 ; Base Addresses /CS1../CS5csbar2 equ csbase+0xd8csbar3 equ csbase+0xd0csbar4 equ csbase+0xc8csbar5 equ csbase+0xc0csbtor equ csbase+0xfc ; Boot EPROM Optionscsbtsbor equ csbase+0xf4csor0 equ csbase+0xec ; Options /CS1../CS11csor1 equ csbase+0xe4csor2 equ csbase+0xdccsor3 equ csbase+0xd4csor4 equ csbase+0xcccsor5 equ csbase+0xc4csor6 equ csbase+0xbccsor7 equ csbase+0xb4csor8 equ csbase+0xaccsor9 equ csbase+0xa4csor10 equ csbase+0x9ccsor11 equ csbase+0x94endif;----------------------------------------------------------------------------; Peripheral Control Unit MPC505if MOMCPU=0x505pcubase equ 0x8007ef80pcumcr equ pcubase+0x00 ; Base Configurationtstmsra equ pcubase+0x10tstmsrb equ tstmsratstcntrab equ pcubase+0x14tstreps equ tstcntrabtstcreg1 equ pcubase+0x18tstcreg2 equ tstcreg1tstdreg equ pcubase+0x1cirqpend equ pcubase+0x20 ; Pending Interruptsirqand equ pcubase+0x24 ; Enabled & Pending Interruptsirqenable equ pcubase+0x28 ; Enabled Interruptspitqil equ pcubase+0x2c ; Interrupt Level PortQ/PITswsr equ pcubase+0x40 ; Trigger Reload Watchdogswcr equ pcubase+0x44 ; Watchdog Controlswtc equ swcrswr equ pcubase+0x48pqedgdat equ pcubase+0x50 ; Edge Selection PortQpqpar equ pcubase+0x54 ; Pin Assignment PortQendif;----------------------------------------------------------------------------; SRAM Module MPC505if MOMCPU=0x505srammcr equ 0x8007f00 ; Basiskonfiguration SRAMendif;============================================================================; SUBI may have two or three argumentssubi macro dest,src,VALif "VAL"=""addi dest,dest,-srcelseifaddi dest,src,-VALendifendm;----------------------------------------------------------------------------; Comparisonscmpw macro cr,REG1,REG2if "REG2"=""cmp 0,0,cr,REG1elseifcmp cr,0,REG1,REG2endifendmcmpwi macro cr,REG1,IMMif "IMM"=""cmpi 0,0,cr,IMMelseifcmpi cr,0,REG1,immendifendmcmplw macro cr,REG1,REG2if "REG2"=""cmpl 0,0,cr,REG1elseifcmpl cr,0,REG1,REG2endifendmcmplwi macro cr,REG1,IMMif "IMM"=""cmpli 0,0,cr,IMMelseifcmpli cr,0,REG1,IMMendifendm;----------------------------------------------------------------------------; Extended Instructions Condition Code Registercrset macro bxcreqv bx,bx,bxendmcrnot macro bx,bycrnor bx,by,byendmcrmove macro bx,bycror bx,by,byendm;----------------------------------------------------------------------------; Extended Logic Instructionsnot macro dest,SRCif "SRC"=""nor dest,destelseifnor dest,SRC,SRCendifendmnot. macro dest,SRCif "SRC"=""nor. dest,destelseifnor. dest,SRC,SRCendifendmmr macro dest,srcor dest,src,srcendmmr. macro dest,srcor. dest,src,srcendmnop macroori 0,0,0endm;----------------------------------------------------------------------------; Simplified Shift-In Instructionsinslwi macro ra,rs,n,brlwimi ra,rs,32-b,b,b+n-1endminslwi. macro ra,rs,n,brlwimi. ra,rs,32-b,b,b+n-1endminsrwi macro ra,rs,n,brlwimi ra,rs,32-b-n,b,b+n-1endminsrwi. macro ra,rs,n,brlwimi. ra,rs,32-b-n,b,b+n-1endm__defins1 macro NAME,par1,par2,par3,{NoExpand}{"NAME"} macro ra,rs,nrlwinm ra,rs,par1,par2,par3endm{"NAME"}. macro ra,rs,nrlwinm. ra,rs,par1,par2,par3endmendm__defins2 macro NAME,par1,par2,par3,{NoExpand}{"NAME"} macro ra,rs,b,nrlwinm ra,rs,par1,par2,par3endm{"NAME"}. macro ra,rs,b,nrlwinm. ra,rs,par1,par2,par3endmendm__defins1 clrlwi,0,n,31__defins2 clrlslwi,n,b-n,31-n__defins1 clrrwi,0,0,31-n__defins2 extlwi,b,0,n-1__defins2 extrwi,b+n,32-n,31__defins1 rotlwi,n,0,31__defins1 rotrwi,32-n,0,31__defins1 slwi,n,0,31-n__defins1 srwi,32-n,n,31rotlw macro ra,rs,rbrlwnm ra,rs,rb,0,31endmrotlw. macro ra,rs,rbrlwnm. ra,rs,rb,0,31endm;----------------------------------------------------------------------------; Simplified Jumps__defjmp1 macro NAME,m1,m2,{NoExpand}{"NAME"} macro adrbc m1,m2,adrendm{"NAME"}a macro adrbca m1,m2,adrendm{"NAME"}l macro adrbcl m1,m2,adrendm{"NAME"}la macro adrbcla m1,m2,adrendmendm__defjmp1 bdnz,16,0__defjmp1 bdz,18,0__defjmp2 macro NAME,m1,{NoExpand}{"NAME"} macro cr,adrbc m1,cr,adrendm{"NAME"}a macro cr,adrbca m1,cr,adrendm{"NAME"}l macro cr,adrbcl m1,cr,adrendm{"NAME"}la macro cr,adrbcla m1,cr,adrendmendm__defjmp2 bdnzf,0__defjmp2 bdnzt,8__defjmp2 bdzf,2__defjmp2 bdzt,10__defjmp2 bf,4__defjmp2 bt,12__defjmp3 macro NAME,mask,ofs,{NoExpand}{"NAME"} macro cr,ADRif "ADR"=""bc mask,ofs,crelseifbc mask,cr*4+ofs,adrendifendm{"NAME"}a macro cr,ADRif "ADR"=""bca mask,ofs,crelseifbca mask,cr*4+ofs,adrendifendm{"NAME"}l macro cr,ADRif "ADR"=""bcl mask,ofs,crelseifbcl mask,cr*4+ofs,adrendifendm{"NAME"}la macro cr,ADRif "ADR"=""bcla mask,ofs,crelseifbcla mask,cr*4+ofs,adrendifendm{"NAME"}ctr macro CRif "CR"=""bcctr mask,ofselseifbc mask,CR*4+ofsendifendm{"NAME"}ctrl macro CRif "CR"=""bcl mask,ofselseifbcl mask,CR*4+ofsendifendm{"NAME"}lr macro CRif "CR"=""bclr mask,ofselseifbclr mask,4*CR+ofsendifendm{"NAME"}lrl macro CRif "CR"=""bclrl mask,ofselseifbclrl mask,4*CR+ofsendifendmendm__defjmp3 beq,12,2__defjmp3 bge,4,0__defjmp3 bgt,12,1__defjmp3 ble,4,1__defjmp3 blt,12,0__defjmp3 bne,4,2__defjmp3 bng,4,1__defjmp3 bnl,4,0__defjmp3 bns,4,3__defjmp3 bnu,4,3__defjmp3 bso,12,3__defjmp3 bun,12,3bctr macrobcctr 20,0endmbctrl macrobcctrl 20,0endm__defjmp4 macro NAME,mask,{NoExpand}{"NAME"} macro crbcctr mask,crendm{"NAME"}l macro crbcctrl mask,crendmendm__defjmp4 bfctr,4__defjmp4 btctr,12__defjmp6 macro NAME,mask,bit,{NoExpand}{"NAME"} macrobclr mask,bitendm{"NAME"}l macrobclrl mask,bitendmendm__defjmp6 blr,20,0__defjmp6 bdnzlr,16,0__defjmp6 bdzlr,18,0__defjmp7 macro NAME,mask,{NoExpand}{"NAME"} macro crbclr mask,crendm{"NAME"}l macro crbclrl mask,crendmendm__defjmp7 bdnzflr,0__defjmp7 bdnztlr,8__defjmp7 bdzflr,2__defjmp7 bdztlr,10__defjmp7 bflr,4__defjmp7 btlr,12;-------------------------------------------------------------------------; Trapstrap macro ra,rbtw 31,ra,rbendm__deftrap macro NAME,mask,{NoExpand}{"NAME"} macro ra,rbtw mask,ra,rbendm{"NAME"}i macro ra,imtwi mask,ra,imendmendm__deftrap tweq,4__deftrap twge,12__deftrap twgt,8__deftrap twle,20__deftrap twlge,5__deftrap twlgt,1__deftrap twlle,6__deftrap twllt,2__deftrap twlng,6__deftrap twlnl,5__deftrap twlt,16__deftrap twne,24__deftrap twng,20__deftrap twnl,12;-------------------------------------------------------------------------; MMU Macros PPC403G[BC]if (MOMCPU=0x403c)||(MOMCPU=0x403c)tlbrehi macro rt,ratlbre rt,ra,0endmtlbrelo macro rt,ratlbre rt,ra,1endmtlbwehi macro rt,ratlbwe rt,ra,0endmtlbwelo macro rt,ratlbwe rt,ra,1endmendif;=========================================================================restore ; allow listing againendif ; stddef60inc