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ifndef __reg72361inc ; avoid multiple inclusion__reg72361inc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File REG72361.INC *;* *;* contains SFR and Bit Definitions for ST72[AR/J/K]361 *;* *;* Source: ST72361 Data Sheet, Rev. 3, August 2010, Doc ID 12468 *;* *;****************************************************************************;----------------------------------------------------------------------------; Memory AddressesRAMSTART label $0080 ; start address internal RAMswitch substr(MOMCPUNAME,9,1)case "4","6"RAMEND label $067f ; end " " "case "7","9"RAMEND label $087f ; end " " "endcase;----------------------------------------------------------------------------; Interrupt VectorsPWM_ART_vect label $ffe0 ; PWM ART InterruptLINSCI1_vect label $ffe2 ; LINSCI1 Interrupt VectorLINSCI2_vect label $ffe4 ; LINSCI2 Interrupt VectorTIMER16_vect label $ffe6 ; 16-bit Timer Interrupt VectorTIMER8_vect label $ffe8 ; 8-bit Timer Interrupt VectorSPI_vect label $ffea ; SPI Interrupt VectorEI3_vect label $fff0 ; External Interrupt Vector B7..4EI2_vect label $fff2 ; External Interrupt Vector B3..0EI1_vect label $fff4 ; External Interrupt Vector F2..0EI0_vect label $fff6 ; External Interrupt Vector A3..0, shared withAWU_vect label $fff6 ; Auto wake up from haltMCC_RTC_vect label $fff8 ; Main clock controller time base interruptTLI_vect label $fffa ; Top Level InterruptTRAP_vect label $fffc ; TRAP (software) Interrupt VectorRESET_vect label $fffe ; RESET Vector;----------------------------------------------------------------------------; GPIOinclude "gpio.inc"__defgpio "PA",$0000__defgpio "PB",$0003__defgpio "PC",$0006__defgpio "PD",$0009__defgpio "PE",$000c__defgpio "PF",$000f;----------------------------------------------------------------------------; SPIinclude "spi2.inc"__defspi $0021;----------------------------------------------------------------------------; FlashFCSR label $0024 ; Flash Control/Status Register;----------------------------------------------------------------------------; ITCISPR0 label $0025 ; Interrupt Software Priority Register 0I0_0 bit ISPR0,0I1_0 bit ISPR0,1I0_1 bit ISPR0,2I1_1 bit ISPR0,3I0_2 bit ISPR0,4I1_2 bit ISPR0,5I0_3 bit ISPR0,6I1_3 bit ISPR0,7ISPR1 label $0026 ; Interrupt Software Priority Register 1I0_4 bit ISPR1,0I1_4 bit ISPR1,1I0_5 bit ISPR1,2I1_5 bit ISPR1,3I0_6 bit ISPR1,4I1_6 bit ISPR1,5I0_7 bit ISPR1,6I1_7 bit ISPR1,7ISPR2 label $0027 ; Interrupt Software Priority Register 2I0_8 bit ISPR2,0I1_8 bit ISPR2,1I0_9 bit ISPR2,2I1_9 bit ISPR2,3I0_10 bit ISPR2,4I1_10 bit ISPR2,5I0_11 bit ISPR2,6I1_11 bit ISPR2,7ISPR3 label $0028 ; Interrupt Software Priority Register 3I0_12 bit ISPR3,0I1_12 bit ISPR3,1I0_13 bit ISPR3,2I1_13 bit ISPR3,3EICR0 label $0029 ; External Interrupt Control Register 0IS3 bfield EICR0,6,2 ; ei3 sensitivityIS2 bfield EICR0,4,2 ; ei2 sensitivityIS1 bfield EICR0,2,2 ; ei1 sensitivityIS0 bfield EICR0,0,2 ; ei0 sensitivityEICR1 label $002a ; External Interrupt Control Register 1TLIS bit EICR1,1 ; Top Level Interrupt sensitivityTLIE bit EICR1,0 ; Top Level Interrupt enable;----------------------------------------------------------------------------; PWM ARTinclude "pwm_art.inc"__defpwmart $0031;----------------------------------------------------------------------------; 8-bit TimerT8CR2 label $003c ; Timer Control Register 2T8ICIE bit T8CR2,7 ; Input Capture Interrupt EnableT8OCIE bit T8CR2,6 ; Output Compare Interrupt EnableT8TOIE bit T8CR2,5 ; Timer Overflow Interrupt EnableT8FOLV2 bit T8CR2,4 ; Forced Output Compare 2T8FOLV1 bit T8CR2,3 ; Forced Output Compare 1T8OLVL2 bit T8CR2,2 ; Output Level 2T8IEDG1 bit T8CR2,1 ; Input Edge 1T8OLVL1 bit T8CR2,0 ; Output Level 1T8CR1 label $003d ; Timer Control Register 1T8OC1E bit T8CR1,7 ; Output Compare 1 Pin EnableT8OC2E bit T8CR1,6 ; Output Compare 2 Pin EnableT8OPM bit T8CR1,5 ; One Pulse ModeT8PWM bit T8CR1,4 ; Pulse Width ModulationT8CC bfield T8CR1,2,2 ; Clock ControlT8IEDG2 bit T8CR1,1 ; Input Edge 2T8CSR label $003e ; Timer Control/Status RegisterT8ICF1 bit T8CSR,7 ; Input Capture Flag 1T8OCF1 bit T8CSR,6 ; Output Compare Flag 1T8TOF bit T8CSR,5 ; Timer Overflow FlagT8ICF2 bit T8CSR,4 ; Input Capture Flag 2T8OCF2 bit T8CSR,3 ; Output Compare Flag 2T8TIMD bit T8CSR,2 ; Timer disableT8IC1R label $003f ; Timer Input Capture 1 RegisterT8OC1R label $0040 ; Timer Output Compare 1 RegisterT8CTR label $0041 ; Timer Counter RegisterT8ACTR label $0042 ; Timer Alternate Counter RegisterT8IC2R label $0043 ; Timer Input Capture 2 RegisterT8OC2R label $0044 ; Timer Output Compare 2 Register;----------------------------------------------------------------------------; 16-bit Timerinclude "timer.inc"__deftimer "T16",$0050T16CSR label T16SR ; Control/Status RegisterT16TIMD bit T16CSR,2 ; Timer Disable;----------------------------------------------------------------------------; LINSCI__deflinsci macro Name,Base__NS set "\{NAME}"SCI{__NS}SR label $0050 ; SCI Status RegisterSCI{__NS}TDRE bit SCI{__NS}SR,7 ; Transmit data register emptySCI{__NS}TC bit SCI{__NS}SR,6 ; Transmission completeSCI{__NS}RDRF bit SCI{__NS}SR,5 ; Received data ready flagSCI{__NS}IDLE bit SCI{__NS}SR,4 ; Idle line detectSCI{__NS}OR bit SCI{__NS}SR,3 ; Overrun errorSCI{__NS}NF bit SCI{__NS}SR,2 ; Noise flagSCI{__NS}FE bit SCI{__NS}SR,1 ; Framing errorSCI{__NS}PE bit SCI{__NS}SR,0 ; Parity ErrorSCI{__NS}DR label Base+$01 ; SCI Data RegisterSCI{__NS}BRR label Base+$02 ; SCI Baud Rate RegisterSCI{__NS}SCP bfield SCI{__NS}BRR,6,2 ; First SCI Prescaler [1:0]SCI{__NS}SCT bfield SCI{__NS}BRR,3,3 ; SCI Transmitter rate divisor [2:0]SCI{__NS}SCR bfield SCI{__NS}BRR,0,3 ; SCI Receiver rate divisor [2:0]SCI{__NS}CR1 label Base+$03 ; SCI Control Register 1SCI{__NS}R8 bit SCI{__NS}CR1,7 ; Receive data bit 8SCI{__NS}T8 bit SCI{__NS}CR1,6 ; Transmit data bit 8SCI{__NS}SCID bit SCI{__NS}CR1,5 ; SCI DisableSCI{__NS}M bit SCI{__NS}CR1,4 ; Word lengthSCI{__NS}WAKE bit SCI{__NS}CR1,3 ; Wake-Up methodSCI{__NS}PCE bit SCI{__NS}CR1,2 ; Parity control enableSCI{__NS}PS bit SCI{__NS}CR1,1 ; Parity selectionSCI{__NS}PIE bit SCI{__NS}CR1,0 ; Parity interrupt enableSCI{__NS}CR2 label Base+$04 ; SCI Control Register 2SCI{__NS}TIE bit SCI{__NS}CR2,7 ; Transmitter interrupt enableSCI{__NS}TCIE bit SCI{__NS}CR2,6 ; Transmission complete interrupt enableSCI{__NS}RIE bit SCI{__NS}CR2,5 ; Receiver interrupt enableSCI{__NS}ILIE bit SCI{__NS}CR2,4 ; Idle line interrupt enableSCI{__NS}TE bit SCI{__NS}CR2,3 ; Transmitter enableSCI{__NS}RE bit SCI{__NS}CR2,2 ; Receiver enableSCI{__NS}RWU bit SCI{__NS}CR2,1 ; Receiver wake-upSCI{__NS}SBK bit SCI{__NS}CR2,0 ; Send breakSCI{__NS}CR3 label Base+$05 ; SCI Control Register 3SCI{__NS}LINE bit SCI{__NS}CR3,6 ; LIN Mode EnableSCI{__NS}CLKEN bit SCI{__NS}CR3,3 ; Clock EnableSCI{__NS}CPOL bit SCI{__NS}CR3,2 ; Clock PolaritySCI{__NS}CPHA bit SCI{__NS}CR3,1 ; Clock PhaseSCI{__NS}LBCL bit SCI{__NS}CR3,0 ; Last bit clock pulseSCI{__NS}ERPR label Base+$06 ; SCI Extended Receive Prescaler RegisterSCI{__NS}ETPR label Base+$07 ; SCI Extended Transmit Prescaler Registerendm__deflinsci "1",$0048__deflinsci "2",$0060;----------------------------------------------------------------------------; Analog/Digital Converterinclude "adc10.inc"__defadc10 $0045SLOW bit ADCCSR,4 ; A/D Clock Selectionrestoreendif ; __reg72361inc