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ifndef regst9inc ; avoid multiple inclusionregst9inc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - Datei REGST9.INC *;* *;* Contains SFR, Macro, and Addres Definitions for the ST9 Family *;* *;****************************************************************************if (MOMCPUNAME<>"ST9020")&&(MOMCPUNAME<>"ST9030")&&(MOMCPUNAME<>"ST9040")&&(MOMCPUNAME<>"ST9050")fatal "wrong target selected: only ST9020,ST9030,ST9040, or ST9050 supported"endifif MOMPASS=1message "ST9 SFR Definitions (C) 1997 Alfred Arnold"endif;----------------------------------------------------------------------------; Register Banks__CNT set 0rept 16BK{"\{__CNT}"}0 equ __CNT*2BK{"\{__CNT}"}1 equ __CNT*2+1__CNT set __CNT+1endmBK_SYS equ BKE0 ; Group System DefinitionBK_F equ BKF0 ; Page Register Definition;----------------------------------------------------------------------------; Definition of a Bits:; This exploits the internal representation of Bit symbols: rrrrbbbi__defbit macro NAME,REG,BITPOSNAME bit ((REG&15)<<4)+(BITPOS<<1){"NAME"}m equ 1<<BITPOSendm;----------------------------------------------------------------------------; System GroupFCW reg RR230 ; Flag and Control WordCICR reg R230 ; Central Interrupt Control Register__defbit gcen,CICR,7 ; Global Counter Enable__defbit tlip,CICR,6 ; Top Level Interrupt Pending Bit__defbit tli,CICR,5 ; Top Level Interrupt Bit__defbit ien,CICR,4 ; Interrupt Enable Flag__defbit iam,CICR,3 ; Interrupt Arbitration Mode__defbit cpl2,CICR,2 ; Current Priority Level Bit 2__defbit cpl1,CICR,1 ; Current Priority Level Bit 1__defbit cpl0,CICR,0 ; Current Priority Level Bit 0cplm equ cpl2m|cpl1m|cpl0m ; Current Priority LevelFLAGR reg R231 ; Flags Register__defbit c,FLAGR,7 ; Carry Flag__defbit z,FLAGR,6 ; Zero Flag__defbit s,FLAGR,5 ; Sign Flag__defbit v,FLAGR,4 ; Overflow Flag__defbit d,FLAGR,3 ; Decimal Adjust Flag__defbit h,FLAGR,2 ; Half Carry Flag__defbit uf,FLAGR,1 ; User Flag 1__defbit dp,FLAGR,0 ; Data/Program Memory FlagRPP reg RR232 ; Register Pointer PairRP0R reg R232 ; Register Pointer #0__defbit rp0s,RP0R,2 ; Register Pointer SelectorRP1R reg R233 ; Register Pointer #1__defbit rp1s,RP1R,2 ; Register Pointer SelectorPPR reg R234 ; Page Pointer RegisterMODER reg R235 ; Mode Register__defbit ssp,MODER,7 ; System Stack Pointer Flag (int/ext)__defbit usp,MODER,6 ; User Stack Pointer Flag (int/ext)__defbit div2,MODER,5 ; External Clock Divided by 2__defbit prs2,MODER,4 ; Internal Clock Prescaling Bit 2__defbit prs1,MODER,3 ; Internal Clock Prescaling Bit 1__defbit prs0,MODER,2 ; Internal Clock Prescaling Bit 0__defbit brqen,MODER,1 ; Bus Request Enable__defbit himp,MODER,0 ; High Impedance Enableprsm equ prs2m|prs1m|prs0m ; Internal Clock PrescalerUSPR reg RR236 ; User Stack PointerUSPHR reg R236USPLR reg R237SSPR reg RR238 ; System Stack PointerSSPHR reg R238SSPLR reg R239;----------------------------------------------------------------------------; EEPROMif MOMCPUNAME="ST9040"EEP_PG equ 0 ; EEPROM Register PageEECR reg R241 ; EEPROM Control Register__defbit verify,EECR,6 ; EEPROM Verify Mode__defbit eestby,EECR,5 ; EEPROM Stand-By__defbit eeien,EECR,4 ; EEPROM Interrupt Enable__defbit pllst,EECR,3 ; Parallel Write Start__defbit pllen,EECR,2 ; Parallel Write Enable__defbit eebusy,EECR,1 ; EEPROM Busy__defbit eewen,EECR,0 ; EEPROM Write Enableendif;----------------------------------------------------------------------------; InterruptsEXINT_PG equ 0 ; EXTERNAL Interrupt Register PageEITR reg R242 ; External Interrupt Trigger Level Register__defbit tea0,EITR,0 ; Trigger Event A0 Bit__defbit tea1,EITR,1 ; Trigger Event A1 Bit__defbit teb0,EITR,2 ; Trigger Event B0 Bit__defbit teb1,EITR,3 ; Trigger Event B1 Bit__defbit tec0,EITR,4 ; Trigger Event C0 Bit__defbit tec1,EITR,5 ; Trigger Event C1 Bit__defbit ted0,EITR,6 ; Trigger Event D0 Bit__defbit ted1,EITR,7 ; Trigger Event D1 BitEIPR reg R243 ; External Interrupt Pending Register__defbit ipa0,EIPR,0 ; Interrupt Pending Bit Channel A0__defbit ipa1,EIPR,1 ; Interrupt Pending Bit " A1__defbit ipb0,EIPR,2 ; Interrupt Pending Bit " B0__defbit ipb1,EIPR,3 ; Interrupt Pending Bit " B1__defbit ipc0,EIPR,4 ; Interrupt Pending Bit " C0__defbit ipc1,EIPR,5 ; Interrupt Pending Bit " C1__defbit ipd0,EIPR,6 ; Interrupt Pending Bit " D0__defbit ipd1,EIPR,7 ; Interrupt Pending Bit " D1EIMR reg R244 ; External Interrupt Mask Register__defbit ima0,EIMR,0 ; Int. A0 Bit__defbit ima1,EIMR,1 ; Int. A1 Bit__defbit imb0,EIMR,2 ; Int. B0 Bit__defbit imb1,EIMR,3 ; Int. B1 Bit__defbit imc0,EIMR,4 ; Int. C0 Bit__defbit imc1,EIMR,5 ; Int. C1 Bit__defbit imd0,EIMR,6 ; Int. D0 Bit__defbit imd1,EIMR,7 ; Int. D1 BitEIPLR reg R245 ; Ext. Interrupt Priority Level RegisterEIVR reg R246 ; External Interrupt Vector Register__defbit ewen,EIVR,0 ; External Wait Enable__defbit ia0s,EIVR,1 ; Interrupt A0 Selection__defbit tlis,EIVR,2 ; Top Level Input Selection__defbit tltev,EIVR,3 ; Top Level Trigger EventNICR reg R247 ; Nested Interrupt Control Register__defbit tlnm,NICR,7 ; Top Level not Maskable;----------------------------------------------------------------------------; WatchdogWDT_PG equ 0 ; Timer Watchdog PageWDTR reg RR248 ; TWD Timer Constant RegisterWDTHR reg R248 ; TWD Timer High Constant RegisterWDTLR reg R249 ; TWD Timer Low Constant RegisterWDTPR reg R250 ; TWD Timer Prescaler Constant RegisterWDTCR reg R251 ; TWD Timer Control Register__defbit WD_stsp8,WDTCR,7 ; TWD Start Stop__defbit WD_sc,WDTCR,6 ; TWD Single Continuous Mode__defbit WD_inmd1,WDTCR,5 ; Input Mode 1__defbit WD_inmd2,WDTCR,4 ; Input Mode 2__defbit WD_inen,WDTCR,3 ; TWD Input Section Enable/Disable__defbit WD_outmd,WDTCR,2 ; TWD Output Mode__defbit WD_wrout,WDTCR,1 ; TWD Output Bit__defbit WD_outen,WDTCR,0 ; TWD Output Enableinm_evc equ 0 ; TWD Input Mode Event Counterinm_g equ 010h ; TWD Input Mode Gatedinm_t equ 020h ; TWD Input Mode Triggerableinm_r equ 030h ; TWD Input Mode RetriggerableWCR reg R252 ; Wait Control Register__defbit WD_wden,WCR,6 ; TWD Timer Enablewdm2 equ 1 << 5 ; Data Memory Wait Cyclewdm1 equ 1 << 4wdm0 equ 1 << 3wpm2 equ 1 << 2 ; Program Memory Wait Cyclewpm1 equ 1 << 1wpm0 equ 1 << 0dmwc1 equ wdm0 ; 1 Wait Cycle on Data M.dmwc2 equ wdm1 ; 2 Wait Cycles on Data M.dmwc3 equ wdm1|wdm0 ; 3 Wait Cycles on Data M.dmwc4 equ wdm2 ; 4 Wait Cycles on Data M.dmwc5 equ wdm2|wdm0 ; 5 Wait Cycles on Data M.dmwc6 equ wdm2|wdm1 ; 6 Wait Cycles on Data M.dmwc7 equ wdm2|wdm1|wdm0 ; 7 Wait Cycles on Data M.pmwc1 equ wpm0 ; 1 Wait Cycle on Prog M.pmwc2 equ wpm1 ; 2 Wait Cycles on Prog M.pmwc3 equ wpm1|wpm0 ; 3 Wait Cycles on Prog M.pmwc4 equ wpm2 ; 4 Wait Cycles on Prog M.pmwc5 equ wpm2|wpm0 ; 5 Wait Cycles on Prog M.pmwc6 equ wpm2|wpm1 ; 6 Wait Cycles on Prog M.pmwc7 equ wpm2|wpm1|wpm0 ; 7 Wait Cycles on Prog M.;----------------------------------------------------------------------------; SPISPI_PG equ 0 ; SPI Register PageSPIDR reg R253 ; SPI Data RegisterSPICR reg R254 ; SPI Control Register__defbit SP_spen,SPICR,7 ; Serial Peripheral Enable__defbit SP_bms,SPICR,6 ; SBUS/I2C Bus Mode Selector__defbit SP_arb,SPICR,5 ; Arbitration Flag Bit__defbit SP_busy,SPICR,4 ; SPI Busy Flag__defbit SP_cpol,SPICR,3 ; SPI Transmission Clock Polarity__defbit SP_cpha,SPICR,2 ; SPI Transmission Clock Phase__defbit SP_spr1,SPICR,1 ; SPI Rate Bit 1__defbit SP_spr0,SPICR,0 ; SPI Rate Bit 0SP_8 equ 0 ; SPI Clock Divider 8 = 1500 kHz (12MHz)SP_16 equ 1 ; SPI Clock Divider 16 = 750 kHz (12MHz)SP_128 equ 2 ; SPI Clock Divider 128 = 93.75 kHz (12MHz)SP_256 equ 3 ; SPI Clock Divider 256 = 46.87 kHz (12MHz)RW_PG equ 0 ; R/W Signal Programming Page;----------------------------------------------------------------------------; Read/Write Registerif MOMCPUNAME="ST9050"RWR reg R255 ; R/W Signal Programming Register__defbit RW_rw,RWR,0 ; R/W Bit__defbit RW_bs,RWR,1 ; Bank Switch Port Timingendif;----------------------------------------------------------------------------; PortsP0C_PG equ 2 ; Port 0 Control Registers PageP0DR reg R224 ; Port 0 Data RegisterP0C0R reg R240 ; Port 0 Control Register 0P0C1R reg R241 ; Port 0 Control Register 1P0C2R reg R242 ; Port 0 Control Register 2P1C_PG equ 2 ; Port 1 Control Registers PageP1DR reg R225 ; Port 1 Data RegisterP1C0R reg R244 ; Port 1 Control Register 0P1C1R reg R245 ; Port 1 Control Register 1P1C2R reg R246 ; Port 1 Control Register 2P2C_PG equ 2 ; Port 2 Control Registers PageP2DR reg R226 ; Port 2 Data RegisterBS_DSR reg R226 ; Bank Switch Data Segment RegisterP2C0R reg R248 ; Port 2 Control Register 0BS_DDSR reg R248 ; Bank Switch Data DMA Segment RegisterP2C1R reg R249 ; Port 2 Control Register 1BS_PDSR reg R249 ; Bank Switch Program DMA Segment RegisterP2C2R reg R250 ; Port 2 Control Register 2P3C_PG equ 2 ; Port 3 Control Registers PageP3DR reg R227 ; Port 3 Data RegisterBS_PSR reg R227 ; Bank Switch Program Segment RegisterP3C0R reg R252 ; Port 3 Control Register 0P3C1R reg R253 ; Port 3 Control Register 1P3C2R reg R254 ; Port 3 Control Register 2P4C_PG equ 3 ; Port 4 Control Registers PageP4DR reg R228 ; Port 4 Data RegisterP4C0R reg R240 ; Port 4 Control Register 0P4C1R reg R241 ; Port 4 Control Register 1P4C2R reg R242 ; Port 4 Control Register 2P5C_PG equ 3 ; Port 5 Control Registers PageP5DR reg R229 ; Port 5 Data RegisterP5C0R reg R244 ; Port 5 Control Register 0P5C1R reg R245 ; Port 5 Control Register 1P5C2R reg R246 ; Port 5 Control Register 2P6C_PG equ 3 ; Port 6 Control Registers PageP6D_PG equ 3 ; Port 6 Data Register PageP6DR reg R251 ; Port 6 Data RegisterP6C0R reg R248 ; Port 6 Control Register 0P6C1R reg R249 ; Port 6 Control Register 1P6C2R reg R250 ; Port 6 Control Register 2P7C_PG equ 3 ; Port 7 Control Registers PageP7D_PG equ 3 ; Port 7 Data Register PageP7DR reg R255 ; Port 7 Data RegisterP7C0R reg R252 ; Port 7 Control Register 0P7C1R reg R253 ; Port 7 Control Register 1P7C2R reg R254 ; Port 7 Control Register 2P8C_PG equ 43 ; Port 8 Control Registers PageP8D_PG equ 43 ; Port 8 Data Register PageP8DR reg R251 ; Port 8 Data RegisterP8C0R reg R248 ; Port 8 Control Register 0P8C1R reg R249 ; Port 8 Control Register 1P8C2R reg R250 ; Port 8 Control Register 2P9C_PG equ 43 ; Port 9 Control Registers PageP9D_PG equ 43 ; Port 9 Data Register PageP9DR reg R255 ; Port 9 Data RegisterP9C0R reg R252 ; Port 9 Control Register 0P9C1R reg R253 ; Port 9 Control Register 1P9C2R reg R254 ; Port 9 Control Register 2HDCTL2R reg R251 ; Port 2 handshake DMA Control RegisterHDCTL3R reg R255 ; Port 3 handshake DMA Control RegisterHDCTL4R reg R243 ; Port 4 handshake DMA Control RegisterHDCTL5R reg R247 ; Port 5 handshake DMA Control Register; Handshake DMA Control Register configurationhsdis equ 0E0h ; Handshake Disabled Maskhso2 equ 0C0h ; Handshake Output 2 Lines Maskhso1 equ 040h ; Handshake Output 1 Line Maskhsi2 equ 0A0h ; Handshake Input 2 Lines Maskhsi1 equ 020h ; Handshake Input 1 Line Maskhsb equ 000h ; Handshake bidirectional Maskden equ 000h ; DMA Enable Maskddi equ 010h ; DMA Disable Maskddw equ 000h ; Data Direction Output Mask (Write)ddr equ 008h ; Data Direction Input Mask (read)dst equ 004h ; DMA Strobe on Chip Event Maskdcp0 equ 000h ; DMA Channel Capture0 Maskdcm0 equ 002h ; DMA Channel Compare0 Mask;----------------------------------------------------------------------------; Multi Function TimerT0D_PG equ 10 ; MFTimer 0 Data Registers PageT0C_PG equ 9 ; MFTimer 0 Control Registers PageT1D_PG equ 8 ; MFTimer 1 Data Registers PageT1C_PG equ 9 ; MFTimer 1 Control Registers PageT2D_PG equ 14 ; MFTimer 2 Data Registers PageT2C_PG equ 13 ; MFTimer 2 Control Registers PageT3D_PG equ 12 ; MFTimer 3 Data Registers PageT3C_PG equ 13 ; MFTimer 3 Control Registers PageT_REG0R reg RR240 ; MFTimer REG0 Load and Capture RegisterT_REG0HR reg R240 ; Register 0 High RegisterT_REG0LR reg R241 ; Register 0 Low RegisterT_REG1R reg RR242 ; MFTimer REG1 Load ConstantT_REG1HR reg R242 ; Register 1 High RegisterT_REG1LR reg R243 ; Register 1 Low RegisterT_CMP0R reg RR244 ; MFTimer CMP0 Store Compare ConstantT_CMP0HR reg R244 ; Compare 0 High RegisterT_CMP0LR reg R245 ; Compare 0 Low RegisterT_CMP1R reg RR246 ; MFTimer CMP1 Store Compare ConstantT_CMP1HR reg R246 ; Compare 1 High RegisterT_CMP1LR reg R247 ; Compare 1 Low RegisterT_TCR reg R248 ; MFTimer Control Register__defbit T_cs,T_TCR,0 ; Counter Status__defbit T_of0,T_TCR,1 ; Over/UnderfLow on CAP on REG0__defbit T_udcs,T_TCR,2 ; Up/Down Count Status__defbit T_udc,T_TCR,3 ; Up/Down Count__defbit T_ccl,T_TCR,4 ; Counter Clear__defbit T_ccmp0,T_TCR,5 ; Clear on Compare 0__defbit T_ccp0,T_TCR,6 ; Clear on Capture__defbit T_cen,T_TCR,7 ; Counter EnableT_TMR reg R249 ; MFTimer Mode Register__defbit T_co,T_TMR,0 ; Continuous/One Shot Bit__defbit T_ren,T_TMR,1 ; Retrigger Enable Bit__defbit T_eck,T_TMR,2 ; Enable Clocking Mode Bit__defbit T_rm0,T_TMR,3 ; Register 0 Mode Bit__defbit T_rm1,T_TMR,4 ; Register 1 Mode Bit__defbit T_bm,T_TMR,5 ; Bivalue Mode Bit__defbit T_oe0,T_TMR,6 ; Output 0 Enable Bit__defbit T_oe1,T_TMR,7 ; Output 1 Enable BitT_ICR reg R250 ; MFTimer External Input Control Registerexb_f equ 01h ; External B Falling Edge Sensitive Maskexb_r equ 02h ; External B Rising Edge Sensitive Maskexb_rf equ 03h ; External B Falling and Rising Edge Maskexa_f equ 04h ; External A Falling Edge Sensitive Maskexa_r equ 08h ; External A Rising Edge Sensitive Maskexa_rf equ 0Ch ; External A Falling and Rising Edge Maskab_ii equ 00h ; A I/O B I/O Maskab_it equ 10h ; A I/O B Trigger Maskab_gi equ 20h ; A Gate B I/O Maskab_gt equ 30h ; A Gate B Trigger Maskab_ie equ 40h ; A I/O B External Clock Maskab_ti equ 50h ; A Trigger B I/O Maskab_ge equ 60h ; A Gate B External Clock Maskab_tt equ 70h ; A Trigger B Trigger Maskab_cucd equ 80h ; A Clock Up B Clock Down Maskab_ue equ 90h ; A Clock Up/Down B External Clock Maskab_tutd equ 0A0h ; A Trigger Up B Trigger Down Maskab_ui equ 0B0h ; A Up/Down Clock B I/O Maskab_aa equ 0C0h ; A Autodiscr. B Autodiscr. Maskab_te equ 0D0h ; A Trigger B External Clock Maskab_et equ 0E0h ; A External Clock B Trigger Maskab_tg equ 0F0h ; A Trigger B Gate MaskT_PRSR reg R251 ; MFTimer Prescaler RegisterT_OACR reg R252 ; MFTimer Output A Control Registercev equ 02h ; On Chip Event Bit on Compare 0 MaskT_OBCR reg R253 ; MFTimer Output B Control Registerop equ 01h ; Output Preset Bit Maskoev equ 02h ; On Chip Event Bit on OVF/UDF Maskou_set equ 00h ; Overflow Underflow Set Maskou_tog equ 04h ; Overflow Underflow Toggle Maskou_res equ 08h ; Overflow Underflow Reset Maskou_nop equ 0Ch ; Overflow Underflow NOP Maskc1_set equ 00h ; Compare 1 Set Maskc1_tog equ 10h ; Compare 1 toggle Maskc1_res equ 20h ; Compare 1 Reset Maskc1_nop equ 30h ; Compare 1 NOP Maskc0_set equ 00h ; Compare 0 Set Maskc0_tog equ 40h ; Compare 0 Toggle Maskc0_res equ 80h ; Compare 0 Reset Maskc0_nop equ 0C0h ; Compare 0 NOP MaskT_FLAGR reg R254 ; MFTimer Flags Register__defbit T_ao,T_FLAGR,0 ; AND/OR on Capture Interrupt__defbit T_ocm0,T_FLAGR,1 ; Overrun Compare 0__defbit T_ocp0,T_FLAGR,2 ; Overrun Capture 0__defbit T_ouf,T_FLAGR,3 ; Overflow Underflow Flag__defbit T_cm1,T_FLAGR,4 ; Successful Compare 1__defbit T_cm0,T_FLAGR,5 ; Successful Compare 0__defbit T_cp1,T_FLAGR,6 ; Successful Capture 1__defbit T_cp0,T_FLAGR,7 ; Successful Capture 0T_IDMR equ R255 ; MFTimer Interrupt DMA Mask Register__defbit T_oui,T_IDMR,0 ; Overflow Underflow Interrupt__defbit T_cm1i,T_IDMR,1 ; Compare 1 Interrupt__defbit T_cm0i,T_IDMR,2 ; Compare 0 Interrupt__defbit T_cm0d,T_IDMR,3 ; Compare 0 DMA__defbit T_cp1i,T_IDMR,4 ; Capture 1 Interrupt__defbit T_cp0i,T_IDMR,5 ; Capture 0 Interrupt__defbit T_cp0d,T_IDMR,6 ; Capture 0 DMA__defbit T_gtien,T_IDMR,7 ; Global Timer Interrupt EnableT0_DCPR reg R240 ; MFTimer 0 DMA Counter Pointer RegisterT1_DCPR reg R244 ; MFTimer 1 DMA Counter Pointer RegisterT0_DAPR reg R241 ; MFTimer 0 DMA Address Pointer RegisterT1_DAPR reg R245 ; MFTimer 1 DMA Address Pointer RegisterT0_IVR reg R242 ; MFTimer 0 Interrupt Vector RegisterT1_IVR reg R246 ; MFTimer 1 Interrupt Vector RegisterT0_IDCR reg R243 ; MFTimer 0 Interrupt/DMA Control RegisterT1_IDCR reg R247 ; MFTimer 1 Interrupt/DMA Control RegisterT2_DCPR reg R240 ; MFTimer 2 DMA Counter Pointer RegisterT3_DCPR reg R244 ; MFTimer 3 DMA Counter Pointer RegisterT2_DAPR reg R241 ; MFTimer 2 DMA Address Pointer RegisterT3_DAPR reg R245 ; MFTimer 3 DMA Address Pointer RegisterT2_IVR reg R242 ; MFTimer 2 Interrupt Vector RegisterT3_IVR reg R246 ; MFTimer 3 Interrupt Vector RegisterT2_IDCR reg R243 ; MFTimer 2 Interrupt/DMA Control RegisterT3_IDCR reg R247 ; MFTimer 3 Interrupt/DMA Control Registerplm equ 07h ; Priority Level Maskswen equ 08h ; Swap Function Enable Maskdctd equ 10h ; DMA Compare Transaction Destination Maskdcts equ 20h ; DMA Capture Transaction Source Maskcme equ 40h ; Compare 0 End of Block Maskcpe equ 80h ; Capture 0 End of Block MaskT_IOCR reg R248 ; MFTimer I/O Connection Registersc0 equ 01h ; TxOUTA and TxINA Connection Bit (even)sc1 equ 02h ; TxOUTA and TxINA Connection Bit (odd);----------------------------------------------------------------------------; AD Converterif MOMCPUNAME<>"ST9020"AD0_PG equ 63 ; A/D Converter Registers PageAD1_PG equ 62 ; Second A/D unitAD_D0R reg R240 ; Channel 0 Data RegisterAD_D1R reg R241 ; Channel 1 Data RegisterAD_D2R reg R242 ; Channel 2 Data RegisterAD_D3R reg R243 ; Channel 3 Data RegisterAD_D4R reg R244 ; Channel 4 Data RegisterAD_D5R reg R245 ; Channel 5 Data RegisterAD_D6R reg R246 ; Channel 6 Data RegisterAD_D7R reg R247 ; Channel 7 Data RegisterAD_LT6R reg R248 ; Channel 6 Lower Threshold RegisterAD_LT7R reg R249 ; Channel 7 Lower Threshold RegisterAD_UT6R reg R250 ; Channel 6 Upper Threshold RegisterAD_UT7R reg R251 ; Channel 7 Upper Threshold RegisterAD_CRR reg R252 ; Compare Result Register__defbit AD_c6l,AD_CRR,4 ; Compare Channel 6 Lower Bit__defbit AD_c7l,AD_CRR,5 ; Compare Channel 7 Lower Bit__defbit AD_c6u,AD_CRR,6 ; Compare Channel 6 Upper Bit__defbit AD_c7u,AD_CRR,7 ; Compare Channel 7 Upper BitAD_CLR reg R253 ; Control Logic Register__defbit AD_st,AD_CLR,0 ; Start/Stop Bit__defbit AD_cont,AD_CLR,1 ; Continuous Mode__defbit AD_pow,AD_CLR,2 ; Power Up/Down Control__defbit AD_intg,AD_CLR,3 ; Internal Trigger__defbit AD_extg,AD_CLR,4 ; External Triggersch equ 0E0h ; Scan Channel Selection MaskAD_ICR reg R254 ; Interrupt Control Register__defbit AD_awdi,AD_ICR,4 ; Analog Watchdog Interrupt__defbit AD_eci,AD_ICR,5 ; End of Count Interrupt__defbit AD_awd,AD_ICR,6 ; Analog Watchdog Pending Flag__defbit AD_ecv,AD_ICR,7 ; End of conversion Pending FlagAD_prl equ 07h ; Priority Level MaskAD_IVR reg R255 ; Interrupt Vector Registerendif;----------------------------------------------------------------------------; Serial InterfaceSCI1_PG equ 24 ; SCI1 Control Registers PageSCI2_PG equ 25 ; SCI2 Control Registers PageSCI3_PG equ 26 ; SCI3 Control Registers PageSCI4_PG equ 27 ; SCI4 Control Registers PageS_RDCPR reg R240 ; Receive DMA Counter Pointer RegisterS_RDAPR reg R241 ; Receive DMA Address Pointer RegisterS_TDCPR reg R242 ; Transmit DMA Counter Pointer RegisterS_TDAPR reg R243 ; Transmit DMA address Pointer RegisterS_IVR reg R244 ; Interrupt Vector RegisterS_ACR reg R245 ; Address Compare RegisterS_IMR reg R246 ; Interrupt Mask Register__defbit S_txdi,S_IMR,0 ; Transmitter Data Interrupt__defbit S_rxdi,S_IMR,1 ; Receiver Data Interrupt__defbit S_rxb,S_IMR,2 ; Receiver Break__defbit S_rxa,S_IMR,3 ; Receiver Address__defbit S_rxe,S_IMR,4 ; Receiver Error__defbit S_txeob,S_IMR,5 ; Transmit End of Block__defbit S_rxeob,S_IMR,6 ; Receive End of Block__defbit S_hsn,S_IMR,7 ; Holding or Shift Register EmptyS_ISR reg R247 ; Interrupt Status Register__defbit S_txsem,S_ISR,0 ; Transmit Shift Register Empty__defbit S_txhem,S_ISR,1 ; Transmit Hold Register Empty__defbit S_rxdp,S_ISR,2 ; Received Data Pending Bit__defbit S_rxbp,S_ISR,3 ; Received Break Pending Bit__defbit S_rxap,S_ISR,4 ; Received Address Pending Bit__defbit S_pe,S_ISR,5 ; Parity Error Pending Bit__defbit S_fe,S_ISR,6 ; Framing Error Pending Bit__defbit S_oe,S_ISR,7 ; Overrun Error Pending BitS_RXBR reg R248 ; Receive Buffer RegisterS_TXBR reg R248 ; Transmit Buffer RegisterS_IDPR reg R249 ; Interrupt/DMA Priority Register__defbit S_txd,S_IDPR,3 ; Transmitter DMA__defbit S_rxd,S_IDPR,4 ; Receiver DMA__defbit S_sa,S_IDPR,5 ; Set Address__defbit S_sb,S_IDPR,6 ; Set Break__defbit S_amen,S_IDPR,7 ; Address Mode EnableS_pri equ 07h ; Interrupt/DMA Priority MaskS_CHCR reg R250 ; Character Configuration Registerwl5 equ 000h ; 5 Bits Data Word Maskwl6 equ 001h ; 6 Bits Data Word Maskwl7 equ 002h ; 7 Bits Data Word Maskwl8 equ 003h ; 8 Bits Data Word Masksb10 equ 000h ; 1.0 Stop Bit Masksb15 equ 004h ; 1.5 Stop Bit Masksb20 equ 008h ; 2.0 Stop Bit Masksb25 equ 00Ch ; 2.5 Stop Bit Maskab equ 010h ; Address Bit Insertion Maskpen equ 020h ; Parity Enable Maskep equ 040h ; Even Parity Maskoddp equ 000h ; Odd Parity Maskam equ 080h ; Address Mode MaskS_CCR reg R251 ; Clock Configuration Register__defbit S_stpen,S_CCR,0 ; Stick Parity Enable__defbit S_lben,S_CCR,1 ; Loop Back Enable__defbit S_aen,S_CCR,2 ; Auto Echo Enable__defbit S_cd,S_CCR,3 ; Clock Divider__defbit S_xbrg,S_CCR,4 ; External Baud Rate Generator Source__defbit S_xrx,S_CCR,5 ; External Receiver Source__defbit S_oclk,S_CCR,6 ; Output Clock Selection__defbit S_txclk,S_CCR,7 ; Transmit Clock SelectionS_BRGR reg RR252 ; Baud Rate Generator RegisterS_BRGHR reg R252 ; Baud Rate Generator Register HighS_BRGLR reg R253 ; Baud Rate Generator Register Low;----------------------------------------------------------------------------; Security Registers:SEC_PG equ 59 ; Security Register PageSECR reg R255__defbit tlck,SECR,0 ; Test Lock Bit__defbit wf1,SECR,1 ; Write Fuse 1 Bit__defbit hlck,SECR,2 ; Hardware Lock Bit__defbit wf2,SECR,3 ; Write Fuse 2 Bit__defbit f2tst,SECR,4 ; Select Fuse 2 Bit__defbit slck,SECR,7 ; Software Lock Bit;----------------------------------------------------------------------------endif ; regst9increstore ; re-enable listing