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ifndef regcop8inc ; avoid multiple inclusionregcop8inc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File REGCOP8.INC *;* *;* Contains Register Definitions for COP8 Controllers *;* *;****************************************************************************if MOMPASS=1switch MOMCPUNAMEcase "COP87L84"message "including COP87L84-registers"elsecasefatal "invalid processor type: only COP87L84 allowed"endcaseendif;----------------------------------------------------------------------------; Processor Core__REG set 0rept 10R{"\{__REG}"} equ __REG+0xf0__REG set __REG+1,dataendmrept 6R1{"\{__REG-10}"} equ __REG+0xf0__REG set __REG+1,dataendmpsw sfr 0xef ; Flagsgie equ 0 ; Global Interrupt Enableexen equ 1 ; External Interrupt Enablebusy equ 2 ; Microwire Busyexpnd equ 3 ; External Interrupt Pendingt1ena equ 4 ; Timer 1 Interrupt Enablet1pnda equ 5 ; Timer 1 Interrupt Pendingc equ 6 ; Carryhc equ 7 ; Half Carryx sfr 0xfc ; X-Registersp sfr 0xfd ; Stack Pointerb sfr 0xfe ; B Register;----------------------------------------------------------------------------; Peripheral Control Registerscntrl sfr 0xee ; Globale Controlsl0 equ 0 ; Microwire Clock Dividersl1 equ 1iedg equ 2 ; External Interrupt Edge Selectmsel equ 3 ; Microwire use G4/G5t1c0 equ 4 ; Timer 1 Interrupt/Start-Stopt1c1 equ 5 ; Timer 1 Mode Selectt1c2 equ 6t1c3 equ 7icntrl sfr 0xe8 ; Continuation...t1enb equ 0 ; Timer 1 Capture Interrupt Enablet1pndb equ 1 ; Timer 1 Capture Interrupt Pendinguwen equ 2 ; MicroWire-Interrupt Enableuwpnd equ 3 ; MicroWire-Interrupt Pendingt0en equ 4 ; Timer 0 Interrupt Enablet0pndb equ 5 ; Timer 0 Interrupt Pendinglpen equ 6 ; Port L-Interrupt Enable;----------------------------------------------------------------------------; Timert1rblo sfr 0xe6 ; Timer 1 Reload Value Bt1rbhi sfr 0xe7tmr1lo sfr 0xea ; Timer 1 Count Valuetmr1hi sfr 0xebt1ralo sfr 0xec ; Timer 1 Reload Value Bt1rahi sfr 0xed;----------------------------------------------------------------------------; PWMpscal sfr 0xa0 ; PWM Prescalerrlon sfr 0xa1 ; PWM Duty Cyclepwmcon sfr 0xa2 ; PWM Controlpwen0 equ 0 ; PWM0 Output to I/O Portpwen1 equ 1 ; PWM1 Output to I/O Portpwon equ 2 ; PWM Start/Stoppwmd equ 3 ; PWM Modepwie equ 4 ; PWM Interrupt Enablepwpnd equ 5 ; PWM Interrupt Pendingesel equ 6 ; PWM Edge Select;----------------------------------------------------------------------------; MicroWire Interfacewkedg sfr 0xc8wken sfr 0xc9wkpnd sfr 0xcasior sfr 0xe9 ; Shift register;----------------------------------------------------------------------------; CAN Interfacetxd1 sfr 0xb0 ; Transmit Data (Byte 1,3,5,7,...)txd2 sfr 0xb1 ; Transmit Data (Byte 2,4,6,8,...)tdlc sfr 0xb2 ; Transmit Length/Identifier(L) Registertdlc0 equ 0 ; Transmit Lengthtdlc1 equ 1tdlc2 equ 2tdlc3 equ 3tid0 equ 4 ; Transmit Identification (Bits 0..3)tid1 equ 5tid2 equ 6tid3 equ 7tid sfr 0xb3 ; Transmit Identification Registertid4 equ 0 ; Transmit Identification (Bits 4..10)tid5 equ 1tid6 equ 2tid7 equ 3tid8 equ 4tid9 equ 5tid10 equ 6trtr equ 7 ; Transmit Frame Remoterxd1 sfr 0xb4 ; Receive Data (Byte 1,3,5,7,...)rxd2 sfr 0xb5 ; Receive Data (Byte 2,4,6,8,...)ridl sfr 0xb6 ; Receive Length/Identifier(L) Registerrdlc0 equ 0 ; Receive Lengthrdlc1 equ 1rdlc2 equ 2rdlc3 equ 3rid0 equ 4 ; Receive Identification (Bits 0..3)rid1 equ 5rid2 equ 6rid3 equ 7rid sfr 0xb7 ; Receive Identification Registerrid4 equ 0 ; Receive Identification (Bits 4..10)rid5 equ 1rid6 equ 2rid7 equ 3rid8 equ 4rid9 equ 5rid10 equ 6cscal sfr 0xb8 ; CAN Clock Prescalerctim sfr 0xb9 ; CAN Bus Timing Registerps0 equ 2 ; Phase Segmentps1 equ 3ps2 equ 4pps0 equ 5 ; Propagation Segmentpps1 equ 6pps2 equ 7cbus sfr 0xba ; CAN Bus Timing Registerfmod equ 1 ; Fault Confinement Moderxred0 equ 2 ; Apply Reference Voltage to Rx0rxref1 equ 3 ; Apply Reference Voltage to Tx0txen0 equ 4 ; Enable TxD Output Driverstxen1 equ 5riaf equ 6 ; Receive Filter Enabletcntl sfr 0xbb ; CAN Bus Control/Status Registertxss equ 0 ; Transmitter Start/Stoprie equ 1 ; Receive Interrupt Enabletie equ 2 ; Transmit Interrupt Enableceie equ 3 ; CAN Interrupt Enablererr equ 4 ; Receive Errorterr equ 5 ; Transmit Errorns0 equ 6 ; Node Statens1 equ 7rtstat sfr 0xbc ; CAN Bus Transmitter/Receiver Staterbf equ 0 ; Receive Buffer Fullrcv equ 1 ; Reception Runningrfv equ 2 ; Received Frame Validrorn equ 3 ; Receiver Overflowrold equ 4 ; Receiver Frame Overflowrrtr equ 5 ; Remote-Bit Set in Received Frametxpnd equ 6 ; Transmission Pendingtbe equ 7 ; Transmit Buffer Emptytec sfr 0xbd ; Transmit Error Counterrec sfr 0xbe ; Receive Error Counter;----------------------------------------------------------------------------; Comparatorscmpsl sfr 0xd3 ; Comparator Control Registercmp1en equ 1 ; Comparator 1 Enablecmp1rd equ 2 ; Comparator 1 Output Valuecmp1oe equ 3 ; Comparator 1 Output Enablecmp2en equ 4 ; Comparator 2 Enablecmp2rd equ 5 ; Comparator 2 Output Valuecmp2oe equ 6 ; Comparator 2 Output Enablecmp2sel equ 7 ; Comparator 2 Output on L3/L5;----------------------------------------------------------------------------; Portsportld sfr 0xd0 ; Port L Output Registerportlc sfr 0xd1 ; Port L Configuration Registerportlp sfr 0xd2 ; Port L Input Registerportgd sfr 0xd4 ; Port G Output Registerportgc sfr 0xd5 ; Port G Configuration Registerportgp sfr 0xd6 ; Port G Input Registerportd sfr 0xdc ; Port D Output Register;----------------------------------------------------------------------------; Vector Addresses;----------------------------------------------------------------------------; Memory Addressesiram sfr 0x00 ; Internal RAM Areairamend sfr 0x2f;----------------------------------------------------------------------------restore ; re-enable listingendif ; regcop8inc