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  1. /* code601.c */
  2. /*****************************************************************************/
  3. /* SPDX-License-Identifier: GPL-2.0-only OR GPL-3.0-only                     */
  4. /*                                                                           */
  5. /* AS-Portierung                                                             */
  6. /*                                                                           */
  7. /* Codegenerator PowerPC-Familie                                             */
  8. /*                                                                           */
  9. /*****************************************************************************/
  10.  
  11. #include "stdinc.h"
  12. #include <string.h>
  13. #include <ctype.h>
  14.  
  15. #include "be_le.h"
  16. #include "strutil.h"
  17. #include "asmdef.h"
  18. #include "asmsub.h"
  19. #include "asmpars.h"
  20. #include "asmallg.h"
  21. #include "onoff_common.h"
  22. #include "asmitree.h"
  23. #include "intpseudo.h"
  24. #include "codevars.h"
  25. #include "headids.h"
  26. #include "errmsg.h"
  27.  
  28. #include "code601.h"
  29.  
  30. typedef struct
  31. {
  32.   const char *Name;
  33.   LongWord Code;
  34.   Byte CPUMask;
  35. } BaseOrder;
  36.  
  37. static BaseOrder *FixedOrders;
  38. static BaseOrder *Reg1Orders;
  39. static BaseOrder *CReg1Orders;
  40. static BaseOrder *CBit1Orders;
  41. static BaseOrder *FReg1Orders;
  42. static BaseOrder *Reg2Orders;
  43. static BaseOrder *CReg2Orders;
  44. static BaseOrder *FReg2Orders;
  45. static BaseOrder *Reg2BOrders;
  46. static BaseOrder *Reg2SwapOrders;
  47. static BaseOrder *NoDestOrders;
  48. static BaseOrder *Reg3Orders;
  49. static BaseOrder *CReg3Orders;
  50. static BaseOrder *FReg3Orders;
  51. static BaseOrder *Reg3SwapOrders;
  52. static BaseOrder *MixedOrders;
  53. static BaseOrder *FReg4Orders;
  54. static BaseOrder *RegDispOrders;
  55. static BaseOrder *FRegDispOrders;
  56. static BaseOrder *Reg2ImmOrders;
  57. static BaseOrder *Imm16Orders;
  58. static BaseOrder *Imm16SwapOrders;
  59.  
  60. static CPUVar CPU403, CPU403C, CPU505, CPU601, CPU821, CPU6000;
  61.  
  62. #define M_403 0x01
  63. #define M_403C 0x02
  64. #define M_505 0x04
  65. #define M_601 0x08
  66. #define M_821 0x10
  67. #define M_6000 0x20
  68. #define M_SUP 0x80
  69.  
  70. #ifdef __STDC__
  71. #define T1  1lu
  72. #define T3  3lu
  73. #define T4  4lu
  74. #define T7  7lu
  75. #define T8  8lu
  76. #define T9  9lu
  77. #define T10 10lu
  78. #define T11 11lu
  79. #define T12 12lu
  80. #define T13 13lu
  81. #define T14 14lu
  82. #define T15 15lu
  83. #define T16 16lu
  84. #define T17 17lu
  85. #define T18 18lu
  86. #define T19 19lu
  87. #define T20 20lu
  88. #define T21 21lu
  89. #define T22 22lu
  90. #define T23 23lu
  91. #define T24 24lu
  92. #define T25 25lu
  93. #define T26 26lu
  94. #define T27 27lu
  95. #define T28 28lu
  96. #define T29 29lu
  97. #define T31 31lu
  98. #define T32 32lu
  99. #define T33 33lu
  100. #define T34 34lu
  101. #define T35 35lu
  102. #define T36 36lu
  103. #define T37 37lu
  104. #define T38 38lu
  105. #define T39 39lu
  106. #define T40 40lu
  107. #define T41 41lu
  108. #define T42 42lu
  109. #define T43 43lu
  110. #define T44 44lu
  111. #define T45 45lu
  112. #define T46 46lu
  113. #define T47 47lu
  114. #define T48 48lu
  115. #define T49 49lu
  116. #define T50 50lu
  117. #define T51 51lu
  118. #define T52 52lu
  119. #define T53 53lu
  120. #define T54 54lu
  121. #define T55 55lu
  122. #define T59 59lu
  123. #define T63 63lu
  124. #else
  125. #define T1  1l
  126. #define T3  3l
  127. #define T4  4l
  128. #define T7  7l
  129. #define T8  8l
  130. #define T9  9l
  131. #define T10 10l
  132. #define T11 11l
  133. #define T12 12l
  134. #define T13 13l
  135. #define T14 14l
  136. #define T15 15l
  137. #define T16 16l
  138. #define T17 17l
  139. #define T18 18l
  140. #define T19 19l
  141. #define T20 20l
  142. #define T21 21l
  143. #define T22 22l
  144. #define T23 23l
  145. #define T24 24l
  146. #define T25 25l
  147. #define T26 26l
  148. #define T27 27l
  149. #define T28 28l
  150. #define T29 29l
  151. #define T31 31l
  152. #define T32 32l
  153. #define T33 33l
  154. #define T34 34l
  155. #define T35 35l
  156. #define T36 36l
  157. #define T37 37l
  158. #define T38 38l
  159. #define T39 39l
  160. #define T40 40l
  161. #define T41 41l
  162. #define T42 42l
  163. #define T43 43l
  164. #define T44 44l
  165. #define T45 45l
  166. #define T46 46l
  167. #define T47 47l
  168. #define T48 48l
  169. #define T49 49l
  170. #define T50 50l
  171. #define T51 51l
  172. #define T52 52l
  173. #define T53 53l
  174. #define T54 54l
  175. #define T55 55l
  176. #define T59 59l
  177. #define T63 63l
  178. #endif
  179.  
  180. static char ZeroStr[] = "0";
  181. static const tStrComp ZeroComp = { { -1, 0 }, {0, ZeroStr, 0} };
  182.  
  183. /*-------------------------------------------------------------------------*/
  184.  
  185. static void PutCode(LongWord Code)
  186. {
  187. #if 0
  188.   memcpy(BAsmCode, &Code, 4);
  189.   if (!TargetBigEndian)
  190.     DSwap((void *)BAsmCode, 4);
  191. #endif
  192.   DAsmCode[0] = Code;
  193. }
  194.  
  195. /*-------------------------------------------------------------------------*/
  196.  
  197. /*!------------------------------------------------------------------------
  198.  * \fn     DecodeGenRegCore(const char *pArg, LongWord *pValue)
  199.  * \brief  check whether argument is general register
  200.  * \param  pArg source argument
  201.  * \param  pValue register # if it's a register
  202.  * \return True if it's a register
  203.  * ------------------------------------------------------------------------ */
  204.  
  205. static Boolean DecodeGenRegCore(const char *pArg, LongWord *pValue)
  206. {
  207.   if ((strlen(pArg) < 2) || (as_toupper(*pArg) != 'R'))
  208.     return False;
  209.   else
  210.   {
  211.     Boolean OK;
  212.  
  213.     *pValue = ConstLongInt(pArg + 1, &OK, 10);
  214.     return (OK && (*pValue <= 31));
  215.   }
  216. }
  217.  
  218. /*!------------------------------------------------------------------------
  219.  * \fn     DecodeFPRegCore(const char *pArg, LongWord *pValue)
  220.  * \brief  check whether argument is floating point register
  221.  * \param  pArg source argument
  222.  * \param  pValue register # if it's a register
  223.  * \return True if it's a register
  224.  * ------------------------------------------------------------------------ */
  225.  
  226. static Boolean DecodeFPRegCore(const char *pArg, LongWord *pValue)
  227. {
  228.   if ((strlen(pArg) < 3) || (as_toupper(*pArg) != 'F') || (as_toupper(pArg[1]) != 'R'))
  229.     return False;
  230.   else
  231.   {
  232.     Boolean OK;
  233.  
  234.     *pValue = ConstLongInt(pArg + 2, &OK, 10);
  235.     return OK && (*pValue <= 31);
  236.   }
  237. }
  238.  
  239. /*!------------------------------------------------------------------------
  240.  * \fn     DecodeGenReg(const tStrComp *pArg, LongWord *pValue)
  241.  * \brief  check whether argument is general register, including aliases
  242.  * \param  pArg source argument
  243.  * \param  pValue register # if it's a register
  244.  * \return True if it's a register
  245.  * ------------------------------------------------------------------------ */
  246.  
  247. static Boolean DecodeGenReg(const tStrComp *pArg, LongWord *pValue)
  248. {
  249.   tRegDescr RegDescr;
  250.   tEvalResult EvalResult;
  251.   tRegEvalResult RegEvalResult;
  252.  
  253.   if (DecodeGenRegCore(pArg->str.p_str, pValue))
  254.     return True;
  255.  
  256.   RegEvalResult = EvalStrRegExpressionAsOperand(pArg, &RegDescr, &EvalResult, eSymbolSize32Bit, True);
  257.   *pValue = RegDescr.Reg;
  258.   return (RegEvalResult == eIsReg);
  259. }
  260.  
  261. /*!------------------------------------------------------------------------
  262.  * \fn     DissectReg_601(char *pDest, size_t DestSize, tRegInt Value, tSymbolSize InpSize)
  263.  * \brief  dissect register symbols - PPC variant
  264.  * \param  pDest destination buffer
  265.  * \param  DestSize destination buffer size
  266.  * \param  Value numeric register value
  267.  * \param  InpSize register size
  268.  * ------------------------------------------------------------------------ */
  269.  
  270. static void DissectReg_601(char *pDest, size_t DestSize, tRegInt Value, tSymbolSize InpSize)
  271. {
  272.   switch (InpSize)
  273.   {
  274.     case eSymbolSize32Bit:
  275.       as_snprintf(pDest, DestSize, "R%u", (unsigned)Value);
  276.       break;
  277.     case eSymbolSizeFloat64Bit:
  278.       as_snprintf(pDest, DestSize, "FR%u", (unsigned)Value);
  279.       break;
  280.     default:
  281.       as_snprintf(pDest, DestSize, "%d-%u", (int)InpSize, (unsigned)Value);
  282.   }
  283. }
  284.  
  285. /*!------------------------------------------------------------------------
  286.  * \fn     DecodeFPReg(const tStrComp *pArg, LongWord *pValue)
  287.  * \brief  check whether argument is floating point register, including aliases
  288.  * \param  pArg source argument
  289.  * \param  pValue register # if it's a register
  290.  * \return True if it's a register
  291.  * ------------------------------------------------------------------------ */
  292.  
  293. static Boolean DecodeFPReg(const tStrComp *pArg, LongWord *pValue)
  294. {
  295.   tRegDescr RegDescr;
  296.   tEvalResult EvalResult;
  297.   tRegEvalResult RegEvalResult;
  298.  
  299.   if (DecodeFPRegCore(pArg->str.p_str, pValue))
  300.     return True;
  301.  
  302.   RegEvalResult = EvalStrRegExpressionAsOperand(pArg, &RegDescr, &EvalResult, eSymbolSizeFloat64Bit, True);
  303.   *pValue = RegDescr.Reg;
  304.   return (RegEvalResult == eIsReg);
  305. }
  306.  
  307. static Boolean DecodeCondReg(const tStrComp *pComp, LongWord *Erg)
  308. {
  309.   Boolean OK, Result;
  310.  
  311.   *Erg = EvalStrIntExpression(pComp, UInt3, &OK) << 2;
  312.   Result = (OK && (*Erg <= 31));
  313.   if (!Result)
  314.     WrStrErrorPos(ErrNum_InvAddrMode, pComp);
  315.   return Result;
  316. }
  317.  
  318. static Boolean DecodeCondBit(const tStrComp *pComp, LongWord *Erg)
  319. {
  320.   Boolean OK, Result;
  321.  
  322.   *Erg = EvalStrIntExpression(pComp, UInt5, &OK);
  323.   Result = (OK && (*Erg <= 31));
  324.   if (!Result)
  325.     WrStrErrorPos(ErrNum_InvAddrMode, pComp);
  326.   return Result;
  327. }
  328.  
  329. static Boolean DecodeRegDisp(tStrComp *pComp, LongWord *Erg)
  330. {
  331.   char *p;
  332.   int l = strlen(pComp->str.p_str);
  333.   LongInt Disp;
  334.   Boolean OK;
  335.   tStrComp DispArg, RegArg;
  336.  
  337.   if (pComp->str.p_str[l - 1] != ')')
  338.   {
  339.     WrStrErrorPos(ErrNum_InvAddrMode, pComp);
  340.     return False;
  341.   }
  342.   pComp->str.p_str[l - 1] = '\0';  l--;
  343.   p = pComp->str.p_str + l - 1;
  344.   while ((p >= pComp->str.p_str) && (*p != '('))
  345.     p--;
  346.   if (p < pComp->str.p_str)
  347.   {
  348.     WrStrErrorPos(ErrNum_InvAddrMode, pComp);
  349.     return False;
  350.   }
  351.   StrCompSplitRef(&DispArg, &RegArg, pComp, p);
  352.   if (!DecodeGenReg(&RegArg, Erg))
  353.     return False;
  354.   *p = '\0';
  355.   Disp = EvalStrIntExpression(&DispArg, Int16, &OK);
  356.   if (!OK)
  357.     return False;
  358.  
  359.   *Erg = (*Erg << 16) + (Disp & 0xffff);
  360.   return True;
  361. }
  362.  
  363. /*-------------------------------------------------------------------------*/
  364.  
  365. static LongWord ExtractPoint(Word Code)
  366. {
  367.   return (Code >> 15) & 1;
  368. }
  369.  
  370. static void ChkSup(void)
  371. {
  372.   if (!SupAllowed)
  373.     WrError(ErrNum_PrivOrder);
  374. }
  375.  
  376. static void SwapCode(LongWord *Code)
  377. {
  378.   *Code = ((*Code & 0x1f) << 5) | ((*Code >> 5) & 0x1f);
  379. }
  380.  
  381. /*-------------------------------------------------------------------------*/
  382.  
  383. /* ohne Argument */
  384.  
  385. static void DecodeFixed(Word Index)
  386. {
  387.   const BaseOrder *pOrder = FixedOrders + Index;
  388.  
  389.   if (ChkArgCnt(0, 0)
  390.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0))
  391.   {
  392.     CodeLen = 4;
  393.     PutCode(pOrder->Code);
  394.     if (pOrder->CPUMask & M_SUP)
  395.       ChkSup();
  396.   }
  397. }
  398.  
  399. /* ein Register */
  400.  
  401. static void DecodeReg1(Word Index)
  402. {
  403.   const BaseOrder *pOrder = Reg1Orders + Index;
  404.   LongWord Dest;
  405.  
  406.   if (ChkArgCnt(1, 1)
  407.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  408.    && DecodeGenReg(&ArgStr[1], &Dest))
  409.   {
  410.     CodeLen = 4;
  411.     PutCode(pOrder->Code + (Dest << 21));
  412.     if (pOrder->CPUMask & M_SUP)
  413.       ChkSup();
  414.   }
  415. }
  416.  
  417. /* ein Steuerregister */
  418.  
  419. static void DecodeCReg1(Word Index)
  420. {
  421.   const BaseOrder *pOrder = CReg1Orders + Index;
  422.   LongWord Dest;
  423.  
  424.   if (!ChkArgCnt(1, 1));
  425.   else if (ChkExactCPUMask(pOrder->CPUMask, CPU403) < 0);
  426.   else if (!DecodeCondReg(&ArgStr[1], &Dest));
  427.   else if (Dest & 3) WrStrErrorPos(ErrNum_AddrMustBeAligned, &ArgStr[1]);
  428.   else
  429.   {
  430.     CodeLen = 4;
  431.     PutCode(pOrder->Code + (Dest << 21));
  432.   }
  433. }
  434.  
  435. /* ein Steuerregisterbit */
  436.  
  437. static void DecodeCBit1(Word Index)
  438. {
  439.   const BaseOrder *pOrder = CBit1Orders + Index;
  440.   LongWord Dest;
  441.  
  442.   if (ChkArgCnt(1, 1)
  443.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  444.    && DecodeCondBit(&ArgStr[1], &Dest))
  445.   {
  446.     CodeLen = 4;
  447.     PutCode(pOrder->Code + (Dest << 21));
  448.   }
  449. }
  450.  
  451. /* ein Gleitkommaregister */
  452.  
  453. static void DecodeFReg1(Word Index)
  454. {
  455.   const BaseOrder *pOrder = FReg1Orders + Index;
  456.   LongWord Dest;
  457.  
  458.   if (ChkArgCnt(1, 1)
  459.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  460.    && DecodeFPReg(&ArgStr[1], &Dest))
  461.   {
  462.     CodeLen = 4;
  463.     PutCode(pOrder->Code + (Dest << 21));
  464.   }
  465. }
  466.  
  467. /* 1/2 Integer-Register */
  468.  
  469. static void DecodeReg2(Word Index)
  470. {
  471.   const BaseOrder *pOrder = Reg2Orders + Index;
  472.   LongWord Dest, Src1;
  473.   const tStrComp *pArg2 = (ArgCnt == 2) ? &ArgStr[2] : &ArgStr[1];
  474.  
  475.   if (ChkArgCnt(1, 2)
  476.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  477.    && DecodeGenReg(&ArgStr[1], &Dest)
  478.    && DecodeGenReg(pArg2, &Src1))
  479.   {
  480.     CodeLen = 4;
  481.     PutCode(pOrder->Code + (Dest << 21) + (Src1 << 16));
  482.   }
  483. }
  484.  
  485. /* 2 Bedingungs-Bits */
  486.  
  487. static void DecodeCReg2(Word Index)
  488. {
  489.   const BaseOrder *pOrder = CReg2Orders + Index;
  490.   LongWord Dest, Src1;
  491.  
  492.   if (!ChkArgCnt(2, 2));
  493.   else if (ChkExactCPUMask(pOrder->CPUMask, CPU403) < 0);
  494.   else if (!DecodeCondReg(&ArgStr[1], &Dest));
  495.   else if (Dest & 3) WrStrErrorPos(ErrNum_AddrMustBeAligned, &ArgStr[1]);
  496.   else if (!DecodeCondReg(&ArgStr[2], &Src1));
  497.   else if (Src1 & 3) WrStrErrorPos(ErrNum_AddrMustBeAligned, &ArgStr[2]);
  498.   else
  499.   {
  500.     CodeLen = 4;
  501.     PutCode(pOrder->Code + (Dest << 21) + (Src1 << 16));
  502.   }
  503. }
  504.  
  505. /* 1/2 Float-Register */
  506.  
  507. static void DecodeFReg2(Word Index)
  508. {
  509.   const BaseOrder *pOrder = FReg2Orders + Index;
  510.   LongWord Dest, Src1;
  511.   const tStrComp *pArg2 = (ArgCnt == 2) ? &ArgStr[2] : &ArgStr[1];
  512.  
  513.   if (ChkArgCnt(1, 2)
  514.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  515.    && DecodeFPReg(&ArgStr[1], &Dest)
  516.    && DecodeFPReg(pArg2, &Src1))
  517.   {
  518.     CodeLen = 4;
  519.     PutCode(pOrder->Code + (Dest << 21) + (Src1 << 11));
  520.   }
  521. }
  522.  
  523. /* 1/2 Integer-Register, Quelle in B */
  524.  
  525. static void DecodeReg2B(Word Index)
  526. {
  527.   const BaseOrder *pOrder = Reg2BOrders + Index;
  528.   LongWord Dest, Src1;
  529.   const tStrComp *pArg2 = (ArgCnt == 2) ? &ArgStr[2] : &ArgStr[1];
  530.  
  531.   if (ChkArgCnt(1, 2)
  532.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  533.    && DecodeGenReg(&ArgStr[1], &Dest)
  534.    && DecodeGenReg(pArg2, &Src1))
  535.   {
  536.     CodeLen = 4;
  537.     PutCode(pOrder->Code + (Dest << 21) + (Src1 << 11));
  538.     ChkSup();
  539.   }
  540. }
  541.  
  542. /* 1/2 Integer-Register, getauscht */
  543.  
  544. static void DecodeReg2Swap(Word Index)
  545. {
  546.   const BaseOrder *pOrder = Reg2SwapOrders + Index;
  547.   LongWord Dest, Src1;
  548.   const tStrComp *pArg2 = (ArgCnt == 2) ? &ArgStr[2] : &ArgStr[1];
  549.  
  550.   if (ChkArgCnt(1, 2)
  551.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  552.    && DecodeGenReg(&ArgStr[1], &Dest)
  553.    && DecodeGenReg(pArg2, &Src1))
  554.   {
  555.     CodeLen = 4;
  556.     PutCode(pOrder->Code + (Dest << 16) + (Src1 << 21));
  557.   }
  558. }
  559.  
  560. /* 2 Integer-Register, kein Ziel */
  561.  
  562. static void DecodeNoDest(Word Index)
  563. {
  564.   const BaseOrder *pOrder = NoDestOrders + Index;
  565.   LongWord Src2, Src1;
  566.  
  567.   if (ChkArgCnt(2, 2)
  568.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  569.    && DecodeGenReg(&ArgStr[1], &Src1)
  570.    && DecodeGenReg(&ArgStr[2], &Src2))
  571.   {
  572.     CodeLen = 4;
  573.     PutCode(pOrder->Code + (Src1 << 16) + (Src2 << 11));
  574.   }
  575. }
  576.  
  577. /* 2/3 Integer-Register */
  578.  
  579. static void DecodeReg3(Word Index)
  580. {
  581.   const BaseOrder *pOrder = Reg3Orders + Index;
  582.   const tStrComp *pArg2 = (ArgCnt == 2) ? &ArgStr[1] : &ArgStr[2],
  583.                  *pArg3 = (ArgCnt == 2) ? &ArgStr[2] : &ArgStr[3];
  584.   LongWord Src2, Src1, Dest;
  585.  
  586.   if (ChkArgCnt(2, 3)
  587.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  588.    && DecodeGenReg(&ArgStr[1], &Dest)
  589.    && DecodeGenReg(pArg2, &Src1)
  590.    && DecodeGenReg(pArg3, &Src2))
  591.   {
  592.     CodeLen = 4;
  593.     PutCode(pOrder->Code + (Dest << 21) + (Src1 << 16) + (Src2 << 11));
  594.   }
  595. }
  596.  
  597. /* 2/3 Bedingungs-Bits */
  598.  
  599. static void DecodeCReg3(Word Index)
  600. {
  601.   const BaseOrder *pOrder = CReg3Orders + Index;
  602.   const tStrComp *pArg2 = (ArgCnt == 2) ? &ArgStr[1] : &ArgStr[2],
  603.                  *pArg3 = (ArgCnt == 2) ? &ArgStr[2] : &ArgStr[3];
  604.   LongWord Src2, Src1, Dest;
  605.  
  606.   if (ChkArgCnt(2, 3)
  607.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  608.    && DecodeCondBit(&ArgStr[1], &Dest)
  609.    && DecodeCondBit(pArg2, &Src1)
  610.    && DecodeCondBit(pArg3, &Src2))
  611.   {
  612.     CodeLen = 4;
  613.     PutCode(pOrder->Code + (Dest << 21) + (Src1 << 16) + (Src2 << 11));
  614.   }
  615. }
  616.  
  617. /* 2/3 Float-Register */
  618.  
  619. static void DecodeFReg3(Word Index)
  620. {
  621.   const BaseOrder *pOrder = FReg3Orders + Index;
  622.   const tStrComp *pArg2 = (ArgCnt == 2) ? &ArgStr[1] : &ArgStr[2],
  623.                  *pArg3 = (ArgCnt == 2) ? &ArgStr[2] : &ArgStr[3];
  624.   LongWord Src2, Src1, Dest;
  625.  
  626.   if (ChkArgCnt(2, 3)
  627.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  628.    && DecodeFPReg(&ArgStr[1], &Dest)
  629.    && DecodeFPReg(pArg2, &Src1)
  630.    && DecodeFPReg(pArg3, &Src2))
  631.   {
  632.     CodeLen = 4;
  633.     PutCode(pOrder->Code + (Dest << 21) + (Src1 << 16) + (Src2 << 11));
  634.   }
  635. }
  636.  
  637. /* 2/3 Integer-Register, Ziel & Quelle 1 getauscht */
  638.  
  639. static void DecodeReg3Swap(Word Index)
  640. {
  641.   const BaseOrder *pOrder = Reg3SwapOrders + Index;
  642.   const tStrComp *pArg2 = (ArgCnt == 2) ? &ArgStr[1] : &ArgStr[2],
  643.                  *pArg3 = (ArgCnt == 2) ? &ArgStr[2] : &ArgStr[3];
  644.   LongWord Src2, Src1, Dest;
  645.  
  646.   if (ChkArgCnt(2, 3)
  647.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  648.    && DecodeGenReg(&ArgStr[1], &Dest)
  649.    && DecodeGenReg(pArg2, &Src1)
  650.    && DecodeGenReg(pArg3, &Src2))
  651.   {
  652.     CodeLen = 4;
  653.     PutCode(pOrder->Code + (Dest << 16) + (Src1 << 21) + (Src2 << 11));
  654.   }
  655. }
  656.  
  657. /* 1 Float und 2 Integer-Register */
  658.  
  659. static void DecodeMixed(Word Index)
  660. {
  661.   const BaseOrder *pOrder = MixedOrders + Index;
  662.   LongWord Src2, Src1, Dest;
  663.  
  664.   if (ChkArgCnt(3, 3)
  665.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  666.    && DecodeFPReg(&ArgStr[1], &Dest)
  667.    && DecodeGenReg(&ArgStr[2], &Src1)
  668.    && DecodeGenReg(&ArgStr[3], &Src2))
  669.    {
  670.      CodeLen = 4;
  671.      PutCode(pOrder->Code + (Dest << 21) + (Src1 << 16) + (Src2 << 11));
  672.    }
  673.  }
  674.  
  675. /* 3/4 Float-Register */
  676.  
  677. static void DecodeFReg4(Word Index)
  678. {
  679.   const BaseOrder *pOrder = FReg4Orders + Index;
  680.   LongWord Src3, Src2, Src1, Dest;
  681.   const tStrComp *pArg2 = (ArgCnt == 3) ? &ArgStr[1] : &ArgStr[2],
  682.                  *pArg3 = (ArgCnt == 3) ? &ArgStr[2] : &ArgStr[3],
  683.                  *pArg4 = (ArgCnt == 3) ? &ArgStr[3] : &ArgStr[4];
  684.  
  685.   if (ChkArgCnt(3, 4)
  686.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  687.    && DecodeFPReg(&ArgStr[1], &Dest)
  688.    && DecodeFPReg(pArg2, &Src1)
  689.    && DecodeFPReg(pArg3, &Src3)
  690.    && DecodeFPReg(pArg4, &Src2))
  691.   {
  692.     CodeLen = 4;
  693.     PutCode(pOrder->Code + (Dest << 21) + (Src1 << 16) + (Src2 << 11) + (Src3 << 6));
  694.   }
  695. }
  696.  
  697. /* Register mit indiziertem Speicheroperanden */
  698.  
  699. static void DecodeRegDispOrder(Word Index)
  700. {
  701.   const BaseOrder *pOrder = RegDispOrders + Index;
  702.   LongWord Src1, Dest;
  703.  
  704.   if (ChkArgCnt(2, 2)
  705.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  706.    && DecodeGenReg(&ArgStr[1], &Dest)
  707.    && DecodeRegDisp(&ArgStr[2], &Src1))
  708.   {
  709.     PutCode(pOrder->Code + (Dest << 21) + Src1);
  710.     CodeLen = 4;
  711.   }
  712. }
  713.  
  714. /* Gleitkommaregister mit indiziertem Speicheroperandem */
  715.  
  716. static void DecodeFRegDisp(Word Index)
  717. {
  718.   const BaseOrder *pOrder = FRegDispOrders + Index;
  719.   LongWord Src1, Dest;
  720.  
  721.   if (ChkArgCnt(2, 2)
  722.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  723.    && DecodeFPReg(&ArgStr[1], &Dest)
  724.    && DecodeRegDisp(&ArgStr[2], &Src1))
  725.   {
  726.     PutCode(pOrder->Code + (Dest << 21) + Src1);
  727.     CodeLen = 4;
  728.   }
  729. }
  730.  
  731. /* 2 verdrehte Register mit immediate */
  732.  
  733. static void DecodeReg2Imm(Word Index)
  734. {
  735.   const BaseOrder *pOrder = Reg2ImmOrders + Index;
  736.   LongWord Src1, Dest, Src2;
  737.   Boolean OK;
  738.  
  739.   if (ChkArgCnt(3, 3)
  740.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  741.    && DecodeGenReg(&ArgStr[1], &Dest)
  742.    && DecodeGenReg(&ArgStr[2], &Src1))
  743.   {
  744.     Src2 = EvalStrIntExpression(&ArgStr[3], UInt5, &OK);
  745.     if (OK)
  746.     {
  747.       PutCode(pOrder->Code + (Src1 << 21) + (Dest << 16) + (Src2 << 11));
  748.       CodeLen = 4;
  749.     }
  750.   }
  751. }
  752.  
  753. /* 2 Register+immediate */
  754.  
  755. static void DecodeImm16(Word Index)
  756. {
  757.   const BaseOrder *pOrder = Imm16Orders + Index;
  758.   LongWord Src1, Dest, Imm;
  759.   Boolean OK;
  760.   const tStrComp *pArg2 = (ArgCnt == 2) ? &ArgStr[1] : &ArgStr[2],
  761.                  *pArg3 = (ArgCnt == 2) ? &ArgStr[2] : &ArgStr[3];
  762.  
  763.   if (ChkArgCnt(2, 3)
  764.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  765.    && DecodeGenReg(&ArgStr[1], &Dest)
  766.    && DecodeGenReg(pArg2, &Src1))
  767.   {
  768.     Imm = EvalStrIntExpression(pArg3, Int16, &OK);
  769.     if (OK)
  770.     {
  771.       CodeLen = 4;
  772.       PutCode(pOrder->Code + (Dest << 21) + (Src1 << 16) + (Imm & 0xffff));
  773.     }
  774.   }
  775. }
  776.  
  777. /* 2 Register+immediate, Ziel & Quelle 1 getauscht */
  778.  
  779. static void DecodeImm16Swap(Word Index)
  780. {
  781.   const BaseOrder *pOrder = Imm16SwapOrders + Index;
  782.   LongWord Src1, Dest, Imm;
  783.   Boolean OK;
  784.   const tStrComp *pArg2 = (ArgCnt == 2) ? &ArgStr[1] : &ArgStr[2],
  785.                  *pArg3 = (ArgCnt == 2) ? &ArgStr[2] : &ArgStr[3];
  786.  
  787.   if (ChkArgCnt(2, 3)
  788.    && (ChkExactCPUMask(pOrder->CPUMask, CPU403) >= 0)
  789.    && DecodeGenReg(&ArgStr[1], &Dest)
  790.    && DecodeGenReg(pArg2, &Src1))
  791.   {
  792.     Imm = EvalStrIntExpression(pArg3, Int16, &OK);
  793.     if (OK)
  794.     {
  795.       CodeLen = 4;
  796.       PutCode(pOrder->Code + (Dest << 16) + (Src1 << 21) + (Imm & 0xffff));
  797.     }
  798.   }
  799. }
  800.  
  801. /* Ausreisser... */
  802.  
  803. static void DecodeFMUL_FMULS(Word Code)
  804. {
  805.   const tStrComp *pArg2 = (ArgCnt == 2) ? &ArgStr[1] : &ArgStr[2],
  806.                  *pArg3 = (ArgCnt == 2) ? &ArgStr[2] : &ArgStr[3];
  807.   LongWord Dest, Src1, Src2, LCode = (Code & 0x7fff);
  808.  
  809.   if (ChkArgCnt(2, 3)
  810.    && DecodeFPReg(&ArgStr[1], &Dest)
  811.    && DecodeFPReg(pArg2, &Src1)
  812.    && DecodeFPReg(pArg3, &Src2))
  813.   {
  814.     PutCode((LCode << 26) + (25 << 1) + (Dest << 21) + (Src1 << 16) + (Src2 << 6) + ExtractPoint(Code));
  815.     CodeLen = 4;
  816.   }
  817. }
  818.  
  819. static void DecodeLSWI_STSWI(Word Code)
  820. {
  821.   LongWord Dest, Src1, Src2, LCode = Code;
  822.   Boolean OK;
  823.  
  824.   if (ChkArgCnt(3, 3)
  825.    && DecodeGenReg(&ArgStr[1], &Dest)
  826.    && DecodeGenReg(&ArgStr[2], &Src1))
  827.   {
  828.     Src2 = EvalStrIntExpression(&ArgStr[3], UInt5, &OK);
  829.     if (OK)
  830.     {
  831.       PutCode((T31 << 26) + (LCode << 1) + (Dest << 21) + (Src1 << 16) + (Src2 << 11));
  832.       CodeLen = 4;
  833.     }
  834.   }
  835. }
  836.  
  837. static void DecodeMTFB_MTTB(Word Code)
  838. {
  839.   LongWord LCode = Code, Src1, Dest;
  840.   Boolean OK;
  841.   const tStrComp *pArg1 = &ArgStr[1], *pArg2 = &ArgStr[2];
  842.   tStrComp TmpComp = { { -1, 0 }, { 0, NULL, 0 } };
  843.  
  844.   if (ChkExactCPUList(ErrNum_InstructionNotSupported, CPU821, CPU505, CPUNone) < 0);
  845.   else if (ArgCnt == 1)
  846.   {
  847.     pArg1 = &ArgStr[1];
  848.     if      ((Memo("MFTB")) || (Memo("MFTBL"))) TmpComp.str.p_str = (char*)"268";
  849.     else if (Memo("MFTBU")) TmpComp.str.p_str = (char*)"269";
  850.     else if ((Memo("MTTB")) || (Memo("MTTBL"))) TmpComp.str.p_str = (char*)"284";
  851.     else if (Memo("MTTBU")) TmpComp.str.p_str = (char*)"285";
  852.     pArg2 = &TmpComp;
  853.     /* already swapped */
  854.   }
  855.   else if ((ArgCnt == 2) && (Code == 467)) /* MTxx */
  856.   {
  857.     pArg1 = &ArgStr[2];
  858.     pArg2 = &ArgStr[1];
  859.   }
  860.   if (ChkArgCnt(1, 2)
  861.    && DecodeGenReg(pArg1, &Dest))
  862.   {
  863.     Src1 = EvalStrIntExpression(pArg2, UInt10, &OK);
  864.     if (OK)
  865.     {
  866.       if ((Src1 == 268) || (Src1 == 269) || (Src1 == 284) || (Src1 == 285))
  867.       {
  868.         SwapCode(&Src1);
  869.         PutCode((T31 << 26) + (Dest << 21) + (Src1 << 11) + (LCode << 1));
  870.         CodeLen = 4;
  871.       }
  872.       else
  873.         WrError(ErrNum_InvCtrlReg);
  874.     }
  875.   }
  876. }
  877.  
  878. static void DecodeMFSPR_MTSPR(Word Code)
  879. {
  880.   LongWord Dest, Src1, LCode = Code;
  881.   const tStrComp *pArg1 = (Code == 467) ? &ArgStr[2] : &ArgStr[1],
  882.                  *pArg2 = (Code == 467) ? &ArgStr[1] : &ArgStr[2];
  883.   Boolean OK;
  884.  
  885.   if (ChkArgCnt(2, 2)
  886.    && DecodeGenReg(pArg1, &Dest))
  887.   {
  888.     Src1 = EvalStrIntExpression(pArg2, UInt10, &OK);
  889.     if (OK)
  890.     {
  891.       SwapCode(&Src1);
  892.       PutCode((T31 << 26) + (Dest << 21) + (Src1 << 11) + (LCode << 1));
  893.       CodeLen = 4;
  894.     }
  895.   }
  896. }
  897.  
  898. static void DecodeMFDCR_MTDCR(Word Code)
  899. {
  900.   LongWord LCode = Code, Src1, Dest;
  901.   const tStrComp *pArg1 = (Code == 451) ? &ArgStr[2] : &ArgStr[1],
  902.                  *pArg2 = (Code == 451) ? &ArgStr[1] : &ArgStr[2];
  903.   Boolean OK;
  904.  
  905.   if (ChkArgCnt(2, 2)
  906.    && (ChkExactCPUList(ErrNum_InstructionNotSupported, CPU403, CPU403C, CPUNone) >= 0)
  907.    && DecodeGenReg(pArg1, &Dest))
  908.   {
  909.     Src1 = EvalStrIntExpression(pArg2, UInt10, &OK);
  910.     if (OK)
  911.     {
  912.       SwapCode(&Src1);
  913.       PutCode((T31 << 26) + (Dest << 21) + (Src1 << 11) + (LCode << 1));
  914.       CodeLen = 4;
  915.     }
  916.   }
  917. }
  918.  
  919. static void DecodeMFSR_MTSR(Word Code)
  920. {
  921.   LongWord LCode = Code, Src1, Dest;
  922.   const tStrComp *pArg1 = (Code == 210) ? &ArgStr[2] : &ArgStr[1],
  923.                  *pArg2 = (Code == 210) ? &ArgStr[1] : &ArgStr[2];
  924.   Boolean OK;
  925.  
  926.   if (ChkArgCnt(2, 2)
  927.    && DecodeGenReg(pArg1, &Dest))
  928.   {
  929.     Src1 = EvalStrIntExpression(pArg2, UInt4, &OK);
  930.     if (OK)
  931.     {
  932.       PutCode((T31 << 26) + (Dest << 21) + (Src1 << 16) + (LCode << 1));
  933.       CodeLen = 4;
  934.       ChkSup();
  935.     }
  936.   }
  937. }
  938.  
  939. static void DecodeMTCRF(Word Code)
  940. {
  941.   LongWord Src1, Dest;
  942.   Boolean OK;
  943.  
  944.   UNUSED(Code);
  945.  
  946.   if (ChkArgCnt(1, 2)
  947.    && DecodeGenReg(&ArgStr[ArgCnt], &Src1))
  948.   {
  949.     OK = True;
  950.     Dest = (ArgCnt == 1) ? 0xff : EvalStrIntExpression(&ArgStr[1], UInt8, &OK);
  951.     if (OK)
  952.     {
  953.       PutCode((T31 << 26) + (Src1 << 21) + (Dest << 12) + (144 << 1));
  954.       CodeLen = 4;
  955.     }
  956.   }
  957. }
  958.  
  959. static void DecodeMTFSF(Word Code)
  960. {
  961.   LongWord Dest, Src1;
  962.   Boolean OK;
  963.  
  964.   UNUSED(Code);
  965.  
  966.   if (ChkArgCnt(2, 2)
  967.    && DecodeFPReg(&ArgStr[2], &Src1))
  968.   {
  969.     Dest = EvalStrIntExpression(&ArgStr[1], UInt8, &OK);
  970.     if (OK)
  971.     {
  972.       PutCode((T63 << 26) + (Dest << 17) + (Src1 << 11) + (711 << 1) + ExtractPoint(Code));
  973.       CodeLen = 4;
  974.     }
  975.   }
  976. }
  977.  
  978. static void DecodeMTFSFI(Word Code)
  979. {
  980.   LongWord Dest, Src1;
  981.   Boolean OK;
  982.  
  983.   if (!ChkArgCnt(2, 2));
  984.   else if (!DecodeCondReg(&ArgStr[1], &Dest));
  985.   else if (Dest & 3) WrStrErrorPos(ErrNum_AddrMustBeAligned, &ArgStr[1]);
  986.   else
  987.   {
  988.     Src1 = EvalStrIntExpression(&ArgStr[2], UInt4, &OK);
  989.     if (OK)
  990.     {
  991.       PutCode((T63 << 26) + (Dest << 21) + (Src1 << 12) + (134 << 1) + ExtractPoint(Code));
  992.       CodeLen = 4;
  993.     }
  994.   }
  995. }
  996.  
  997. static void DecodeRLMI(Word Code)
  998. {
  999.   Integer Imm;
  1000.   LongWord Dest, Src1, Src2, Src3;
  1001.   Boolean OK;
  1002.  
  1003.   if (ChkArgCnt(5, 5)
  1004.    && ChkMinCPU(CPU6000)
  1005.    && DecodeGenReg(&ArgStr[1], &Dest)
  1006.    && DecodeGenReg(&ArgStr[2], &Src1)
  1007.    && DecodeGenReg(&ArgStr[3], &Src2))
  1008.   {
  1009.     Src3 = EvalStrIntExpression(&ArgStr[4], UInt5, &OK);
  1010.     if (OK)
  1011.     {
  1012.       Imm = EvalStrIntExpression(&ArgStr[5], UInt5, &OK);
  1013.       if (OK)
  1014.       {
  1015.         PutCode((T22 << 26) + (Src1 << 21) + (Dest << 16)
  1016.                      + (Src2 << 11) + (Src3 << 6) + (Imm << 1) + ExtractPoint(Code));
  1017.         CodeLen = 4;
  1018.       }
  1019.     }
  1020.   }
  1021. }
  1022.  
  1023. static void DecodeRLWNM(Word Code)
  1024. {
  1025.   Integer Imm;
  1026.   LongWord Dest, Src1, Src2, Src3;
  1027.   Boolean OK;
  1028.  
  1029.   if (ChkArgCnt(5, 5)
  1030.    && DecodeGenReg(&ArgStr[1], &Dest)
  1031.    && DecodeGenReg(&ArgStr[2], &Src1)
  1032.    && DecodeGenReg(&ArgStr[3], &Src2))
  1033.   {
  1034.     Src3 = EvalStrIntExpression(&ArgStr[4], UInt5, &OK);
  1035.     if (OK)
  1036.     {
  1037.       Imm = EvalStrIntExpression(&ArgStr[5], UInt5, &OK);
  1038.       if (OK)
  1039.       {
  1040.         PutCode((T23 << 26) + (Src1 << 21) + (Dest << 16)
  1041.                      + (Src2 << 11) + (Src3 << 6) + (Imm << 1) + ExtractPoint(Code));
  1042.         CodeLen = 4;
  1043.       }
  1044.     }
  1045.   }
  1046. }
  1047.  
  1048. static void DecodeRLWIMI_RLWINM(Word Code)
  1049. {
  1050.   Integer Imm;
  1051.   LongWord Dest, Src1, Src2, Src3, LCode = Code & 0x7fff;
  1052.   Boolean OK;
  1053.  
  1054.   if (ChkArgCnt(5, 5)
  1055.    && DecodeGenReg(&ArgStr[1], &Dest)
  1056.    && DecodeGenReg(&ArgStr[2], &Src1))
  1057.   {
  1058.     Src2 = EvalStrIntExpression(&ArgStr[3], UInt5, &OK);
  1059.     if (OK)
  1060.     {
  1061.       Src3 = EvalStrIntExpression(&ArgStr[4], UInt5, &OK);
  1062.       if (OK)
  1063.       {
  1064.         Imm = EvalStrIntExpression(&ArgStr[5], UInt5, &OK);
  1065.         if (OK)
  1066.         {
  1067.           PutCode((T20 << 26) + (Dest << 16) + (Src1 << 21)
  1068.                 + (Src2 << 11) + (Src3 << 6) + (Imm << 1)
  1069.                 + (LCode << 26) + ExtractPoint(Code));
  1070.           CodeLen = 4;
  1071.         }
  1072.       }
  1073.     }
  1074.   }
  1075. }
  1076.  
  1077. static void DecodeTLBIE(Word Code)
  1078. {
  1079.   LongWord Src1;
  1080.  
  1081.   UNUSED(Code);
  1082.  
  1083.   if (ChkArgCnt(1, 1)
  1084.    && DecodeGenReg(&ArgStr[1], &Src1))
  1085.   {
  1086.     PutCode((T31 << 26) + (Src1 << 11) + (306 << 1));
  1087.     CodeLen = 4;
  1088.     ChkSup();
  1089.   }
  1090. }
  1091.  
  1092. static void DecodeTW(Word Code)
  1093. {
  1094.   LongWord Src1, Src2, Dest;
  1095.   Boolean OK;
  1096.  
  1097.   UNUSED(Code);
  1098.  
  1099.   if (ChkArgCnt(3, 3)
  1100.    && DecodeGenReg(&ArgStr[2], &Src1)
  1101.    && DecodeGenReg(&ArgStr[3], &Src2))
  1102.   {
  1103.     Dest = EvalStrIntExpression(&ArgStr[1], UInt5, &OK);
  1104.     if (OK)
  1105.     {
  1106.       PutCode((T31 << 26) + (Dest << 21) + (Src1 << 16) + (Src2 << 11) + (4 << 1));
  1107.       CodeLen = 4;
  1108.     }
  1109.   }
  1110. }
  1111.  
  1112. static void DecodeTWI(Word Code)
  1113. {
  1114.   Integer Imm;
  1115.   LongWord Dest, Src1;
  1116.   Boolean OK;
  1117.  
  1118.   UNUSED(Code);
  1119.  
  1120.   if (ChkArgCnt(3, 3)
  1121.    && DecodeGenReg(&ArgStr[2], &Src1))
  1122.   {
  1123.     Imm = EvalStrIntExpression(&ArgStr[3], Int16, &OK);
  1124.     if (OK)
  1125.     {
  1126.       Dest = EvalStrIntExpression(&ArgStr[1], UInt5, &OK);
  1127.       if (OK)
  1128.       {
  1129.         PutCode((T3 << 26) + (Dest << 21) + (Src1 << 16) + (Imm & 0xffff));
  1130.         CodeLen = 4;
  1131.       }
  1132.     }
  1133.   }
  1134. }
  1135.  
  1136. static void DecodeWRTEEI(Word Code)
  1137. {
  1138.   LongWord  Src1;
  1139.   Boolean OK;
  1140.  
  1141.   UNUSED(Code);
  1142.  
  1143.   if (ChkArgCnt(1, 1)
  1144.    && (ChkExactCPUList(ErrNum_InstructionNotSupported, CPU403, CPU403C, CPUNone) >= 0))
  1145.   {
  1146.     Src1 = EvalStrIntExpression(&ArgStr[1], UInt1, &OK) << 15;
  1147.     if (OK)
  1148.     {
  1149.       PutCode((T31 << 26) + Src1 + (163 << 1));
  1150.       CodeLen = 4;
  1151.     }
  1152.   }
  1153. }
  1154.  
  1155. static void DecodeCMP_CMPL(Word Code)
  1156. {
  1157.   LongWord Src1, Src2, Src3, Dest, LCode = Code;
  1158.   Boolean OK;
  1159.   const tStrComp *pArg4 = (ArgCnt == 3) ? &ArgStr[3] : &ArgStr[4],
  1160.                  *pArg3 = (ArgCnt == 3) ? &ArgStr[2] : &ArgStr[3],
  1161.                  *pArg2 = (ArgCnt == 3) ? &ZeroComp : &ArgStr[2];
  1162.  
  1163.   if (!ChkArgCnt(3, 4));
  1164.   else if (!DecodeGenReg(pArg4, &Src2));
  1165.   else if (!DecodeGenReg(pArg3, &Src1));
  1166.   else if (!DecodeCondReg(&ArgStr[1], &Dest));
  1167.   else if (Dest & 3) WrStrErrorPos(ErrNum_AddrMustBeAligned, &ArgStr[1]);
  1168.   else
  1169.   {
  1170.     Src3 = EvalStrIntExpression(pArg2, UInt1, &OK);
  1171.     if (OK)
  1172.     {
  1173.       PutCode((T31 << 26) + (Dest << 21) + (Src3 << 21) + (Src1 << 16)
  1174.                    + (Src2 << 11) + (LCode << 1));
  1175.       CodeLen = 4;
  1176.     }
  1177.   }
  1178. }
  1179.  
  1180. /* Vergleiche */
  1181.  
  1182. static void DecodeFCMPO_FCMPU(Word Code)
  1183. {
  1184.   LongWord Src1, Src2, Dest, LCode = Code;
  1185.  
  1186.   if (!ChkArgCnt(3, 3));
  1187.   else if (!DecodeFPReg(&ArgStr[3], &Src2));
  1188.   else if (!DecodeFPReg(&ArgStr[2], &Src1));
  1189.   else if (!DecodeCondReg(&ArgStr[1], &Dest));
  1190.   else if (Dest & 3) WrStrErrorPos(ErrNum_AddrMustBeAligned, &ArgStr[1]);
  1191.   else
  1192.   {
  1193.     PutCode((T63 << 26) + (Dest << 21) + (Src1 << 16) + (Src2 << 11) + (LCode << 1));
  1194.     CodeLen = 4;
  1195.   }
  1196. }
  1197.  
  1198. static void DecodeCMPI_CMPLI(Word Code)
  1199. {
  1200.   LongWord Src1, Src2, Src3, Dest, LCode = Code;
  1201.   Boolean OK;
  1202.   const tStrComp *pArg4 = (ArgCnt == 3) ? &ArgStr[3] : &ArgStr[4],
  1203.                  *pArg3 = (ArgCnt == 3) ? &ArgStr[2] : &ArgStr[3],
  1204.                  *pArg2 = (ArgCnt == 3) ? &ZeroComp : &ArgStr[2];
  1205.  
  1206.   if (ChkArgCnt(3, 4))
  1207.   {
  1208.     Src2 = EvalStrIntExpression(pArg4, Int16, &OK);
  1209.     if (OK)
  1210.     {
  1211.       if (!DecodeGenReg(pArg3, &Src1));
  1212.       else if (!DecodeCondReg(&ArgStr[1], &Dest));
  1213.       else if (Dest & 3) WrStrErrorPos(ErrNum_AddrMustBeAligned, &ArgStr[1]);
  1214.       else
  1215.       {
  1216.         Src3 = EvalStrIntExpression(pArg2, UInt1, &OK);
  1217.         if (OK)
  1218.         {
  1219.           PutCode((T10 << 26) + (Dest << 21) + (Src3 << 21)
  1220.                        + (Src1 << 16) + (Src2 & 0xffff) + (LCode << 26));
  1221.           CodeLen = 4;
  1222.         }
  1223.       }
  1224.     }
  1225.   }
  1226. }
  1227.  
  1228. /* Spruenge */
  1229.  
  1230. static void DecodeB_BL_BA_BLA(Word Code)
  1231. {
  1232.   LongWord LCode = Code;
  1233.   LongInt Dist;
  1234.   Boolean OK;
  1235.   tSymbolFlags Flags;
  1236.  
  1237.   if (ChkArgCnt(1, 1))
  1238.   {
  1239.     Dist = EvalStrIntExpressionWithFlags(&ArgStr[1], Int32, &OK, &Flags);
  1240.     if (OK)
  1241.     {
  1242.       if (!(Code & 2))
  1243.         Dist -= EProgCounter();
  1244.       if (!mSymbolQuestionable(Flags) && (Dist > 0x1ffffff)) WrError(ErrNum_OverRange);
  1245.       else if (!mSymbolQuestionable(Flags) && (Dist < -0x2000000l)) WrError(ErrNum_UnderRange);
  1246.       else if ((Dist & 3) != 0) WrError(ErrNum_DistIsOdd);
  1247.       else
  1248.       {
  1249.         PutCode((T18 << 26) + (Dist & 0x03fffffc) + LCode);
  1250.         CodeLen = 4;
  1251.       }
  1252.     }
  1253.   }
  1254. }
  1255.  
  1256. static void DecodeBC_BCL_BCA_BCLA(Word Code)
  1257. {
  1258.   LongWord LCode = Code, Src1, Src2;
  1259.   LongInt Dist;
  1260.   Boolean OK;
  1261.   tSymbolFlags Flags;
  1262.  
  1263.   if (ChkArgCnt(3, 3))
  1264.   {
  1265.     Src1 = EvalStrIntExpression(&ArgStr[1], UInt5, &OK); /* BO */
  1266.     if (OK)
  1267.     {
  1268.       Src2 = EvalStrIntExpression(&ArgStr[2], UInt5, &OK); /* BI */
  1269.       if (OK)
  1270.       {
  1271.         Dist = EvalStrIntExpressionWithFlags(&ArgStr[3], Int32, &OK, &Flags); /* ADR */
  1272.         if (OK)
  1273.         {
  1274.           if (!(Code & 2))
  1275.             Dist -= EProgCounter();
  1276.           if (!mSymbolQuestionable(Flags) && (Dist > 0x7fff)) WrError(ErrNum_OverRange);
  1277.           else if (!mSymbolQuestionable(Flags) && (Dist < -0x8000l)) WrError(ErrNum_UnderRange);
  1278.           else if ((Dist & 3) != 0) WrError(ErrNum_DistIsOdd);
  1279.           else
  1280.           {
  1281.             PutCode((T16 << 26) + (Src1 << 21) + (Src2 << 16) + (Dist & 0xfffc) + LCode);
  1282.             CodeLen = 4;
  1283.           }
  1284.         }
  1285.       }
  1286.     }
  1287.   }
  1288. }
  1289.  
  1290. static void DecodeBCCTR_BCCTRL_BCLR_BCLRL(Word Code)
  1291. {
  1292.   LongWord Src1, Src2, LCode = Code;
  1293.   Boolean OK;
  1294.  
  1295.   if (ChkArgCnt(2, 2))
  1296.   {
  1297.     Src1 = EvalStrIntExpression(&ArgStr[1], UInt5, &OK);
  1298.     if (OK)
  1299.     {
  1300.       Src2 = EvalStrIntExpression(&ArgStr[2], UInt5, &OK);
  1301.       if (OK)
  1302.       {
  1303.         PutCode((T19 << 26) + (Src1 << 21) + (Src2 << 16) + LCode);
  1304.         CodeLen = 4;
  1305.       }
  1306.     }
  1307.   }
  1308. }
  1309.  
  1310. static void DecodeTLBRE_TLBWE(Word Code)
  1311. {
  1312.   LongWord Src1, Src2, Src3, LCode = Code;
  1313.   Boolean OK;
  1314.  
  1315.   if (ChkArgCnt(3, 3)
  1316.    && ChkExactCPU(CPU403C)
  1317.    && DecodeGenReg(&ArgStr[1], &Src1)
  1318.    && DecodeGenReg(&ArgStr[2], &Src2))
  1319.   {
  1320.     Src3 = EvalStrIntExpression(&ArgStr[3], UInt1, &OK);
  1321.     if (OK)
  1322.     {
  1323.       PutCode((T31 << 26) + (Src1 << 21) + (Src2 << 16) +
  1324.               (Src3 << 11) + (946 << 1) + (LCode << 1));
  1325.       CodeLen = 4;
  1326.     }
  1327.   }
  1328. }
  1329.  
  1330. /*-------------------------------------------------------------------------*/
  1331.  
  1332. static void AddFixed(const char *NName1, const char *NName2, LongWord NCode, Byte NMask)
  1333. {
  1334.   order_array_rsv_end(FixedOrders, BaseOrder);
  1335.   FixedOrders[InstrZ].Code = NCode;
  1336.   FixedOrders[InstrZ].CPUMask = NMask;
  1337.   AddInstTable(InstTable, MomCPU == CPU6000 ? NName2 : NName1, InstrZ++, DecodeFixed);
  1338. }
  1339.  
  1340. static void AddReg1(const char *NName1, const char *NName2, LongWord NCode, Byte NMask)
  1341. {
  1342.   order_array_rsv_end(Reg1Orders, BaseOrder);
  1343.   Reg1Orders[InstrZ].Code = NCode;
  1344.   Reg1Orders[InstrZ].CPUMask = NMask;
  1345.   AddInstTable(InstTable, MomCPU == CPU6000 ? NName2 : NName1, InstrZ++, DecodeReg1);
  1346. }
  1347.  
  1348. static void AddCReg1(const char *NName1, const char *NName2, LongWord NCode, Byte NMask)
  1349. {
  1350.   order_array_rsv_end(CReg1Orders, BaseOrder);
  1351.   CReg1Orders[InstrZ].Code = NCode;
  1352.   CReg1Orders[InstrZ].CPUMask = NMask;
  1353.   AddInstTable(InstTable, MomCPU == CPU6000 ? NName2 : NName1, InstrZ++, DecodeCReg1);
  1354. }
  1355.  
  1356. static void AddCBit1(const char *NName1, const char *NName2, LongWord NCode, Byte NMask)
  1357. {
  1358.   order_array_rsv_end(CBit1Orders, BaseOrder);
  1359.   CBit1Orders[InstrZ].Code = NCode;
  1360.   CBit1Orders[InstrZ].CPUMask = NMask;
  1361.   AddInstTable(InstTable, MomCPU == CPU6000 ? NName2 : NName1, InstrZ++, DecodeCBit1);
  1362. }
  1363.  
  1364. static void AddFReg1(const char *NName1, const char *NName2, LongWord NCode, Byte NMask)
  1365. {
  1366.   order_array_rsv_end(FReg1Orders, BaseOrder);
  1367.   FReg1Orders[InstrZ].Code = NCode;
  1368.   FReg1Orders[InstrZ].CPUMask = NMask;
  1369.   AddInstTable(InstTable, MomCPU == CPU6000 ? NName2 : NName1, InstrZ++, DecodeFReg1);
  1370. }
  1371.  
  1372. static void AddSReg2(const char *NName, LongWord NCode, Byte NMask)
  1373. {
  1374.   order_array_rsv_end(Reg2Orders, BaseOrder);
  1375.   Reg2Orders[InstrZ].Code = NCode;
  1376.   Reg2Orders[InstrZ].CPUMask = NMask;
  1377.   AddInstTable(InstTable, NName, InstrZ++, DecodeReg2);
  1378. }
  1379.  
  1380. static void AddReg2(const char *NName1, const char *NName2, LongWord NCode, Byte NMask, Boolean WithOE, Boolean WithFL)
  1381. {
  1382.   String NName;
  1383.   const char *pSrcName = (MomCPU == CPU6000) ? NName2 : NName1;
  1384.  
  1385.   AddSReg2(pSrcName, NCode, NMask);
  1386.   if (WithOE)
  1387.   {
  1388.     as_snprintf(NName, sizeof(NName), "%sO", pSrcName);
  1389.     AddSReg2(NName, NCode | 0x400, NMask);
  1390.   }
  1391.   if (WithFL)
  1392.   {
  1393.     as_snprintf(NName, sizeof(NName), "%s.", pSrcName);
  1394.     AddSReg2(NName, NCode | 0x001, NMask);
  1395.     if (WithOE)
  1396.     {
  1397.       as_snprintf(NName, sizeof(NName), "%sO.", pSrcName);
  1398.       AddSReg2(NName, NCode | 0x401, NMask);
  1399.     }
  1400.   }
  1401. }
  1402.  
  1403. static void AddCReg2(const char *NName1, const char *NName2, LongWord NCode, Byte NMask)
  1404. {
  1405.   order_array_rsv_end(CReg2Orders, BaseOrder);
  1406.   CReg2Orders[InstrZ].Code = NCode;
  1407.   CReg2Orders[InstrZ].CPUMask = NMask;
  1408.   AddInstTable(InstTable, (MomCPU == CPU6000) ? NName2 : NName1, InstrZ++, DecodeCReg2);
  1409. }
  1410.  
  1411. static void AddSFReg2(const char *NName, LongWord NCode, Byte NMask)
  1412. {
  1413.   order_array_rsv_end(FReg2Orders, BaseOrder);
  1414.   if (!NName) exit(255);
  1415.   FReg2Orders[InstrZ].Code = NCode;
  1416.   FReg2Orders[InstrZ].CPUMask = NMask;
  1417.   AddInstTable(InstTable, NName, InstrZ++, DecodeFReg2);
  1418. }
  1419.  
  1420. static void AddFReg2(const char *NName1, const char *NName2, LongWord NCode, Byte NMask, Boolean WithFL)
  1421. {
  1422.   const char *pSrcName = (MomCPU == CPU6000) ? NName2 : NName1;
  1423.  
  1424.   AddSFReg2(pSrcName, NCode, NMask);
  1425.   if (WithFL)
  1426.   {
  1427.     String NName;
  1428.  
  1429.     as_snprintf(NName, sizeof(NName), "%s.", pSrcName);
  1430.     AddSFReg2(NName, NCode | 0x001, NMask);
  1431.   }
  1432. }
  1433.  
  1434. static void AddReg2B(const char *NName1, const char *NName2, LongWord NCode, Byte NMask)
  1435. {
  1436.   order_array_rsv_end(Reg2BOrders, BaseOrder);
  1437.   Reg2BOrders[InstrZ].Code = NCode;
  1438.   Reg2BOrders[InstrZ].CPUMask = NMask;
  1439.   AddInstTable(InstTable, (MomCPU == CPU6000) ? NName2 : NName1, InstrZ++, DecodeReg2B);
  1440. }
  1441.  
  1442. static void AddSReg2Swap(const char *NName, LongWord NCode, Byte NMask)
  1443. {
  1444.   order_array_rsv_end(Reg2SwapOrders, BaseOrder);
  1445.   if (!NName) exit(255);
  1446.   Reg2SwapOrders[InstrZ].Code = NCode;
  1447.   Reg2SwapOrders[InstrZ].CPUMask = NMask;
  1448.   AddInstTable(InstTable, NName, InstrZ++, DecodeReg2Swap);
  1449. }
  1450.  
  1451. static void AddReg2Swap(const char *NName1, const char *NName2, LongWord NCode, Byte NMask, Boolean WithOE, Boolean WithFL)
  1452. {
  1453.   String NName;
  1454.   const char *pSrcName = (MomCPU == CPU6000) ? NName2 : NName1;
  1455.  
  1456.   AddSReg2Swap(pSrcName, NCode, NMask);
  1457.   if (WithOE)
  1458.   {
  1459.     as_snprintf(NName, sizeof(NName), "%sO", pSrcName);
  1460.     AddSReg2Swap(NName, NCode | 0x400, NMask);
  1461.   }
  1462.   if (WithFL)
  1463.   {
  1464.     as_snprintf(NName, sizeof(NName), "%s.", pSrcName);
  1465.     AddSReg2Swap(NName, NCode | 0x001, NMask);
  1466.     if (WithOE)
  1467.     {
  1468.       as_snprintf(NName, sizeof(NName), "%sO.", pSrcName);
  1469.       AddSReg2Swap(NName, NCode | 0x401, NMask);
  1470.     }
  1471.   }
  1472. }
  1473.  
  1474. static void AddNoDest(const char *NName1, const char *NName2, LongWord NCode, Byte NMask)
  1475. {
  1476.   order_array_rsv_end(NoDestOrders, BaseOrder);
  1477.   NoDestOrders[InstrZ].Code = NCode;
  1478.   NoDestOrders[InstrZ].CPUMask = NMask;
  1479.   AddInstTable(InstTable, (MomCPU == CPU6000) ? NName2 : NName1, InstrZ++, DecodeNoDest);
  1480. }
  1481.  
  1482. static void AddSReg3(const char *NName, LongWord NCode, Byte NMask)
  1483. {
  1484.   order_array_rsv_end(Reg3Orders, BaseOrder);
  1485.   Reg3Orders[InstrZ].Code = NCode;
  1486.   Reg3Orders[InstrZ].CPUMask = NMask;
  1487.   AddInstTable(InstTable, NName, InstrZ++, DecodeReg3);
  1488. }
  1489.  
  1490. static void AddReg3(const char *NName1, const char *NName2, LongWord NCode, Byte NMask, Boolean WithOE, Boolean WithFL)
  1491. {
  1492.   String NName;
  1493.   const char *pSrcName = (MomCPU == CPU6000) ? NName2 : NName1;
  1494.  
  1495.   AddSReg3(pSrcName, NCode, NMask);
  1496.   if (WithOE)
  1497.   {
  1498.     as_snprintf(NName, sizeof(NName), "%sO", pSrcName);
  1499.     AddSReg3(NName, NCode | 0x400, NMask);
  1500.     NName[strlen(NName) - 1] = '\0';
  1501.   }
  1502.   if (WithFL)
  1503.   {
  1504.     as_snprintf(NName, sizeof(NName), "%s.", pSrcName);
  1505.     AddSReg3(NName, NCode | 0x001, NMask);
  1506.     NName[strlen(NName) - 1] = '\0';
  1507.     if (WithOE)
  1508.     {
  1509.       as_snprintf(NName, sizeof(NName), "%sO.", pSrcName);
  1510.       AddSReg3(NName, NCode | 0x401, NMask);
  1511.     }
  1512.   }
  1513. }
  1514.  
  1515. static void AddCReg3(const char *NName, LongWord NCode, CPUVar NMask)
  1516. {
  1517.   order_array_rsv_end(CReg3Orders, BaseOrder);
  1518.   CReg3Orders[InstrZ].Code = NCode;
  1519.   CReg3Orders[InstrZ].CPUMask = NMask;
  1520.   AddInstTable(InstTable, NName, InstrZ++, DecodeCReg3);
  1521. }
  1522.  
  1523. static void AddSFReg3(const char *NName, LongWord NCode, Byte NMask)
  1524. {
  1525.   order_array_rsv_end(FReg3Orders, BaseOrder);
  1526.   FReg3Orders[InstrZ].Code = NCode;
  1527.   FReg3Orders[InstrZ].CPUMask = NMask;
  1528.   AddInstTable(InstTable, NName, InstrZ++, DecodeFReg3);
  1529. }
  1530.  
  1531. static void AddFReg3(const char *NName1, const char *NName2, LongWord NCode, Byte NMask, Boolean WithFL)
  1532. {
  1533.   String NName;
  1534.   const char *pSrcName = (MomCPU == CPU6000) ? NName2 : NName1;
  1535.  
  1536.   AddSFReg3(pSrcName, NCode, NMask);
  1537.   if (WithFL)
  1538.   {
  1539.     as_snprintf(NName, sizeof(NName), "%s.", pSrcName);
  1540.     AddSFReg3(NName, NCode | 0x001, NMask);
  1541.   }
  1542. }
  1543.  
  1544. static void AddSReg3Swap(const char *NName, LongWord NCode, Byte NMask)
  1545. {
  1546.   order_array_rsv_end(Reg3SwapOrders, BaseOrder);
  1547.   Reg3SwapOrders[InstrZ].Code = NCode;
  1548.   Reg3SwapOrders[InstrZ].CPUMask = NMask;
  1549.   AddInstTable(InstTable, NName, InstrZ++, DecodeReg3Swap);
  1550. }
  1551.  
  1552. static void AddReg3Swap(const char *NName1, const char *NName2, LongWord NCode, Byte NMask, Boolean WithFL)
  1553. {
  1554.   String NName;
  1555.   const char *pSrcName = (MomCPU == CPU6000) ? NName2 : NName1;
  1556.  
  1557.   AddSReg3Swap(pSrcName, NCode, NMask);
  1558.   if (WithFL)
  1559.   {
  1560.     as_snprintf(NName, sizeof(NName), "%s.", pSrcName);
  1561.     AddSReg3Swap(NName, NCode | 0x001, NMask);
  1562.   }
  1563. }
  1564.  
  1565. static void AddMixed(const char *NName1, const char *NName2, LongWord NCode, Byte NMask)
  1566. {
  1567.   order_array_rsv_end(MixedOrders, BaseOrder);
  1568.   MixedOrders[InstrZ].Code = NCode;
  1569.   MixedOrders[InstrZ].CPUMask = NMask;
  1570.   AddInstTable(InstTable, (MomCPU == CPU6000) ? NName2 : NName1, InstrZ++, DecodeMixed);
  1571. }
  1572.  
  1573. static void AddSFReg4(const char *NName, LongWord NCode, Byte NMask)
  1574. {
  1575.   order_array_rsv_end(FReg4Orders, BaseOrder);
  1576.   FReg4Orders[InstrZ].Code = NCode;
  1577.   FReg4Orders[InstrZ].CPUMask = NMask;
  1578.   AddInstTable(InstTable, NName, InstrZ++, DecodeFReg4);
  1579. }
  1580.  
  1581. static void AddFReg4(const char *NName1, const char *NName2, LongWord NCode, Byte NMask, Boolean WithFL)
  1582. {
  1583.   String NName;
  1584.   const char *pSrcName = (MomCPU == CPU6000) ? NName2 : NName1;
  1585.  
  1586.   AddSFReg4(pSrcName, NCode, NMask);
  1587.   if (WithFL)
  1588.   {
  1589.     as_snprintf(NName, sizeof(NName), "%s.", pSrcName);
  1590.     AddSFReg4(NName, NCode | 0x001, NMask);
  1591.   }
  1592. }
  1593.  
  1594. static void AddRegDisp(const char *NName1, const char *NName2, LongWord NCode, Byte NMask)
  1595. {
  1596.   order_array_rsv_end(RegDispOrders, BaseOrder);
  1597.   RegDispOrders[InstrZ].Code = NCode;
  1598.   RegDispOrders[InstrZ].CPUMask = NMask;
  1599.   AddInstTable(InstTable, (MomCPU == CPU6000) ? NName2 : NName1, InstrZ++, DecodeRegDispOrder);
  1600. }
  1601.  
  1602. static void AddFRegDisp(const char *NName1, const char *NName2, LongWord NCode, Byte NMask)
  1603. {
  1604.   order_array_rsv_end(FRegDispOrders, BaseOrder);
  1605.   FRegDispOrders[InstrZ].Name = (MomCPU == CPU6000) ? NName2 : NName1;
  1606.   FRegDispOrders[InstrZ].Code = NCode;
  1607.   FRegDispOrders[InstrZ].CPUMask = NMask;
  1608.   AddInstTable(InstTable, (MomCPU == CPU6000) ? NName2 : NName1, InstrZ++, DecodeFRegDisp);
  1609. }
  1610.  
  1611. static void AddSReg2Imm(const char *NName, LongWord NCode, Byte NMask)
  1612. {
  1613.   order_array_rsv_end(Reg2ImmOrders, BaseOrder);
  1614.   if (!NName) exit(255);
  1615.   Reg2ImmOrders[InstrZ].Code = NCode;
  1616.   Reg2ImmOrders[InstrZ].CPUMask = NMask;
  1617.   AddInstTable(InstTable, NName, InstrZ++, DecodeReg2Imm);
  1618. }
  1619.  
  1620. static void AddReg2Imm(const char *NName1, const char *NName2, LongWord NCode, Byte NMask, Boolean WithFL)
  1621. {
  1622.   String NName;
  1623.   const char *pSrcName = (MomCPU == CPU6000) ? NName2 : NName1;
  1624.  
  1625.   AddSReg2Imm(pSrcName, NCode, NMask);
  1626.   if (WithFL)
  1627.   {
  1628.     as_snprintf(NName, sizeof(NName), "%s.", pSrcName);
  1629.     AddSReg2Imm(NName, NCode | 0x001, NMask);
  1630.   }
  1631. }
  1632.  
  1633. static void AddImm16(const char *NName1, const char *NName2, LongWord NCode, Byte NMask)
  1634. {
  1635.   order_array_rsv_end(Imm16Orders, BaseOrder);
  1636.   Imm16Orders[InstrZ].Code = NCode;
  1637.   Imm16Orders[InstrZ].CPUMask = NMask;
  1638.   AddInstTable(InstTable, (MomCPU == CPU6000) ? NName2 : NName1, InstrZ++, DecodeImm16);
  1639. }
  1640.  
  1641. static void AddImm16Swap(const char *NName1, const char *NName2, LongWord NCode, Byte NMask)
  1642. {
  1643.   order_array_rsv_end(Imm16SwapOrders, BaseOrder);
  1644.   Imm16SwapOrders[InstrZ].Code = NCode;
  1645.   Imm16SwapOrders[InstrZ].CPUMask = NMask;
  1646.   AddInstTable(InstTable, (MomCPU == CPU6000) ? NName2 : NName1, InstrZ++, DecodeImm16Swap);
  1647. }
  1648.  
  1649. static void AddPoint(const char *pName, Word Code, InstProc Proc)
  1650. {
  1651.   char PointName[30];
  1652.  
  1653.   AddInstTable(InstTable, pName, Code, Proc);
  1654.   as_snprintf(PointName, sizeof(PointName), "%s.", pName);
  1655.   AddInstTable(InstTable, PointName, Code | 0x8000, Proc);
  1656. }
  1657.  
  1658. static void InitFields(void)
  1659. {
  1660.   InstTable = CreateInstTable(407);
  1661.   SetDynamicInstTable(InstTable);
  1662.  
  1663.   AddPoint("FMULS", 59, DecodeFMUL_FMULS);
  1664.   AddPoint((MomCPU == CPU6000) ? "FM" : "FMUL", 63, DecodeFMUL_FMULS);
  1665.   AddInstTable(InstTable, (MomCPU == CPU6000) ? "LSI" : "LSWI", 597, DecodeLSWI_STSWI);
  1666.   AddInstTable(InstTable, (MomCPU == CPU6000) ? "STSI" : "STSWI", 597 + 128, DecodeLSWI_STSWI);
  1667.   AddInstTable(InstTable, "MFTB", 371, DecodeMTFB_MTTB);
  1668.   AddInstTable(InstTable, "MFTBU", 371, DecodeMTFB_MTTB);
  1669.   AddInstTable(InstTable, "MFTBL", 371, DecodeMTFB_MTTB);
  1670.   AddInstTable(InstTable, "MTTB", 467, DecodeMTFB_MTTB);
  1671.   AddInstTable(InstTable, "MTTBU", 467, DecodeMTFB_MTTB);
  1672.   AddInstTable(InstTable, "MTTBL", 467, DecodeMTFB_MTTB);
  1673.   AddInstTable(InstTable, "MFSPR", 339, DecodeMFSPR_MTSPR);
  1674.   AddInstTable(InstTable, "MTSPR", 467, DecodeMFSPR_MTSPR);
  1675.   AddInstTable(InstTable, "MFDCR", 323, DecodeMFDCR_MTDCR);
  1676.   AddInstTable(InstTable, "MTDCR", 451, DecodeMFDCR_MTDCR);
  1677.   AddInstTable(InstTable, "MFSR", 595, DecodeMFSR_MTSR);
  1678.   AddInstTable(InstTable, "MTSR", 210, DecodeMFSR_MTSR);
  1679.   AddInstTable(InstTable, "MTCRF", 0, DecodeMTCRF);
  1680.   AddPoint("MTFSF", 0, DecodeMTFSF);
  1681.   AddPoint("MTFSFI", 0, DecodeMTFSFI);
  1682.   AddPoint("RLMI", 0, DecodeRLMI);
  1683.   AddPoint((MomCPU == CPU6000) ? "RLNM" : "RLWNM", 0, DecodeRLWNM);
  1684.   AddPoint((MomCPU == CPU6000) ? "RLIMI" : "RLWIMI", 0, DecodeRLWIMI_RLWINM);
  1685.   AddPoint((MomCPU == CPU6000) ? "RLINM" : "RLWINM", 1, DecodeRLWIMI_RLWINM);
  1686.   AddInstTable(InstTable, (MomCPU == CPU6000) ? "TLBI" :  "TLBIE", 0, DecodeTLBIE);
  1687.   AddInstTable(InstTable, (MomCPU == CPU6000) ? "T" : "TW", 0, DecodeTW);
  1688.   AddInstTable(InstTable, (MomCPU == CPU6000) ? "TI" : "TWI", 0, DecodeTWI);
  1689.   AddInstTable(InstTable, "WRTEEI", 0, DecodeWRTEEI);
  1690.   AddInstTable(InstTable, "CMP", 0, DecodeCMP_CMPL);
  1691.   AddInstTable(InstTable, "CMPL", 32, DecodeCMP_CMPL);
  1692.   AddInstTable(InstTable, "FCMPO", 32, DecodeFCMPO_FCMPU);
  1693.   AddInstTable(InstTable, "FCMPU", 0, DecodeFCMPO_FCMPU);
  1694.   AddInstTable(InstTable, "CMPI", 1, DecodeCMPI_CMPLI);
  1695.   AddInstTable(InstTable, "CMPLI", 0, DecodeCMPI_CMPLI);
  1696.   AddInstTable(InstTable, "B", 0, DecodeB_BL_BA_BLA);
  1697.   AddInstTable(InstTable, "BL", 1, DecodeB_BL_BA_BLA);
  1698.   AddInstTable(InstTable, "BA", 2, DecodeB_BL_BA_BLA);
  1699.   AddInstTable(InstTable, "BLA", 3, DecodeB_BL_BA_BLA);
  1700.   AddInstTable(InstTable, "BC", 0, DecodeBC_BCL_BCA_BCLA);
  1701.   AddInstTable(InstTable, "BCL", 1, DecodeBC_BCL_BCA_BCLA);
  1702.   AddInstTable(InstTable, "BCA", 2, DecodeBC_BCL_BCA_BCLA);
  1703.   AddInstTable(InstTable, "BCLA", 3, DecodeBC_BCL_BCA_BCLA);
  1704.   AddInstTable(InstTable, (MomCPU == CPU6000) ? "BCC" : "BCCTR", 528 << 1, DecodeBCCTR_BCCTRL_BCLR_BCLRL);
  1705.   AddInstTable(InstTable, (MomCPU == CPU6000) ? "BCCL" : "BCCTRL", (528 << 1) | 1, DecodeBCCTR_BCCTRL_BCLR_BCLRL);
  1706.   AddInstTable(InstTable, (MomCPU == CPU6000) ? "BCR" : "BCLR", 16 << 1, DecodeBCCTR_BCCTRL_BCLR_BCLRL);
  1707.   AddInstTable(InstTable, (MomCPU == CPU6000) ? "BCRL" : "BCLRL", (16 << 1) | 1, DecodeBCCTR_BCCTRL_BCLR_BCLRL);
  1708.   AddInstTable(InstTable, "TLBRE", 0, DecodeTLBRE_TLBWE);
  1709.   AddInstTable(InstTable, "TLBWE", 32, DecodeTLBRE_TLBWE);
  1710.   AddInstTable(InstTable, "REG", 0, CodeREG);
  1711.  
  1712.   /* --> 0 0 0 */
  1713.  
  1714.   InstrZ = 0;
  1715.   AddFixed("EIEIO"  , "EIEIO"  , (T31 << 26) + (854 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1716.   AddFixed("ISYNC"  , "ICS"    , (T19 << 26) + (150 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1717.   AddFixed("RFI"    , "RFI"    , (T19 << 26) + ( 50 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000 | M_SUP);
  1718.   AddFixed("SC"     , "SVCA"   , (T17 << 26) + (  1 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1719.   AddFixed("SYNC"   , "DCS"    , (T31 << 26) + (598 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1720.   AddFixed("RFCI"   , "RFCI"   , (T19 << 26) + ( 51 << 1), M_403 | M_403C                         );
  1721.   AddFixed("TLBIA"  , "TLBIA"  , (T31 << 26) + (370 << 1),         M_403C | M_821                 );
  1722.   AddFixed("TLBSYNC", "TLBSYNC", (T31 << 26) + (566 << 1),         M_403C | M_821                 );
  1723.  
  1724.   /* D --> D 0 0 */
  1725.  
  1726.   InstrZ = 0;
  1727.   AddReg1("MFCR"   , "MFCR"    , (T31 << 26) + ( 19 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1728.   AddReg1("MFMSR"  , "MFMSR"   , (T31 << 26) + ( 83 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1729.   AddReg1("MTMSR"  , "MTMSR"   , (T31 << 26) + (146 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000 | M_SUP);
  1730.   AddReg1("WRTEE"  , "WRTEE"   , (T31 << 26) + (131 << 1), M_403 | M_403C | M_505 |         M_601 | M_6000);
  1731.  
  1732.   /* crD --> D 0 0 */
  1733.  
  1734.   InstrZ = 0;
  1735.   AddCReg1("MCRXR"  , "MCRXR"  , (T31 << 26) + (512 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1736.  
  1737.   /* crbD --> D 0 0 */
  1738.  
  1739.   InstrZ = 0;
  1740.   AddCBit1("MTFSB0" , "MTFSB0" , (T63 << 26) + ( 70 << 1)    , M_601 | M_6000);
  1741.   AddCBit1("MTFSB0.", "MTFSB0.", (T63 << 26) + ( 70 << 1) + 1, M_601 | M_6000);
  1742.   AddCBit1("MTFSB1" , "MTFSB1" , (T63 << 26) + ( 38 << 1)    , M_601 | M_6000);
  1743.   AddCBit1("MTFSB1.", "MTFSB1.", (T63 << 26) + ( 38 << 1) + 1, M_601 | M_6000);
  1744.  
  1745.   /* frD --> D 0 0 */
  1746.  
  1747.   InstrZ = 0;
  1748.   AddFReg1("MFFS"   , "MFFS"  , (T63 << 26) + (583 << 1)    , M_601 | M_6000);
  1749.   AddFReg1("MFFS."  , "MFFS." , (T63 << 26) + (583 << 1) + 1, M_601 | M_6000);
  1750.  
  1751.   /* D,A --> D A 0 */
  1752.  
  1753.   InstrZ = 0;
  1754.   AddReg2("ABS"   , "ABS"  , (T31 << 26) + (360 << 1),                                          M_6000, True , True );
  1755.   AddReg2("ADDME" , "AME"  , (T31 << 26) + (234 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1756.   AddReg2("ADDZE" , "AZE"  , (T31 << 26) + (202 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1757.   AddReg2("CLCS"  , "CLCS" , (T31 << 26) + (531 << 1),                                          M_6000, False, False);
  1758.   AddReg2("NABS"  , "NABS" , (T31 << 26) + (488 << 1),                                          M_6000, True , True );
  1759.   AddReg2("NEG"   , "NEG"  , (T31 << 26) + (104 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1760.   AddReg2("SUBFME", "SFME" , (T31 << 26) + (232 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1761.   AddReg2("SUBFZE", "SFZE" , (T31 << 26) + (200 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1762.  
  1763.   /* cD,cS --> D S 0 */
  1764.  
  1765.   InstrZ = 0;
  1766.   AddCReg2("MCRF"  , "MCRF"  , (T19 << 26) + (  0 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1767.   AddCReg2("MCRFS" , "MCRFS" , (T63 << 26) + ( 64 << 1),                          M_601 | M_6000);
  1768.  
  1769.   /* fD,fB --> D 0 B */
  1770.  
  1771.   InstrZ = 0;
  1772.   AddFReg2("FABS"  , "FABS"  , (T63 << 26) + (264 << 1), M_601 | M_6000, True );
  1773.   AddFReg2("FCTIW" , "FCTIW" , (T63 << 26) + ( 14 << 1), M_601 | M_6000, True );
  1774.   AddFReg2("FCTIWZ", "FCTIWZ", (T63 << 26) + ( 15 << 1), M_601 | M_6000, True );
  1775.   AddFReg2("FMR"   , "FMR"   , (T63 << 26) + ( 72 << 1), M_601 | M_6000, True );
  1776.   AddFReg2("FNABS" , "FNABS" , (T63 << 26) + (136 << 1), M_601 | M_6000, True );
  1777.   AddFReg2("FNEG"  , "FNEG"  , (T63 << 26) + ( 40 << 1), M_601 | M_6000, True );
  1778.   AddFReg2("FRSP"  , "FRSP"  , (T63 << 26) + ( 12 << 1), M_601 | M_6000, True );
  1779.  
  1780.   /* D,B --> D 0 B */
  1781.  
  1782.   InstrZ = 0;
  1783.   AddReg2B("MFSRIN", "MFSRIN", (T31 << 26) + (659 << 1), M_601 | M_6000);
  1784.   AddReg2B("MTSRIN", "MTSRI" , (T31 << 26) + (242 << 1), M_601 | M_6000);
  1785.  
  1786.   /* A,S --> S A 0 */
  1787.  
  1788.   InstrZ = 0;
  1789.   AddReg2Swap("CNTLZW", "CNTLZ" , (T31 << 26) + ( 26 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, True );
  1790.   AddReg2Swap("EXTSB ", "EXTSB" , (T31 << 26) + (954 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, True );
  1791.   AddReg2Swap("EXTSH ", "EXTS"  , (T31 << 26) + (922 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, True );
  1792.  
  1793.   /* A,B --> 0 A B */
  1794.  
  1795.   InstrZ = 0;
  1796.   AddNoDest("DCBF"  , "DCBF"  , (T31 << 26) + (  86 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1797.   AddNoDest("DCBI"  , "DCBI"  , (T31 << 26) + ( 470 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1798.   AddNoDest("DCBST" , "DCBST" , (T31 << 26) + (  54 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1799.   AddNoDest("DCBT"  , "DCBT"  , (T31 << 26) + ( 278 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1800.   AddNoDest("DCBTST", "DCBTST", (T31 << 26) + ( 246 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1801.   AddNoDest("DCBZ"  , "DCLZ"  , (T31 << 26) + (1014 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1802.   AddNoDest("DCCCI" , "DCCCI" , (T31 << 26) + ( 454 << 1), M_403 | M_403C                         );
  1803.   AddNoDest("ICBI"  , "ICBI"  , (T31 << 26) + ( 982 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1804.   AddNoDest("ICBT"  , "ICBT"  , (T31 << 26) + ( 262 << 1), M_403 | M_403C                         );
  1805.   AddNoDest("ICCCI" , "ICCCI" , (T31 << 26) + ( 966 << 1), M_403 | M_403C                         );
  1806.  
  1807.   /* D,A,B --> D A B */
  1808.  
  1809.   InstrZ = 0;
  1810.   AddReg3("ADD"   , "CAX"   , (T31 << 26) + (266 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True,  True );
  1811.   AddReg3("ADDC"  , "A"     , (T31 << 26) + ( 10 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1812.   AddReg3("ADDE"  , "AE"    , (T31 << 26) + (138 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1813.   AddReg3("DIV"   , "DIV"   , (T31 << 26) + (331 << 1),                                          M_6000, True , True );
  1814.   AddReg3("DIVS"  , "DIVS"  , (T31 << 26) + (363 << 1),                                          M_6000, True , True );
  1815.   AddReg3("DIVW"  , "DIVW"  , (T31 << 26) + (491 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1816.   AddReg3("DIVWU" , "DIVWU" , (T31 << 26) + (459 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1817.   AddReg3("DOZ"   , "DOZ"   , (T31 << 26) + (264 << 1),                                          M_6000, True , True );
  1818.   AddReg3("ECIWX" , "ECIWX" , (T31 << 26) + (310 << 1),                          M_821 |         M_6000, False, False);
  1819.   AddReg3("LBZUX" , "LBZUX" , (T31 << 26) + (119 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1820.   AddReg3("LBZX"  , "LBZX"  , (T31 << 26) + ( 87 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1821.   AddReg3("LHAUX" , "LHAUX" , (T31 << 26) + (375 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1822.   AddReg3("LHAX"  , "LHAX"  , (T31 << 26) + (343 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1823.   AddReg3("LHBRX" , "LHBRX" , (T31 << 26) + (790 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1824.   AddReg3("LHZUX" , "LHZUX" , (T31 << 26) + (311 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1825.   AddReg3("LHZX"  , "LHZX"  , (T31 << 26) + (279 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1826.   AddReg3("LSCBX" , "LSCBX" , (T31 << 26) + (277 << 1),                                          M_6000, False, True );
  1827.   AddReg3("LSWX"  , "LSX"   , (T31 << 26) + (533 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1828.   AddReg3("LWARX" , "LWARX" , (T31 << 26) + ( 20 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1829.   AddReg3("LWBRX" , "LBRX"  , (T31 << 26) + (534 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1830.   AddReg3("LWZUX" , "LUX"   , (T31 << 26) + ( 55 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1831.   AddReg3("LWZX"  , "LX"    , (T31 << 26) + ( 23 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1832.   AddReg3("MUL"   , "MUL"   , (T31 << 26) + (107 << 1),                                          M_6000, True , True );
  1833.   AddReg3("MULHW" , "MULHW" , (T31 << 26) + ( 75 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, True );
  1834.   AddReg3("MULHWU", "MULHWU", (T31 << 26) + ( 11 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, True );
  1835.   AddReg3("MULLW" , "MULS"  , (T31 << 26) + (235 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1836.   AddReg3("STBUX" , "STBUX" , (T31 << 26) + (247 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1837.   AddReg3("STBX"  , "STBX"  , (T31 << 26) + (215 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1838.   AddReg3("STHBRX", "STHBRX", (T31 << 26) + (918 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1839.   AddReg3("STHUX" , "STHUX" , (T31 << 26) + (439 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1840.   AddReg3("STHX"  , "STHX"  , (T31 << 26) + (407 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1841.   AddReg3("STSWX" , "STSX"  , (T31 << 26) + (661 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1842.   AddReg3("STWBRX", "STBRX" , (T31 << 26) + (662 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1843.   AddReg3("STWCX.", "STWCX.", (T31 << 26) + (150 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1844.   AddReg3("STWUX" , "STUX"  , (T31 << 26) + (183 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1845.   AddReg3("STWX"  , "STX"   , (T31 << 26) + (151 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, False, False);
  1846.   AddReg3("SUBF"  , "SUBF"  , (T31 << 26) + ( 40 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1847.   AddReg3("SUB"   , "SUB"   , (T31 << 26) + ( 40 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1848.   AddReg3("SUBFC" , "SF"    , (T31 << 26) + (  8 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1849.   AddReg3("SUBC"  , "SUBC"  , (T31 << 26) + (  8 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1850.   AddReg3("SUBFE" , "SFE"   , (T31 << 26) + (136 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True , True );
  1851.   AddReg3("TLBSX" , "TLBSX" , (T31 << 26) + (914 << 1),         M_403C                                 , False, True );
  1852.  
  1853.   /* cD,cA,cB --> D A B */
  1854.  
  1855.   InstrZ = 0;
  1856.   AddCReg3("CRAND"  , (T19 << 26) + (257 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1857.   AddCReg3("CRANDC" , (T19 << 26) + (129 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1858.   AddCReg3("CREQV"  , (T19 << 26) + (289 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1859.   AddCReg3("CRNAND" , (T19 << 26) + (225 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1860.   AddCReg3("CRNOR"  , (T19 << 26) + ( 33 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1861.   AddCReg3("CROR"   , (T19 << 26) + (449 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1862.   AddCReg3("CRORC"  , (T19 << 26) + (417 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1863.   AddCReg3("CRXOR"  , (T19 << 26) + (193 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1864.  
  1865.   /* fD,fA,fB --> D A B */
  1866.  
  1867.   InstrZ = 0;
  1868.   AddFReg3("FADD"  , "FA"    , (T63 << 26) + (21 << 1), M_601 | M_6000, True );
  1869.   AddFReg3("FADDS" , "FADDS" , (T59 << 26) + (21 << 1), M_601 | M_6000, True );
  1870.   AddFReg3("FDIV"  , "FD"    , (T63 << 26) + (18 << 1), M_601 | M_6000, True );
  1871.   AddFReg3("FDIVS" , "FDIVS" , (T59 << 26) + (18 << 1), M_601 | M_6000, True );
  1872.   AddFReg3("FSUB"  , "FS"    , (T63 << 26) + (20 << 1), M_601 | M_6000, True );
  1873.  
  1874.   /* A,S,B --> S A B */
  1875.  
  1876.   InstrZ = 0;
  1877.   AddReg3Swap("AND"   , "AND"   , (T31 << 26) + (  28 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True );
  1878.   AddReg3Swap("ANDC"  , "ANDC"  , (T31 << 26) + (  60 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True );
  1879.   AddReg3Swap("ECOWX" , "ECOWX" , (T31 << 26) + ( 438 << 1),                          M_821 | M_601 | M_6000, False);
  1880.   AddReg3Swap("EQV"   , "EQV"   , (T31 << 26) + ( 284 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True );
  1881.   AddReg3Swap("MASKG" , "MASKG" , (T31 << 26) + (  29 << 1),                                          M_6000, True );
  1882.   AddReg3Swap("MASKIR", "MASKIR", (T31 << 26) + ( 541 << 1),                                          M_6000, True );
  1883.   AddReg3Swap("NAND"  , "NAND"  , (T31 << 26) + ( 476 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True );
  1884.   AddReg3Swap("NOR"   , "NOR"   , (T31 << 26) + ( 124 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True );
  1885.   AddReg3Swap("OR"    , "OR"    , (T31 << 26) + ( 444 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True );
  1886.   AddReg3Swap("ORC"   , "ORC"   , (T31 << 26) + ( 412 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True );
  1887.   AddReg3Swap("RRIB"  , "RRIB"  , (T31 << 26) + ( 537 << 1),                                          M_6000, True );
  1888.   AddReg3Swap("SLE"   , "SLE"   , (T31 << 26) + ( 153 << 1),                                          M_6000, True );
  1889.   AddReg3Swap("SLEQ"  , "SLEQ"  , (T31 << 26) + ( 217 << 1),                                          M_6000, True );
  1890.   AddReg3Swap("SLLQ"  , "SLLQ"  , (T31 << 26) + ( 216 << 1),                                          M_6000, True );
  1891.   AddReg3Swap("SLQ"   , "SLQ"   , (T31 << 26) + ( 152 << 1),                                          M_6000, True );
  1892.   AddReg3Swap("SLW"   , "SL"    , (T31 << 26) + (  24 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True );
  1893.   AddReg3Swap("SRAQ"  , "SRAQ"  , (T31 << 26) + ( 920 << 1),                                          M_6000, True );
  1894.   AddReg3Swap("SRAW"  , "SRA"   , (T31 << 26) + ( 792 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True );
  1895.   AddReg3Swap("SRE"   , "SRE"   , (T31 << 26) + ( 665 << 1),                                          M_6000, True );
  1896.   AddReg3Swap("SREA"  , "SREA"  , (T31 << 26) + ( 921 << 1),                                          M_6000, True );
  1897.   AddReg3Swap("SREQ"  , "SREQ"  , (T31 << 26) + ( 729 << 1),                                          M_6000, True );
  1898.   AddReg3Swap("SRLQ"  , "SRLQ"  , (T31 << 26) + ( 728 << 1),                                          M_6000, True );
  1899.   AddReg3Swap("SRQ"   , "SRQ"   , (T31 << 26) + ( 664 << 1),                                          M_6000, True );
  1900.   AddReg3Swap("SRW"   , "SR"    , (T31 << 26) + ( 536 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True );
  1901.   AddReg3Swap("XOR"   , "XOR"   , (T31 << 26) + ( 316 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000,True );
  1902.  
  1903.   /* fD,A,B --> D A B */
  1904.  
  1905.   InstrZ = 0;
  1906.   AddMixed("LFDUX" , "LFDUX" , (T31 << 26) + (631 << 1), M_601 | M_6000);
  1907.   AddMixed("LFDX"  , "LFDX"  , (T31 << 26) + (599 << 1), M_601 | M_6000);
  1908.   AddMixed("LFSUX" , "LFSUX" , (T31 << 26) + (567 << 1), M_601 | M_6000);
  1909.   AddMixed("LFSX"  , "LFSX"  , (T31 << 26) + (535 << 1), M_601 | M_6000);
  1910.   AddMixed("STFDUX", "STFDUX", (T31 << 26) + (759 << 1), M_601 | M_6000);
  1911.   AddMixed("STFDX" , "STFDX" , (T31 << 26) + (727 << 1), M_601 | M_6000);
  1912.   AddMixed("STFSUX", "STFSUX", (T31 << 26) + (695 << 1), M_601 | M_6000);
  1913.   AddMixed("STFSX" , "STFSX" , (T31 << 26) + (663 << 1), M_601 | M_6000);
  1914.  
  1915.   /* fD,fA,fC,fB --> D A B C */
  1916.  
  1917.   InstrZ = 0;
  1918.   AddFReg4("FMADD"  , "FMA"    , (T63 << 26) + (29 << 1), M_601 | M_6000, True );
  1919.   AddFReg4("FMADDS" , "FMADDS" , (T59 << 26) + (29 << 1), M_601 | M_6000, True );
  1920.   AddFReg4("FMSUB"  , "FMS"    , (T63 << 26) + (28 << 1), M_601 | M_6000, True );
  1921.   AddFReg4("FMSUBS" , "FMSUBS" , (T59 << 26) + (28 << 1), M_601 | M_6000, True );
  1922.   AddFReg4("FNMADD" , "FNMA"   , (T63 << 26) + (31 << 1), M_601 | M_6000, True );
  1923.   AddFReg4("FNMADDS", "FNMADDS", (T59 << 26) + (31 << 1), M_601 | M_6000, True );
  1924.   AddFReg4("FNMSUB" , "FNMS"   , (T63 << 26) + (30 << 1), M_601 | M_6000, True );
  1925.   AddFReg4("FNMSUBS", "FNMSUBS", (T59 << 26) + (30 << 1), M_601 | M_6000, True );
  1926.  
  1927.   /* D,d(A) --> D A d */
  1928.  
  1929.   InstrZ = 0;
  1930.   AddRegDisp("LBZ"   , "LBZ"   , (T34 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1931.   AddRegDisp("LBZU"  , "LBZU"  , (T35 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1932.   AddRegDisp("LHA"   , "LHA"   , (T42 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1933.   AddRegDisp("LHAU"  , "LHAU"  , (T43 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1934.   AddRegDisp("LHZ"   , "LHZ"   , (T40 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1935.   AddRegDisp("LHZU"  , "LHZU"  , (T41 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1936.   AddRegDisp("LMW"   , "LM"    , (T46 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1937.   AddRegDisp("LWZ"   , "L"     , (T32 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1938.   AddRegDisp("LWZU"  , "LU"    , (T33 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1939.   AddRegDisp("STB"   , "STB"   , (T38 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1940.   AddRegDisp("STBU"  , "STBU"  , (T39 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1941.   AddRegDisp("STH"   , "STH"   , (T44 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1942.   AddRegDisp("STHU"  , "STHU"  , (T45 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1943.   AddRegDisp("STMW"  , "STM"   , (T47 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1944.   AddRegDisp("STW"   , "ST"    , (T36 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1945.   AddRegDisp("STWU"  , "STU"   , (T37 << 26), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1946.  
  1947.   /* fD,d(A) --> D A d */
  1948.  
  1949.   InstrZ = 0;
  1950.   AddFRegDisp("LFD"   , "LFD"   , (T50 << 26), M_601 | M_6000);
  1951.   AddFRegDisp("LFDU"  , "LFDU"  , (T51 << 26), M_601 | M_6000);
  1952.   AddFRegDisp("LFS"   , "LFS"   , (T48 << 26), M_601 | M_6000);
  1953.   AddFRegDisp("LFSU"  , "LFSU"  , (T49 << 26), M_601 | M_6000);
  1954.   AddFRegDisp("STFD"  , "STFD"  , (T54 << 26), M_601 | M_6000);
  1955.   AddFRegDisp("STFDU" , "STFDU" , (T55 << 26), M_601 | M_6000);
  1956.   AddFRegDisp("STFS"  , "STFS"  , (T52 << 26), M_601 | M_6000);
  1957.   AddFRegDisp("STFSU" , "STFSU" , (T53 << 26), M_601 | M_6000);
  1958.  
  1959.   /* A,S,Imm5 --> S A Imm */
  1960.  
  1961.   InstrZ = 0;
  1962.   AddReg2Imm("SLIQ"  , "SLIQ"  , (T31 << 26) + (184 << 1),                                          M_6000, True);
  1963.   AddReg2Imm("SLLIQ" , "SLLIQ" , (T31 << 26) + (248 << 1),                                          M_6000, True);
  1964.   AddReg2Imm("SRAIQ" , "SRAIQ" , (T31 << 26) + (952 << 1),                                          M_6000, True);
  1965.   AddReg2Imm("SRAWI" , "SRAI"  , (T31 << 26) + (824 << 1), M_403 | M_403C | M_505 | M_821 | M_601 | M_6000, True);
  1966.   AddReg2Imm("SRIQ"  , "SRIQ"  , (T31 << 26) + (696 << 1),                                          M_6000, True);
  1967.   AddReg2Imm("SRLIQ" , "SRLIQ" , (T31 << 26) + (760 << 1),                                          M_6000, True);
  1968.  
  1969.   /* D,A,Imm --> D A Imm */
  1970.  
  1971.   InstrZ = 0;
  1972.   AddImm16("ADDI"   , "CAL"    , T14 << 26, M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1973.   AddImm16("ADDIC"  , "AI"     , T12 << 26, M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1974.   AddImm16("ADDIC." , "AI."    , T13 << 26, M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1975.   AddImm16("ADDIS"  , "CAU"    , T15 << 26, M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1976.   AddImm16("DOZI"   , "DOZI"   ,  T9 << 26,                                          M_6000);
  1977.   AddImm16("MULLI"  , "MULI"   ,  T7 << 26, M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1978.   AddImm16("SUBFIC" , "SFI"    ,  T8 << 26, M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1979.  
  1980.   /* A,S,Imm --> S A Imm */
  1981.  
  1982.   InstrZ = 0;
  1983.   AddImm16Swap("ANDI."  , "ANDIL." , T28 << 26, M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1984.   AddImm16Swap("ANDIS." , "ANDIU." , T29 << 26, M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1985.   AddImm16Swap("ORI"    , "ORIL"   , T24 << 26, M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1986.   AddImm16Swap("ORIS"   , "ORIU"   , T25 << 26, M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1987.   AddImm16Swap("XORI"   , "XORIL"  , T26 << 26, M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1988.   AddImm16Swap("XORIS"  , "XORIU"  , T27 << 26, M_403 | M_403C | M_505 | M_821 | M_601 | M_6000);
  1989. }
  1990.  
  1991. static void DeinitFields(void)
  1992. {
  1993.   DestroyInstTable(InstTable);
  1994.   order_array_free(FixedOrders);
  1995.   order_array_free(Reg1Orders);
  1996.   order_array_free(FReg1Orders);
  1997.   order_array_free(CReg1Orders);
  1998.   order_array_free(CBit1Orders);
  1999.   order_array_free(Reg2Orders);
  2000.   order_array_free(CReg2Orders);
  2001.   order_array_free(FReg2Orders);
  2002.   order_array_free(Reg2BOrders);
  2003.   order_array_free(Reg2SwapOrders);
  2004.   order_array_free(NoDestOrders);
  2005.   order_array_free(Reg3Orders);
  2006.   order_array_free(CReg3Orders);
  2007.   order_array_free(FReg3Orders);
  2008.   order_array_free(Reg3SwapOrders);
  2009.   order_array_free(MixedOrders);
  2010.   order_array_free(FReg4Orders);
  2011.   order_array_free(RegDispOrders);
  2012.   order_array_free(FRegDispOrders);
  2013.   order_array_free(Reg2ImmOrders);
  2014.   order_array_free(Imm16Orders);
  2015.   order_array_free(Imm16SwapOrders);
  2016. }
  2017.  
  2018. /*-------------------------------------------------------------------------*/
  2019.  
  2020. static void MakeCode_601(void)
  2021. {
  2022.   CodeLen = 0;
  2023.   DontPrint = False;
  2024.  
  2025.   /* Nullanweisung */
  2026.  
  2027.   if (Memo("") && !*AttrPart.str.p_str && (ArgCnt == 0))
  2028.     return;
  2029.  
  2030.   /* Pseudoanweisungen */
  2031.  
  2032.   if (DecodeIntelPseudo(TargetBigEndian))
  2033.     return;
  2034.  
  2035.   if (!LookupInstTable(InstTable, OpPart.str.p_str))
  2036.     WrStrErrorPos(ErrNum_UnknownInstruction, &OpPart);
  2037. }
  2038.  
  2039. static Boolean IsDef_601(void)
  2040. {
  2041.   return Memo("REG");
  2042. }
  2043.  
  2044. /*!------------------------------------------------------------------------
  2045.  * \fn     InternSymbol_601(char *Asc, TempResult *Erg)
  2046.  * \brief  handle built.in symbols for PPC
  2047.  * \param  Asc source argument
  2048.  * \param  Erg result buffer
  2049.  * ------------------------------------------------------------------------ */
  2050.  
  2051. static void InternSymbol_601(char *Asc, TempResult *Erg)
  2052. {
  2053.   LongWord RegValue;
  2054.   int l = strlen(Asc);
  2055.  
  2056.   Erg->Typ = TempNone;
  2057.   if (((l == 3) || (l == 4))
  2058.    && ((as_toupper(*Asc) == 'C') && (as_toupper(Asc[1]) == 'R'))
  2059.    && ((Asc[l - 1] >= '0') && (Asc[l - 1] <= '7'))
  2060.    && ((l == 3) != ((as_toupper(Asc[2]) == 'F') || (as_toupper(Asc[3]) == 'B'))))
  2061.     as_tempres_set_int(Erg, Asc[l - 1] - '0');
  2062.   else if (DecodeGenRegCore(Asc, &RegValue))
  2063.   {
  2064.     Erg->Typ = TempReg;
  2065.     Erg->Contents.RegDescr.Dissect = DissectReg_601;
  2066.     Erg->Contents.RegDescr.compare = NULL;
  2067.     Erg->Contents.RegDescr.Reg = RegValue;
  2068.     Erg->DataSize = eSymbolSize32Bit;
  2069.   }
  2070.   else if (DecodeFPRegCore(Asc, &RegValue))
  2071.   {
  2072.     Erg->Typ = TempReg;
  2073.     Erg->Contents.RegDescr.Dissect = DissectReg_601;
  2074.     Erg->Contents.RegDescr.compare = NULL;
  2075.     Erg->Contents.RegDescr.Reg = RegValue;
  2076.     Erg->DataSize = eSymbolSizeFloat64Bit;
  2077.   }
  2078. }
  2079.  
  2080. static void SwitchTo_601(void)
  2081. {
  2082.   const TFamilyDescr *FoundDscr;
  2083.  
  2084.   TurnWords = True;
  2085.   SetIntConstMode(eIntConstModeC);
  2086.  
  2087.   FoundDscr = FindFamilyByName("MPC601");
  2088.   if (!FoundDscr)
  2089.     exit(255);
  2090.  
  2091.   PCSymbol = "*";
  2092.   HeaderID = FoundDscr->Id;
  2093.   NOPCode = 0x000000000;
  2094.   DivideChars = ",";
  2095.   HasAttrs = False;
  2096.  
  2097.   ValidSegs = (1 << SegCode);
  2098.   Grans[SegCode] = 1; ListGrans[SegCode] = 4; SegInits[SegCode] = 0;
  2099.   SegLimits[SegCode] = (LargeWord)IntTypeDefs[UInt32].Max;
  2100.  
  2101.   MakeCode = MakeCode_601;
  2102.   IsDef = IsDef_601;
  2103.   SwitchFrom = DeinitFields;
  2104.   InternSymbol = InternSymbol_601;
  2105.   DissectReg = DissectReg_601;
  2106.   onoff_supmode_add();
  2107.   onoff_bigendian_add();
  2108.  
  2109.   InitFields();
  2110. }
  2111.  
  2112. void code601_init(void)
  2113. {
  2114.   CPU403  = AddCPU("PPC403", SwitchTo_601);
  2115.   CPU403C = AddCPU("PPC403GC", SwitchTo_601);
  2116.   CPU505  = AddCPU("MPC505", SwitchTo_601);
  2117.   CPU601  = AddCPU("MPC601", SwitchTo_601);
  2118.   CPU821  = AddCPU("MPC821", SwitchTo_601);
  2119.   CPU6000 = AddCPU("RS6000", SwitchTo_601);
  2120.  
  2121.   AddCopyright("Motorola MPC821 Additions (C) 2012 Marcin Cieslak");
  2122. }
  2123.