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  1. /* code3203x.c */
  2. /*****************************************************************************/
  3. /* SPDX-License-Identifier: GPL-2.0-only OR GPL-3.0-only                     */
  4. /*                                                                           */
  5. /* AS-Portierung                                                             */
  6. /*                                                                           */
  7. /* Codegenerator TMS320C3x/C4x-Familie                                       */
  8. /*                                                                           */
  9. /*****************************************************************************/
  10.  
  11. #include "stdinc.h"
  12. #include <ctype.h>
  13. #include <string.h>
  14.  
  15. #include "nls.h"
  16. #include "be_le.h"
  17. #include "bpemu.h"
  18. #include "strutil.h"
  19. #include "chunks.h"
  20. #include "asmdef.h"
  21. #include "asmsub.h"
  22. #include "asmpars.h"
  23. #include "asmcode.h"
  24. #include "asmitree.h"
  25. #include "codepseudo.h"
  26. #include "codevars.h"
  27. #include "tipseudo.h"
  28. #include "headids.h"
  29. #include "onoff_common.h"
  30. #include "errmsg.h"
  31.  
  32. #include "code3203x.h"
  33.  
  34. typedef struct
  35. {
  36.   LongWord Code;
  37. } FixedOrder;
  38.  
  39. typedef struct
  40. {
  41.   int NameLen;
  42.   CPUVar MinCPU;
  43.   Boolean May1, May3;
  44.   Word Code, Code3;
  45.   Boolean OnlyMem;
  46.   Boolean SwapOps;
  47.   Boolean ImmFloat;
  48.   Boolean Commutative;
  49.   ShortInt ParMask, Par3Mask;
  50.   unsigned ParIndex, ParIndex3;
  51.   Byte PCodes[8], P3Codes[8];
  52. } GenOrder;
  53.  
  54. typedef struct
  55. {
  56.   LongWord Code;
  57.   Byte Mask;
  58. } SingOrder;
  59.  
  60. typedef struct
  61. {
  62.   const GenOrder *pOrder;
  63.   Boolean Is3;
  64.   ShortInt Src2Mode, Src1Mode, DestMode;
  65.   Word Src2Part, Src1Part, DestPart;
  66. } tGenOrderInfo;
  67.  
  68. static CPUVar CPU32030, CPU32031,
  69.               CPU32040, CPU32044;
  70.  
  71. static Boolean NextPar, ThisPar;
  72. static Byte PrevARs, ARs;
  73. static char PrevOp[7];
  74. static tGenOrderInfo PrevGenInfo;
  75.  
  76. static FixedOrder *FixedOrders;
  77. static GenOrder *GenOrders;
  78. static SingOrder *SingOrders;
  79.  
  80. static LongInt DPValue;
  81.  
  82. static const char ParOrders[][6] =
  83. {
  84.   "LDF",   "LDI",
  85.   "STF",   "STI",
  86.   "ADDF3", "SUBF3",
  87.   "ADDI3", "SUBI3"
  88. };
  89.  
  90. /*-------------------------------------------------------------------------*/
  91. /* Adressparser */
  92.  
  93. /* do not change this enum, since it is defined the way as needed in the machine
  94.    code G field! */
  95.  
  96. #define ModNone (-1)
  97. #define ModReg 0
  98. #define MModReg (1 << ModReg)
  99. #define ModDir 1
  100. #define MModDir (1 << ModDir)
  101. #define ModInd 2
  102. #define MModInd (1 << ModInd)
  103. #define ModImm 3
  104. #define MModImm (1 << ModImm)
  105.  
  106. static ShortInt AdrMode;
  107. static LongInt AdrPart;
  108.  
  109. /* special registers with address 0x10... vary: */
  110.  
  111. #define ARxRegStart 0x08
  112. #define CxxRegStart 0x10
  113. static const char *C4XRegs[] =
  114. { "DP", "IR0", "IR1", "BK", "SP", "ST", "DIE", "IIE", "IIF", "RS", "RE", "RC", NULL },
  115.                   *C3XRegs[] =
  116. { "DP", "IR0", "IR1", "BK", "SP", "ST", "IE" , "IF" , "IOF", "RS", "RE", "RC", NULL },
  117.                   **CxxRegs;
  118. static const char *ExpRegs[] =
  119. { "IVTP", "TVTP", NULL };
  120.  
  121. static Boolean Is4x(void)
  122. {
  123.   return MomCPU >= CPU32040;
  124. }
  125.  
  126. static Boolean DecodeReg(const char *Asc, Byte *Erg)
  127. {
  128.   if ((as_toupper(*Asc) == 'R') && (strlen(Asc) <= 3) && (strlen(Asc) >= 2))
  129.   {
  130.     Boolean OK;
  131.  
  132.     *Erg = ConstLongInt(Asc + 1, &OK, 10);
  133.  
  134.     /* For C3x, tolerate R8...R27 as aliases for other registers for backward compatibility.
  135.        For C4x, four new registers R8...R11 are mapped at register file address 28..31.
  136.        So for C4x, only allow the defined R0..11 registers: */
  137.  
  138.     if (OK)
  139.       OK = *Erg <= Is4x() ? 11 : 27;
  140.     if (OK)
  141.     {
  142.       if (Is4x() && (*Erg >= 8))
  143.         *Erg += 20;
  144.       return True;
  145.     }
  146.   }
  147.  
  148.   if ((strlen(Asc) == 3)
  149.    && (as_toupper(*Asc) == 'A') && (as_toupper(Asc[1]) == 'R')
  150.    && (Asc[2] >= '0') && (Asc[2] <= '7'))
  151.   {
  152.     *Erg = Asc[2] - '0' + ARxRegStart;
  153.     return True;
  154.   }
  155.  
  156.   for (*Erg = 0; CxxRegs[*Erg]; (*Erg)++)
  157.     if (!as_strcasecmp(CxxRegs[*Erg], Asc))
  158.     {
  159.       *Erg += CxxRegStart;
  160.       return True;
  161.     }
  162.  
  163.   return False;
  164. }
  165.  
  166. static Boolean DecodeExpReg(const char *Asc, Byte *Erg)
  167. {
  168.   for (*Erg = 0; ExpRegs[*Erg]; (*Erg)++)
  169.     if (!as_strcasecmp(ExpRegs[*Erg], Asc))
  170.       return True;
  171.  
  172.   return False;
  173. }
  174.  
  175. static void DecodeAdr(const tStrComp *pArg, Byte Erl, Boolean ImmFloat)
  176. {
  177.   Byte HReg;
  178.   Integer Disp;
  179.   char *p;
  180.   int l;
  181.   Double f;
  182.   Word fi;
  183.   LongInt AdrLong;
  184.   Boolean BitRev, Circ;
  185.   Boolean OK;
  186.   enum
  187.   {
  188.     ModBase, ModAdd, ModSub, ModPreInc, ModPreDec, ModPostInc, ModPostDec
  189.   } Mode;
  190.   tStrComp Arg;
  191.  
  192.   StrCompRefRight(&Arg, pArg, 0);
  193.   KillPrefBlanksStrCompRef(&Arg);
  194.   KillPostBlanksStrComp(&Arg);
  195.  
  196.   AdrMode = ModNone;
  197.  
  198.   /* I. Register? */
  199.  
  200.   if (DecodeReg(Arg.str.p_str, &HReg))
  201.   {
  202.     AdrMode = ModReg; AdrPart = HReg;
  203.     goto chk;
  204.   }
  205.  
  206.   /* II. indirekt ? */
  207.  
  208.   if (*Arg.str.p_str == '*')
  209.   {
  210.     /* II.1. Erkennungszeichen entfernen */
  211.  
  212.     StrCompIncRefLeft(&Arg, 1);;
  213.  
  214.     /* II.2. Extrawuerste erledigen */
  215.  
  216.     BitRev = False;
  217.     Circ = False;
  218.     l = strlen(Arg.str.p_str);
  219.     if ((l > 0) && (as_toupper(Arg.str.p_str[l - 1]) == 'B'))
  220.     {
  221.       BitRev = True;
  222.       StrCompShorten(&Arg, 1);
  223.       --l;
  224.     }
  225.     else if ((l > 0) && (Arg.str.p_str[l - 1] == '%'))
  226.     {
  227.       Circ = True;
  228.       StrCompShorten(&Arg, 1);
  229.       --l;
  230.     }
  231.  
  232.     /* II.3. Displacement entfernen und auswerten:
  233.             0..255-->Displacement
  234.             -1,-2 -->IR0,IR1
  235.             -3    -->Default */
  236.  
  237.     p = QuotPos(Arg.str.p_str, '(');
  238.     if (p)
  239.     {
  240.       tStrComp NDisp;
  241.  
  242.       if (Arg.str.p_str[l - 1] != ')')
  243.       {
  244.         WrError(ErrNum_InvAddrMode);
  245.         return;
  246.       }
  247.       StrCompSplitRef(&Arg, &NDisp, &Arg, p);
  248.       StrCompShorten(&NDisp, 1);
  249.       if (!as_strcasecmp(NDisp.str.p_str, "IR0"))
  250.         Disp = -1;
  251.       else if (!as_strcasecmp(NDisp.str.p_str, "IR1"))
  252.         Disp = -2;
  253.       else
  254.       {
  255.         Disp = EvalStrIntExpression(&NDisp, UInt8, &OK);
  256.         if (!OK)
  257.           return;
  258.       }
  259.     }
  260.     else
  261.       Disp = -3;
  262.  
  263.     /* II.4. Addieren/Subtrahieren mit/ohne Update? */
  264.  
  265.     l = strlen(Arg.str.p_str);
  266.     if (*Arg.str.p_str == '-')
  267.     {
  268.       if (Arg.str.p_str[1] == '-')
  269.       {
  270.         Mode = ModPreDec;
  271.         StrCompIncRefLeft(&Arg, 2);
  272.       }
  273.       else
  274.       {
  275.         Mode = ModSub;
  276.         StrCompIncRefLeft(&Arg, 1);
  277.       }
  278.     }
  279.     else if (*Arg.str.p_str == '+')
  280.     {
  281.       if (Arg.str.p_str[1] == '+')
  282.       {
  283.         Mode = ModPreInc;
  284.         StrCompIncRefLeft(&Arg, 2);
  285.       }
  286.       else
  287.       {
  288.         Mode = ModAdd;
  289.         StrCompIncRefLeft(&Arg, 1);
  290.       }
  291.     }
  292.     else if (Arg.str.p_str[l - 1] == '-')
  293.     {
  294.       if (Arg.str.p_str[l - 2] == '-')
  295.       {
  296.         Mode = ModPostDec;
  297.         StrCompShorten(&Arg, 2);
  298.       }
  299.       else
  300.       {
  301.         WrError(ErrNum_InvAddrMode);
  302.         return;
  303.       }
  304.     }
  305.     else if (Arg.str.p_str[l - 1] == '+')
  306.     {
  307.       if (Arg.str.p_str[l - 2] == '+')
  308.       {
  309.         Mode = ModPostInc;
  310.         StrCompShorten(&Arg, 2);
  311.       }
  312.       else
  313.       {
  314.         WrError(ErrNum_InvAddrMode);
  315.         return;
  316.       }
  317.     }
  318.     else
  319.       Mode = ModBase;
  320.  
  321.     /* II.5. Rest muss Basisregister sein */
  322.  
  323.     if ((!DecodeReg(Arg.str.p_str, &HReg)) || (HReg < 8) || (HReg > 15))
  324.     {
  325.       WrError(ErrNum_InvAddrMode);
  326.       return;
  327.     }
  328.     HReg -= 8;
  329.     if ((ARs & (1l << HReg)) == 0)
  330.       ARs += 1l << HReg;
  331.     else
  332.       WrStrErrorPos(ErrNum_DoubleAdrRegUse, &Arg);
  333.  
  334.     /* II.6. Default-Displacement explizit machen */
  335.  
  336.     if (Disp == -3)
  337.      Disp = (Mode == ModBase) ? 0 : 1;
  338.  
  339.     /* II.7. Entscheidungsbaum */
  340.  
  341.     switch (Mode)
  342.     {
  343.       case ModBase:
  344.       case ModAdd:
  345.         if ((Circ) || (BitRev)) WrError(ErrNum_InvAddrMode);
  346.         else
  347.         {
  348.           switch (Disp)
  349.           {
  350.             case -2: AdrPart = 0x8000; break;
  351.             case -1: AdrPart = 0x4000; break;
  352.             case  0: AdrPart = 0xc000; break;
  353.             default: AdrPart = Disp;
  354.           }
  355.           AdrPart += ((Word)HReg) << 8;
  356.           AdrMode = ModInd;
  357.         }
  358.         break;
  359.       case ModSub:
  360.         if ((Circ) || (BitRev)) WrError(ErrNum_InvAddrMode);
  361.         else
  362.         {
  363.           switch (Disp)
  364.           {
  365.             case -2: AdrPart = 0x8800; break;
  366.             case -1: AdrPart = 0x4800; break;
  367.             case  0: AdrPart = 0xc000; break;
  368.             default: AdrPart = 0x0800 + Disp;
  369.           }
  370.           AdrPart += ((Word)HReg) << 8;
  371.           AdrMode = ModInd;
  372.         }
  373.         break;
  374.       case ModPreInc:
  375.         if ((Circ) || (BitRev)) WrError(ErrNum_InvAddrMode);
  376.         else
  377.         {
  378.           switch (Disp)
  379.           {
  380.             case -2: AdrPart = 0x9000; break;
  381.             case -1: AdrPart = 0x5000; break;
  382.             default: AdrPart = 0x1000 + Disp;
  383.           }
  384.           AdrPart += ((Word)HReg) << 8;
  385.           AdrMode = ModInd;
  386.         }
  387.         break;
  388.       case ModPreDec:
  389.         if ((Circ) || (BitRev)) WrError(ErrNum_InvAddrMode);
  390.         else
  391.         {
  392.           switch (Disp)
  393.           {
  394.             case -2: AdrPart = 0x9800; break;
  395.             case -1: AdrPart = 0x5800; break;
  396.             default: AdrPart = 0x1800 + Disp;
  397.           }
  398.           AdrPart += ((Word)HReg) << 8;
  399.           AdrMode = ModInd;
  400.         }
  401.         break;
  402.       case ModPostInc:
  403.         if (BitRev)
  404.         {
  405.           if (Disp != -1) WrError(ErrNum_InvAddrMode);
  406.           else
  407.           {
  408.             AdrPart = 0xc800 + (((Word)HReg) << 8);
  409.             AdrMode = ModInd;
  410.           }
  411.         }
  412.         else
  413.         {
  414.           switch (Disp)
  415.           {
  416.             case -2: AdrPart = 0xa000; break;
  417.             case -1: AdrPart = 0x6000; break;
  418.             default: AdrPart = 0x2000 + Disp;
  419.           }
  420.           if (Circ)
  421.             AdrPart += 0x1000;
  422.           AdrPart += ((Word)HReg) << 8;
  423.           AdrMode = ModInd;
  424.         }
  425.         break;
  426.       case ModPostDec:
  427.         if (BitRev) WrError(ErrNum_InvAddrMode);
  428.         else
  429.         {
  430.           switch (Disp)
  431.           {
  432.             case -2: AdrPart = 0xa800; break;
  433.             case -1: AdrPart = 0x6800; break;
  434.             default: AdrPart = 0x2800 + Disp; break;
  435.           }
  436.           if (Circ)
  437.              AdrPart += 0x1000;
  438.           AdrPart += ((Word)HReg) << 8;
  439.           AdrMode = ModInd;
  440.         }
  441.         break;
  442.     }
  443.  
  444.     goto chk;
  445.   }
  446.  
  447.   /* III. absolut */
  448.  
  449.   if (*Arg.str.p_str == '@')
  450.   {
  451.     AdrLong = EvalStrIntExpressionOffs(&Arg, 1, UInt24, &OK);
  452.     if (OK)
  453.     {
  454.       if ((DPValue != -1) && ((AdrLong >> 16) != DPValue))
  455.         WrError(ErrNum_InAccPage);
  456.       AdrMode = ModDir;
  457.       AdrPart = AdrLong & 0xffff;
  458.     }
  459.     goto chk;
  460.   }
  461.  
  462.   /* IV. immediate */
  463.  
  464.   if (ImmFloat)
  465.   {
  466.     f = EvalStrFloatExpression(&Arg, Float64, &OK);
  467.     if ((OK) && (ExtToTIC34xShort(f, &fi)))
  468.     {
  469.       AdrPart = fi;
  470.       AdrMode = ModImm;
  471.     }
  472.   }
  473.   else
  474.   {
  475.     AdrPart = EvalStrIntExpression(&Arg, Int16, &OK);
  476.     if (OK)
  477.     {
  478.       AdrPart &= 0xffff;
  479.       AdrMode = ModImm;
  480.     }
  481.   }
  482.  
  483. chk:
  484.   if ((AdrMode != ModNone) && (!(Erl & (1 << AdrMode))))
  485.   {
  486.     AdrMode = ModNone;
  487.     WrError(ErrNum_InvAddrMode);
  488.   }
  489. }
  490.  
  491. static Word EffPart(Byte Mode, Word Part)
  492. {
  493.   switch (Mode)
  494.   {
  495.     case ModReg:
  496.     case ModImm:
  497.       return Lo(Part);
  498.     case ModInd:
  499.       return Hi(Part);
  500.     default:
  501.       WrError(ErrNum_InternalError);
  502.       return 0;
  503.   }
  504. }
  505.  
  506. /*-------------------------------------------------------------------------*/
  507. /* Code-Erzeugung */
  508.  
  509. static void JudgePar(const GenOrder *Prim, int Sec, Byte *ErgMode, Byte *ErgCode)
  510. {
  511.   if (Sec > 3)
  512.     *ErgMode = 3;
  513.   else if (Prim->May3)
  514.     *ErgMode = 1;
  515.   else
  516.     *ErgMode = 2;
  517.   *ErgCode = (*ErgMode == 2) ? Prim->PCodes[Sec] : Prim->P3Codes[Sec];
  518. }
  519.  
  520. static LongWord EvalAdrExpression(const tStrComp *pArg, Boolean *OK, tSymbolFlags *pFlags)
  521. {
  522.   return EvalStrIntExpressionOffsWithFlags(pArg, !!(*pArg->str.p_str == '@'), UInt24, OK, pFlags);
  523. }
  524.  
  525. static void SwapMode(ShortInt *M1, ShortInt *M2)
  526. {
  527.   AdrMode = (*M1);
  528.   *M1 = (*M2);
  529.   *M2 = AdrMode;
  530. }
  531.  
  532. static void SwapPart(Word *P1, Word *P2)
  533. {
  534.   AdrPart = (*P1);
  535.   *P1 = (*P2);
  536.   *P2 = AdrPart;
  537. }
  538.  
  539. static int MatchParIndex(Byte Mask, int Index)
  540. {
  541.   return ((Index >= 0) && (Mask & (1 << Index))) ? Index : -1;
  542. }
  543.  
  544. /*-------------------------------------------------------------------------*/
  545. /* Instruction Decoders */
  546.  
  547.  /* ohne Argument */
  548.  
  549. static void DecodeFixed(Word Index)
  550. {
  551.   if (!ChkArgCnt(0, 0));
  552.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  553.   else
  554.   {
  555.     DAsmCode[0] = FixedOrders[Index].Code;
  556.     CodeLen = 1;
  557.   }
  558.   NextPar = False;
  559. }
  560.  
  561. /* Arithmetik/Logik */
  562.  
  563. static Boolean Gen3IndirectAllowed(LongWord ThisAdrPart)
  564. {
  565.   /* indirect addressing mode fits into 3-op, non-par instruction if it needs no
  566.      displacement, i.e. the 'displacement' is IR0/IR1/special, or it is one: */
  567.  
  568.   return ((ThisAdrPart & 0xc000) || (Lo(ThisAdrPart) == 1));
  569. }
  570.  
  571. static Boolean Is4xArDisp(ShortInt ThisAdrMode, LongWord ThisAdrPart)
  572. {
  573.   return (ThisAdrMode == ModInd)
  574.       && ((ThisAdrPart & 0xf800) == 0x0000)
  575.       && (Lo(ThisAdrPart) != 1)  /* prefer C3x format if displacement=1 */
  576.       && (Lo(ThisAdrPart) <= 31);
  577. }
  578.  
  579. static void DecodeGen(Word Index)
  580. {
  581.   Byte HReg, HReg2, Sum;
  582.   String Form;
  583.   tGenOrderInfo CurrGenInfo;
  584.   LongWord T21_22 = 0, T28 = 0;
  585.   const tStrComp *pArg[4];
  586.   int ActArgCnt;
  587.  
  588.   NextPar = False;
  589.  
  590.   CurrGenInfo.pOrder = GenOrders + (Index & ~0x8000);
  591.   CurrGenInfo.Is3 = (Index & 0x8000) || FALSE;
  592.  
  593.   if (!ChkMinCPU(CurrGenInfo.pOrder->MinCPU))
  594.     return;
  595.  
  596.   for (ActArgCnt = 0; ActArgCnt <= ArgCnt; ActArgCnt++)
  597.     pArg[ActArgCnt] = &ArgStr[ActArgCnt];
  598.   ActArgCnt = ArgCnt;
  599.  
  600.   /* Argumentzahl abgleichen */
  601.  
  602.   if (ActArgCnt == 1)
  603.   {
  604.     if (CurrGenInfo.pOrder->May1)
  605.     {
  606.       ActArgCnt = 2;
  607.       pArg[2] = pArg[1];
  608.     }
  609.     else
  610.     {
  611.       (void)ChkArgCntExt(ActArgCnt, 2, 2);
  612.       return;
  613.     }
  614.   }
  615.   if ((ActArgCnt == 3) && (!CurrGenInfo.Is3))
  616.     CurrGenInfo.Is3 = True;
  617.  
  618.   if ((CurrGenInfo.pOrder->SwapOps) && (!CurrGenInfo.Is3))
  619.   {
  620.     pArg[3] = pArg[1];
  621.     pArg[1] = pArg[2];
  622.     pArg[2] = pArg[3];
  623.   }
  624.   if ((CurrGenInfo.Is3) && (ActArgCnt == 2))
  625.   {
  626.     ActArgCnt = 3;
  627.     pArg[3] = pArg[2];
  628.   }
  629.   if ((ActArgCnt < 2) || (ActArgCnt > 3) || ((CurrGenInfo.Is3) && (!CurrGenInfo.pOrder->May3)))
  630.   {
  631.     (void)ChkArgCntExt(ActArgCnt, 3, 3);
  632.     return;
  633.   }
  634.  
  635.   /* Argumente parsen */
  636.  
  637.   if (CurrGenInfo.Is3)
  638.   {
  639.     if (Memo("TSTB3"))
  640.     {
  641.       CurrGenInfo.DestMode = ModReg;
  642.       CurrGenInfo.DestPart = 0;
  643.     }
  644.     else
  645.     {
  646.       DecodeAdr(pArg[3], MModReg, CurrGenInfo.pOrder->ImmFloat);
  647.       if (AdrMode == ModNone)
  648.         return;
  649.       CurrGenInfo.DestMode = AdrMode;
  650.       CurrGenInfo.DestPart = AdrPart;
  651.     }
  652.  
  653.     /* The C4x type 2 format may use an immediate operand only if it is an
  654.        integer operation - there is no 8-bit represenataion of floats. */
  655.  
  656.     DecodeAdr(pArg[1],
  657.               MModReg | MModInd | ((Is4x() && !CurrGenInfo.pOrder->ImmFloat) ? MModImm : 0),
  658.               CurrGenInfo.pOrder->ImmFloat);
  659.     if (AdrMode == ModNone)
  660.       return;
  661.  
  662.     /* src2 is immediate or *+ARn(udisp5): C4x type 2 format */
  663.  
  664.     if (AdrMode == ModImm)
  665.     {
  666.       T28 = 1ul << 28;
  667.     }
  668.     else if (Is4x() && Is4xArDisp(AdrMode, AdrPart))
  669.     {
  670.       /* note that for type 2, bit 21 defines addressing mode of src2 and bit 22
  671.          defines addressing mode of src1, which is the opposite of the type 1 format! */
  672.  
  673.       T21_22 |= 1ul << 21;
  674.       T28 = 1ul << 28;
  675.       AdrPart = ((Word)(Hi(AdrPart) & 7) | (Lo(AdrPart) << 3)) << 8;
  676.     }
  677.  
  678.     /* type 1/C3x format: check whether indirect mode is 'short': */
  679.  
  680.     else if (AdrMode == ModInd)
  681.     {
  682.       if (!Gen3IndirectAllowed(AdrPart))
  683.       {
  684.         WrError(ErrNum_InvAddrMode);
  685.         return;
  686.       }
  687.       T21_22 |= 1ul << 22;
  688.     }
  689.     CurrGenInfo.Src2Mode = AdrMode;
  690.     CurrGenInfo.Src2Part = AdrPart;
  691.  
  692.     DecodeAdr(pArg[2], MModReg | MModInd, CurrGenInfo.pOrder->ImmFloat);
  693.     if (AdrMode == ModNone)
  694.       return;
  695.  
  696.     /* if type 2, the only indirect mode allowed for src1 is *+ARn(udisp5): */
  697.  
  698.     if (T28)
  699.     {
  700.       if (AdrMode == ModInd)
  701.       {
  702.         if (!Is4xArDisp(AdrMode, AdrPart))
  703.         {
  704.           WrError(ErrNum_InvAddrMode);
  705.           return;
  706.         }
  707.         else
  708.           AdrPart = ((Word)(Hi(AdrPart) & 7) | (Lo(AdrPart) << 3)) << 8;
  709.         T21_22 |= 1ul << 22;
  710.       }
  711.     }
  712.  
  713.     /* type 1/C3x format: similar check for src1 for 'short' adressing: */
  714.  
  715.     else if (AdrMode == ModInd)
  716.     {
  717.       if (!Gen3IndirectAllowed(AdrPart))
  718.       {
  719.         WrError(ErrNum_InvAddrMode);
  720.         return;
  721.       }
  722.       T21_22 |= 1ul << 21;
  723.     }
  724.     CurrGenInfo.Src1Mode = AdrMode;
  725.     CurrGenInfo.Src1Part = AdrPart;
  726.   }
  727.   else /* !CurrGenInfo.Is3 */
  728.   {
  729.     DecodeAdr(pArg[1], MModDir + MModInd + ((CurrGenInfo.pOrder->OnlyMem) ? 0 : MModReg + MModImm), CurrGenInfo.pOrder->ImmFloat);
  730.     if (AdrMode == ModNone)
  731.       return;
  732.     CurrGenInfo.Src2Mode = AdrMode;
  733.     CurrGenInfo.Src2Part = AdrPart;
  734.     DecodeAdr(pArg[2], MModReg + MModInd, CurrGenInfo.pOrder->ImmFloat);
  735.     switch (AdrMode)
  736.     {
  737.       case ModReg:
  738.         CurrGenInfo.DestMode = AdrMode;
  739.         CurrGenInfo.DestPart = AdrPart;
  740.         CurrGenInfo.Src1Mode = CurrGenInfo.Src2Mode;
  741.         CurrGenInfo.Src1Part = CurrGenInfo.Src2Part;
  742.         break;
  743.       case ModInd:
  744.         if (((strcmp(OpPart.str.p_str, "TSTB")) && (strcmp(OpPart.str.p_str, "CMPI")) && (strcmp(OpPart.str.p_str, "CMPF")))
  745.         ||  ((CurrGenInfo.Src2Mode == ModDir) || (CurrGenInfo.Src2Mode == ModImm))
  746.         ||  ((CurrGenInfo.Src2Mode == ModInd) && ((CurrGenInfo.Src2Part & 0xe000) == 0) && (Lo(CurrGenInfo.Src2Part) != 1))
  747.         ||  (((AdrPart & 0xe000) == 0) && (Lo(AdrPart) != 1)))
  748.         {
  749.           WrError(ErrNum_InvAddrMode);
  750.           return;
  751.         }
  752.         else
  753.         {
  754.           CurrGenInfo.Is3 = True;
  755.           CurrGenInfo.DestMode = ModReg;
  756.           CurrGenInfo.DestPart = 0;
  757.           CurrGenInfo.Src1Mode = AdrMode;
  758.           CurrGenInfo.Src1Part = AdrPart;
  759.         }
  760.         break;
  761.       case ModNone:
  762.         return;
  763.     }
  764.   }
  765.  
  766.   /* auswerten: parallel... */
  767.  
  768.   if (ThisPar)
  769.   {
  770.     int ParIndex;
  771.     unsigned ARIndex;
  772.  
  773.     if (!PrevGenInfo.pOrder)
  774.     {
  775.       WrError(ErrNum_ParNotPossible);
  776.       return;
  777.     }
  778.  
  779.     /* in Standardreihenfolge suchen */
  780.  
  781.     ParIndex = MatchParIndex(PrevGenInfo.Is3 ? PrevGenInfo.pOrder->Par3Mask : PrevGenInfo.pOrder->ParMask,
  782.                              CurrGenInfo.Is3 ? CurrGenInfo.pOrder->ParIndex3 : CurrGenInfo.pOrder->ParIndex);
  783.     if (ParIndex >= 0)
  784.       JudgePar(PrevGenInfo.pOrder, ParIndex, &HReg, &HReg2);
  785.  
  786.     /* in gedrehter Reihenfolge suchen */
  787.  
  788.     else
  789.     {
  790.       ParIndex = MatchParIndex(CurrGenInfo.Is3 ? CurrGenInfo.pOrder->Par3Mask : CurrGenInfo.pOrder->ParMask,
  791.                                PrevGenInfo.Is3 ? PrevGenInfo.pOrder->ParIndex3 : PrevGenInfo.pOrder->ParIndex);
  792.       if (ParIndex >= 0)
  793.       {
  794.         JudgePar(CurrGenInfo.pOrder, ParIndex, &HReg, &HReg2);
  795.         SwapMode(&CurrGenInfo.DestMode, &PrevGenInfo.DestMode);
  796.         SwapMode(&CurrGenInfo.Src2Mode, &PrevGenInfo.Src2Mode);
  797.         SwapMode(&CurrGenInfo.Src1Mode, &PrevGenInfo.Src1Mode);
  798.         SwapPart(&CurrGenInfo.DestPart, &PrevGenInfo.DestPart);
  799.         SwapPart(&CurrGenInfo.Src2Part, &PrevGenInfo.Src2Part);
  800.         SwapPart(&CurrGenInfo.Src1Part, &PrevGenInfo.Src1Part);
  801.       }
  802.       else
  803.       {
  804.         WrError(ErrNum_ParNotPossible);
  805.         return;
  806.       }
  807.     }
  808.  
  809.     /* mehrfache Registernutzung ? */
  810.  
  811.     for (ARIndex = 0; ARIndex < 8; ARIndex++)
  812.       if (ARs & PrevARs & (1l << ARIndex))
  813.       {
  814.         as_snprintf(Form, sizeof(Form), "AR%d", (int)ARIndex);
  815.         WrXError(ErrNum_DoubleAdrRegUse, Form);
  816.       }
  817.  
  818.     /* 3 Basisfaelle */
  819.  
  820.     switch (HReg)
  821.     {
  822.       case 1:
  823.         if ((!strcmp(PrevOp, "LSH3")) || (!strcmp(PrevOp, "ASH3")) || (!strcmp(PrevOp, "SUBF3")) || (!strcmp(PrevOp, "SUBI3")))
  824.         {
  825.           SwapMode(&PrevGenInfo.Src2Mode, &PrevGenInfo.Src1Mode);
  826.           SwapPart(&PrevGenInfo.Src2Part, &PrevGenInfo.Src1Part);
  827.         }
  828.         if ((PrevGenInfo.DestPart > 7) || (CurrGenInfo.DestPart > 7))
  829.         {
  830.           WrError(ErrNum_InvReg);
  831.           return;
  832.         }
  833.  
  834.         /* Bei Addition und Multiplikation Kommutativitaet nutzen */
  835.  
  836.         if  ((PrevGenInfo.Src1Mode == ModInd) && (PrevGenInfo.Src2Mode == ModReg) && (PrevGenInfo.pOrder->Commutative))
  837.         {
  838.           SwapMode(&PrevGenInfo.Src2Mode, &PrevGenInfo.Src1Mode);
  839.           SwapPart(&PrevGenInfo.Src2Part, &PrevGenInfo.Src1Part);
  840.         }
  841.         if ((PrevGenInfo.Src1Mode != ModReg) || (PrevGenInfo.Src1Part > 7)
  842.          || (PrevGenInfo.Src2Mode != ModInd) || (CurrGenInfo.Src2Mode != ModInd))
  843.         {
  844.           WrError(ErrNum_InvParAddrMode);
  845.           return;
  846.         }
  847.         RetractWords(1);
  848.         DAsmCode[0] = 0xc0000000 + (((LongWord)HReg2) << 25)
  849.                     + (((LongWord)PrevGenInfo.DestPart) << 22)
  850.                     + (((LongWord)PrevGenInfo.Src1Part) << 19)
  851.                     + (((LongWord)CurrGenInfo.DestPart) << 16)
  852.                     + (CurrGenInfo.Src2Part & 0xff00) + Hi(PrevGenInfo.Src2Part);
  853.         CodeLen = 1;
  854.         NextPar = False;
  855.         break;
  856.       case 2:
  857.         if ((PrevGenInfo.DestPart > 7) || (CurrGenInfo.DestPart > 7))
  858.         {
  859.           WrError(ErrNum_InvReg);
  860.           return;
  861.         }
  862.         if ((PrevGenInfo.Src2Mode != ModInd) || (CurrGenInfo.Src2Mode != ModInd))
  863.         {
  864.           WrError(ErrNum_InvParAddrMode);
  865.           return;
  866.         }
  867.         RetractWords(1);
  868.         DAsmCode[0] = 0xc0000000 + (((LongWord)HReg2) << 25)
  869.                     + (((LongWord)PrevGenInfo.DestPart) << 22)
  870.                     + (CurrGenInfo.Src2Part & 0xff00) + Hi(PrevGenInfo.Src2Part);
  871.         if ((!strcmp(PrevOp, OpPart.str.p_str)) && (*OpPart.str.p_str == 'L'))
  872.         {
  873.           DAsmCode[0] += ((LongWord)CurrGenInfo.DestPart) << 19;
  874.           if (PrevGenInfo.DestPart == CurrGenInfo.DestPart) WrError(ErrNum_Unpredictable);
  875.         }
  876.         else
  877.           DAsmCode[0] += ((LongWord)CurrGenInfo.DestPart) << 16;
  878.         CodeLen = 1;
  879.         NextPar = False;
  880.         break;
  881.       case 3:
  882.         if ((PrevGenInfo.DestPart > 1) || (CurrGenInfo.DestPart<2) || (CurrGenInfo.DestPart > 3))
  883.         {
  884.           WrError(ErrNum_InvReg);
  885.           return;
  886.         }
  887.         Sum = 0;
  888.         if (PrevGenInfo.Src2Mode == ModInd) Sum++;
  889.         if (PrevGenInfo.Src1Mode == ModInd) Sum++;
  890.         if (CurrGenInfo.Src2Mode == ModInd) Sum++;
  891.         if (CurrGenInfo.Src1Mode == ModInd) Sum++;
  892.         if (Sum != 2)
  893.         {
  894.           WrError(ErrNum_InvParAddrMode);
  895.           return;
  896.         }
  897.         RetractWords(1);
  898.         DAsmCode[0] = 0x80000000 + (((LongWord)HReg2) << 26)
  899.                     + (((LongWord)PrevGenInfo.DestPart & 1) << 23)
  900.                     + (((LongWord)CurrGenInfo.DestPart & 1) << 22);
  901.         CodeLen = 1;
  902.         if (CurrGenInfo.Src1Mode == ModReg)
  903.         {
  904.           if (CurrGenInfo.Src2Mode == ModReg)
  905.           {
  906.             DAsmCode[0] += ((LongWord)0x00000000)
  907.                          + (((LongWord)CurrGenInfo.Src1Part) << 19)
  908.                          + (((LongWord)CurrGenInfo.Src2Part) << 16)
  909.                          + (PrevGenInfo.Src1Part & 0xff00) + Hi(PrevGenInfo.Src2Part);
  910.           }
  911.           else
  912.           {
  913.             DAsmCode[0] += ((LongWord)0x03000000)
  914.                          + (((LongWord)CurrGenInfo.Src1Part) << 16)
  915.                          + Hi(CurrGenInfo.Src2Part);
  916.             if (PrevGenInfo.Src2Mode == ModReg)
  917.               DAsmCode[0] += (((LongWord)PrevGenInfo.Src2Part) << 19) + (PrevGenInfo.Src1Part & 0xff00);
  918.             else
  919.               DAsmCode[0] += (((LongWord)PrevGenInfo.Src1Part) << 19) + (PrevGenInfo.Src2Part & 0xff00);
  920.           }
  921.         }
  922.         else
  923.         {
  924.           if (CurrGenInfo.Src2Mode == ModReg)
  925.           {
  926.             DAsmCode[0] += ((LongWord)0x01000000)
  927.                          + (((LongWord)CurrGenInfo.Src2Part) << 16)
  928.                          + Hi(CurrGenInfo.Src1Part);
  929.             if (PrevGenInfo.Src2Mode == ModReg)
  930.               DAsmCode[0] += (((LongWord)PrevGenInfo.Src2Part) << 19) + (PrevGenInfo.Src1Part & 0xff00);
  931.             else
  932.               DAsmCode[0] += (((LongWord)PrevGenInfo.Src1Part) << 19) + (PrevGenInfo.Src2Part & 0xff00);
  933.           }
  934.           else
  935.           {
  936.             DAsmCode[0] += ((LongWord)0x02000000)
  937.                          + (((LongWord)PrevGenInfo.Src1Part) << 19)
  938.                          + (((LongWord)PrevGenInfo.Src2Part) << 16)
  939.                          + (CurrGenInfo.Src1Part & 0xff00) + Hi(CurrGenInfo.Src2Part);
  940.           }
  941.         }
  942.         break;
  943.     }
  944.   }
  945.   /* ...sequentiell */
  946.   else
  947.   {
  948.     strcpy(PrevOp, OpPart.str.p_str);
  949.     PrevARs = ARs;
  950.     PrevGenInfo = CurrGenInfo;
  951.     if (CurrGenInfo.Is3)
  952.       DAsmCode[0] = 0x20000000 | T28 | (((LongWord)CurrGenInfo.pOrder->Code3) << 23) | T21_22
  953.                   | (((LongWord)CurrGenInfo.DestPart) << 16)
  954.                   | (EffPart(CurrGenInfo.Src1Mode, CurrGenInfo.Src1Part) << 8)
  955.                   | EffPart(CurrGenInfo.Src2Mode, CurrGenInfo.Src2Part);
  956.     else
  957.       DAsmCode[0] = 0x00000000 | (((LongWord)CurrGenInfo.pOrder->Code) << 23)
  958.                   | (((LongWord)CurrGenInfo.Src2Mode) << 21)
  959.                   | CurrGenInfo.Src2Part
  960.                   | (((LongWord)CurrGenInfo.DestPart) << 16);
  961.     CodeLen = 1;
  962.     NextPar = True;
  963.   }
  964. }
  965.  
  966. /* Due to the way it is executed in the instruction pipeline, LDA has some restrictions
  967.    on its operands: only ARx, DP-SP allowed as destination, and source+dest reg cannot be same register */
  968.  
  969. static void DecodeLDA(Word Code)
  970. {
  971.   Byte HReg;
  972.  
  973.   if (!ChkArgCnt(2, 2));
  974.   else if (!ChkMinCPU(CPU32040));
  975.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  976.   else if (!DecodeReg(ArgStr[2].str.p_str, &HReg)) WrStrErrorPos(ErrNum_InvReg, &ArgStr[2]);
  977.   else if ((HReg < 8) || (HReg > 20)) WrStrErrorPos(ErrNum_InvReg, &ArgStr[2]);
  978.   else
  979.   {
  980.     Boolean RegClash;
  981.  
  982.     DecodeAdr(&ArgStr[1], MModReg | MModInd | MModDir | MModImm, False);
  983.     switch (AdrMode)
  984.     {
  985.       case ModDir:
  986.       case ModImm:
  987.         RegClash = False;
  988.         break;
  989.       case ModReg:
  990.         RegClash = (AdrPart == HReg);
  991.         break;
  992.       case ModInd:
  993.         if ((Hi(AdrPart) & 7) + ARxRegStart == HReg)
  994.           RegClash = True;
  995.         else if (((AdrPart & 0xc000) == 0x4000) && (HReg == 0x11))
  996.           RegClash = True;
  997.         else if (((AdrPart & 0xc000) == 0x8000) && (HReg == 0x12))
  998.           RegClash = True;
  999.         else if (((AdrPart & 0xf800) == 0xc800) && (HReg == 0x11))
  1000.           RegClash = True;
  1001.         else
  1002.           RegClash = False;
  1003.         break;
  1004.       default:
  1005.         return;
  1006.     }
  1007.     if (RegClash) WrError(ErrNum_InvRegPair);
  1008.     else
  1009.     {
  1010.       DAsmCode[0] = (((LongWord)Code) << 23)
  1011.                   | (((LongWord)AdrMode) << 21)
  1012.                   | (((LongWord)HReg) << 16)
  1013.                   | AdrPart;
  1014.       CodeLen = 1;
  1015.     }
  1016.   }
  1017.   NextPar = False;
  1018. }
  1019.  
  1020. static void DecodeRot(Word Code)
  1021. {
  1022.   Byte HReg;
  1023.  
  1024.   if (!ChkArgCnt(1, 1));
  1025.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1026.   else if (!DecodeReg(ArgStr[1].str.p_str, &HReg)) WrError(ErrNum_InvAddrMode);
  1027.   else
  1028.   {
  1029.     DAsmCode[0] = 0x11e00000 + (((LongWord)Code) << 23) + (((LongWord)HReg) << 16);
  1030.     CodeLen = 1;
  1031.   }
  1032.   NextPar = False;
  1033. }
  1034.  
  1035. static void DecodeStk(Word Code)
  1036. {
  1037.   Byte HReg;
  1038.  
  1039.   if (!ChkArgCnt(1, 1));
  1040.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1041.   else if (!DecodeReg(ArgStr[1].str.p_str, &HReg)) WrError(ErrNum_InvAddrMode);
  1042.   else
  1043.   {
  1044.     DAsmCode[0] = 0x0e200000 + (((LongWord)Code) << 23) + (((LongWord)HReg) << 16);
  1045.     CodeLen = 1;
  1046.   }
  1047.   NextPar = False;
  1048. }
  1049.  
  1050. /* Datentransfer */
  1051.  
  1052. static void DecodeLDIcc_LDFcc(Word Code)
  1053. {
  1054.   LongWord CondCode = Lo(Code), InstrCode = ((LongWord)Hi(Code)) << 24;
  1055.   Byte HReg;
  1056.  
  1057.   if (!ChkArgCnt(2, 2));
  1058.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1059.   else
  1060.   {
  1061.     DecodeAdr(&ArgStr[2], MModReg, False);
  1062.     if (AdrMode != ModNone)
  1063.     {
  1064.       HReg = AdrPart;
  1065.       DecodeAdr(&ArgStr[1], MModReg + MModDir + MModInd + MModImm, InstrCode == 0x40000000);
  1066.       if (AdrMode != ModNone)
  1067.       {
  1068.         DAsmCode[0] = InstrCode + (((LongWord)HReg) << 16)
  1069.                     + (CondCode << 23)
  1070.                     + (((LongWord)AdrMode) << 21) + AdrPart;
  1071.         CodeLen = 1;
  1072.       }
  1073.     }
  1074.     NextPar = False;
  1075.   }
  1076. }
  1077.  
  1078. /* Sonderfall NOP auch ohne Argumente */
  1079.  
  1080. static void DecodeNOP(Word Code)
  1081. {
  1082.   UNUSED(Code);
  1083.  
  1084.   if (ArgCnt == 0)
  1085.   {
  1086.     CodeLen = 1;
  1087.     DAsmCode[0] = NOPCode;
  1088.   }
  1089.   else if (!ChkArgCnt(1, 1));
  1090.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1091.   else
  1092.   {
  1093.     DecodeAdr(&ArgStr[1], 5, False);
  1094.     if (AdrMode != ModNone)
  1095.     {
  1096.       DAsmCode[0] = 0x0c800000 + (((LongWord)AdrMode) << 21) + AdrPart;
  1097.       CodeLen = 1;
  1098.     }
  1099.   }
  1100.   NextPar = False;
  1101. }
  1102.  
  1103. /* Sonderfaelle */
  1104.  
  1105. static void DecodeSing(Word Index)
  1106. {
  1107.   const SingOrder *pOrder = SingOrders + Index;
  1108.  
  1109.   if (!ChkArgCnt(1, 1));
  1110.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1111.   else
  1112.   {
  1113.     DecodeAdr(&ArgStr[1], pOrder->Mask, False);
  1114.     if (AdrMode != ModNone)
  1115.     {
  1116.       DAsmCode[0] = pOrder->Code + (((LongWord)AdrMode) << 21) + AdrPart;
  1117.       CodeLen = 1;
  1118.     }
  1119.   }
  1120.   NextPar = False;
  1121. }
  1122.  
  1123. static void DecodeLDP(Word Code)
  1124. {
  1125.   UNUSED(Code);
  1126.  
  1127.   if (!ChkArgCnt(1, 2));
  1128.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1129.   else if ((ArgCnt == 2) && (as_strcasecmp(ArgStr[2].str.p_str, "DP"))) WrError(ErrNum_InvAddrMode);
  1130.   else
  1131.   {
  1132.     Boolean OK;
  1133.     tSymbolFlags Flags;
  1134.     LongInt AdrLong = EvalAdrExpression(&ArgStr[1], &OK, &Flags);
  1135.  
  1136.     if (OK)
  1137.     {
  1138.       DAsmCode[0] = 0x08700000 + (AdrLong >> 16);
  1139.       CodeLen = 1;
  1140.     }
  1141.   }
  1142.   NextPar = False;
  1143. }
  1144.  
  1145. static void DecodeLdExp(Word Code)
  1146. {
  1147.   Boolean Swapped = (Code & 1) || False;
  1148.   Byte Src, Dest;
  1149.  
  1150.   if (!ChkArgCnt(2, 2));
  1151.   else if (!ChkMinCPU(CPU32040));
  1152.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1153.   else if (!(Swapped ? DecodeReg(ArgStr[1].str.p_str, &Src) : DecodeExpReg(ArgStr[1].str.p_str, &Src))) WrStrErrorPos(ErrNum_InvReg, &ArgStr[1]);
  1154.   else if (!(Swapped ? DecodeExpReg(ArgStr[2].str.p_str, &Dest) : DecodeReg(ArgStr[2].str.p_str, &Dest))) WrStrErrorPos(ErrNum_InvReg, &ArgStr[2]);
  1155.   else
  1156.   {
  1157.     DAsmCode[0] = (((LongWord)Code) << 23)
  1158.                 | (((LongWord)Dest) << 16)
  1159.                 | (((LongWord)Src) << 0);
  1160.     CodeLen = 1;
  1161.   }
  1162.   NextPar = False;
  1163. }
  1164.  
  1165. static void DecodeRegImm(Word Code)
  1166. {
  1167.   Byte Dest;
  1168.  
  1169.   if (!ChkArgCnt(2, 2));
  1170.   else if (!ChkMinCPU(CPU32040));
  1171.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1172.   else if (!DecodeReg(ArgStr[2].str.p_str, &Dest)) WrStrErrorPos(ErrNum_InvReg, &ArgStr[2]);
  1173.   else
  1174.   {
  1175.     DecodeAdr(&ArgStr[1], MModImm, False);
  1176.     if (AdrMode == ModImm)
  1177.     {
  1178.       DAsmCode[0] = (((LongWord)Code) << 23)
  1179.                   | (((LongWord)AdrMode) << 21)
  1180.                   | (((LongWord)Dest) << 16)
  1181.                   | AdrPart;
  1182.       CodeLen = 1;
  1183.     }
  1184.   }
  1185.   NextPar = False;
  1186. }
  1187.  
  1188. static void DecodeLDPK(Word Code)
  1189. {
  1190.   Byte Dest;
  1191.  
  1192.   if (!ChkArgCnt(1, 1));
  1193.   else if (!ChkMinCPU(CPU32040));
  1194.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1195.   else if (!DecodeReg("DP", &Dest)) WrXError(ErrNum_InvReg, "DP");
  1196.   else
  1197.   {
  1198.     DecodeAdr(&ArgStr[1], MModImm, False);
  1199.     if (AdrMode == ModImm)
  1200.     {
  1201.       DAsmCode[0] = (((LongWord)Code) << 23)
  1202.                   | (((LongWord)AdrMode) << 21)
  1203.                   | (((LongWord)Dest) << 16)
  1204.                   | AdrPart;
  1205.       CodeLen = 1;
  1206.     }
  1207.   }
  1208.   NextPar = False;
  1209. }
  1210.  
  1211. static void DecodeSTIK(Word Code)
  1212. {
  1213.   if (!ChkArgCnt(2, 2));
  1214.   else if (!ChkMinCPU(CPU32040));
  1215.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1216.   else
  1217.   {
  1218.     Boolean OK;
  1219.     LongInt Src = EvalStrIntExpression(&ArgStr[1], SInt5, &OK);
  1220.  
  1221.     if (OK)
  1222.     {
  1223.       DecodeAdr(&ArgStr[2], MModInd | MModDir, False);
  1224.  
  1225.       if (AdrMode != ModNone)
  1226.       {
  1227.         AdrMode = (AdrMode == ModInd) ? 3 : 0;
  1228.         Src = (Src << 16) & 0x001f0000ul;
  1229.         DAsmCode[0] = (((LongWord)Code) << 23)
  1230.                     | (((LongWord)AdrMode) << 21)
  1231.                     | Src
  1232.                     | AdrPart;
  1233.         CodeLen = 1;
  1234.       }
  1235.     }
  1236.   }
  1237.   NextPar = False;
  1238. }
  1239.  
  1240. /* Schleifen */
  1241.  
  1242. static void DecodeRPTB_C3x(Word Code)
  1243. {
  1244.   UNUSED(Code);
  1245.  
  1246.   if (!ChkArgCnt(1, 1));
  1247.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1248.   else
  1249.   {
  1250.     Boolean OK;
  1251.     tSymbolFlags Flags;
  1252.     LongInt AdrLong = EvalAdrExpression(&ArgStr[1], &OK, &Flags);
  1253.  
  1254.     if (OK)
  1255.     {
  1256.       DAsmCode[0] = 0x64000000 + AdrLong;
  1257.       CodeLen = 1;
  1258.     }
  1259.   }
  1260.   NextPar = False;
  1261. }
  1262.  
  1263. static void DecodeRPTB_C4x(Word Code)
  1264. {
  1265.   Byte Reg;
  1266.  
  1267.   UNUSED(Code);
  1268.  
  1269.   if (!ChkArgCnt(1, 1));
  1270.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1271.   else if (DecodeReg(ArgStr[1].str.p_str, &Reg))
  1272.   {
  1273.     DAsmCode[0] = 0x79000000 | Reg;
  1274.     CodeLen = 1;
  1275.   }
  1276.   else
  1277.   {
  1278.     Boolean OK;
  1279.     tSymbolFlags Flags;
  1280.     LongInt AdrLong = EvalAdrExpression(&ArgStr[1], &OK, &Flags) - (EProgCounter() + 1);
  1281.  
  1282.     if (OK)
  1283.     {
  1284.       if (!mSymbolQuestionable(Flags) && ((AdrLong > 0x7fffffl) || (AdrLong < -0x800000l))) WrError(ErrNum_JmpDistTooBig);
  1285.       else
  1286.       {
  1287.         DAsmCode[0] = 0x64000000 + AdrLong;
  1288.         CodeLen = 1;
  1289.       }
  1290.     }
  1291.   }
  1292.   NextPar = False;
  1293. }
  1294.  
  1295. /* Spruenge */
  1296.  
  1297. /* note that BR/BRD/CALL/(LAJ) take an absolute 24-bit address on C3x,
  1298.    but a 24-bit displacement on C4x. So we use different decoders for
  1299.    C3x and C4x: */
  1300.  
  1301. static void DecodeBR_BRD_CALL_C3x(Word Code)
  1302. {
  1303.   Byte InstrCode = Lo(Code);
  1304.  
  1305.   if (!ChkArgCnt(1, 1));
  1306.   else if (InstrCode == 0x63) (void)ChkMinCPU(CPU32040); /* no LAJ on C3x */
  1307.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1308.   else
  1309.   {
  1310.     Boolean OK;
  1311.     tSymbolFlags Flags;
  1312.     LongInt AdrLong = EvalAdrExpression(&ArgStr[1], &OK, &Flags);
  1313.  
  1314.     if (OK)
  1315.     {
  1316.       DAsmCode[0] = (((LongWord)Code) << 24) + AdrLong;
  1317.       CodeLen = 1;
  1318.     }
  1319.   }
  1320.   NextPar = False;
  1321. }
  1322.  
  1323. static void DecodeBR_BRD_CALL_LAJ_C4x(Word Code)
  1324. {
  1325.   Byte InstrCode = Lo(Code), Dist = Hi(Code);
  1326.  
  1327.   if (!ChkArgCnt(1, 1));
  1328.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1329.   else
  1330.   {
  1331.     Boolean OK;
  1332.     tSymbolFlags Flags;
  1333.     LongInt AdrLong = EvalAdrExpression(&ArgStr[1], &OK, &Flags) - (EProgCounter() + Dist);
  1334.  
  1335.     if (OK)
  1336.     {
  1337.       if (!mSymbolQuestionable(Flags) && ((AdrLong > 0x7fffffl) || (AdrLong < -0x800000l))) WrError(ErrNum_JmpDistTooBig);
  1338.       else
  1339.       {
  1340.         DAsmCode[0] = (((LongWord)InstrCode) << 24) + (AdrLong & 0xffffff);
  1341.         CodeLen = 1;
  1342.       }
  1343.     }
  1344.   }
  1345.   NextPar = False;
  1346. }
  1347.  
  1348. static void DecodeBcc(Word Code)
  1349. {
  1350.   LongWord CondCode = Lo(Code) & 0x7f,
  1351.            DFlag = ((LongWord)Hi(Code)) << 21;
  1352.   LongInt Disp = DFlag ? 3 : 1;
  1353.   Byte HReg;
  1354.  
  1355.   if (!ChkArgCnt(1, 1));
  1356.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1357.   else if ((Code & 0x80) && !ChkMinCPU(CPU32040));
  1358.   else if (DecodeReg(ArgStr[1].str.p_str, &HReg))
  1359.   {
  1360.     DAsmCode[0] = 0x68000000 + (CondCode << 16) + DFlag + HReg;
  1361.     CodeLen = 1;
  1362.   }
  1363.   else
  1364.   {
  1365.     Boolean OK;
  1366.     tSymbolFlags Flags;
  1367.     LongInt AdrLong = EvalAdrExpression(&ArgStr[1], &OK, &Flags) - (EProgCounter() + Disp);
  1368.  
  1369.     if (OK)
  1370.     {
  1371.       if (!mSymbolQuestionable(Flags) && ((AdrLong > 0x7fffl) || (AdrLong < -0x8000l))) WrError(ErrNum_JmpDistTooBig);
  1372.       else
  1373.       {
  1374.         DAsmCode[0] = 0x6a000000 + (CondCode << 16) + DFlag + (AdrLong & 0xffff);
  1375.         CodeLen = 1;
  1376.       }
  1377.     }
  1378.   }
  1379.   NextPar = False;
  1380. }
  1381.  
  1382. static void DecodeCALLcc(Word Code)
  1383. {
  1384.   Byte HReg;
  1385.  
  1386.   if (!ChkArgCnt(1, 1));
  1387.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1388.   else if (DecodeReg(ArgStr[1].str.p_str, &HReg))
  1389.   {
  1390.     DAsmCode[0] = 0x70000000 + (((LongWord)Code) << 16) + HReg;
  1391.     CodeLen = 1;
  1392.   }
  1393.   else
  1394.   {
  1395.     Boolean OK;
  1396.     tSymbolFlags Flags;
  1397.     LongInt AdrLong = EvalAdrExpression(&ArgStr[1], &OK, &Flags) - (EProgCounter() + 1);
  1398.  
  1399.     if (OK)
  1400.     {
  1401.       if (!mSymbolQuestionable(Flags) && ((AdrLong > 0x7fffl) || (AdrLong < -0x8000l))) WrError(ErrNum_JmpDistTooBig);
  1402.       else
  1403.       {
  1404.         DAsmCode[0] = 0x72000000 + (((LongWord)Code) << 16) + (AdrLong & 0xffff);
  1405.         CodeLen = 1;
  1406.       }
  1407.     }
  1408.   }
  1409.   NextPar = False;
  1410. }
  1411.  
  1412. static void DecodeDBcc(Word Code)
  1413. {
  1414.   LongWord CondCode = Lo(Code),
  1415.            DFlag = ((LongWord)Hi(Code)) << 21;
  1416.   LongInt Disp = DFlag ? 3 : 1;
  1417.   Byte HReg, HReg2;
  1418.  
  1419.   if (!ChkArgCnt(2, 2));
  1420.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1421.   else if (!DecodeReg(ArgStr[1].str.p_str, &HReg2)) WrError(ErrNum_InvAddrMode);
  1422.   else if ((HReg2 < 8) || (HReg2 > 15)) WrError(ErrNum_InvAddrMode);
  1423.   else
  1424.   {
  1425.     HReg2 -= 8;
  1426.     if (DecodeReg(ArgStr[2].str.p_str, &HReg))
  1427.     {
  1428.       DAsmCode[0] = 0x6c000000
  1429.                   + (CondCode << 16)
  1430.                   + DFlag
  1431.                   + (((LongWord)HReg2) << 22)
  1432.                   + HReg;
  1433.       CodeLen = 1;
  1434.     }
  1435.     else
  1436.     {
  1437.       Boolean OK;
  1438.       tSymbolFlags Flags;
  1439.       LongInt AdrLong = EvalAdrExpression(&ArgStr[2], &OK, &Flags) - (EProgCounter() + Disp);
  1440.  
  1441.       if (OK)
  1442.       {
  1443.         if (!mSymbolQuestionable(Flags) && ((AdrLong > 0x7fffl) || (AdrLong < -0x8000l))) WrError(ErrNum_JmpDistTooBig);
  1444.         else
  1445.         {
  1446.           DAsmCode[0] = 0x6e000000
  1447.                       + (CondCode << 16)
  1448.                       + DFlag
  1449.                       + (((LongWord)HReg2) << 22)
  1450.                       + (AdrLong & 0xffff);
  1451.           CodeLen = 1;
  1452.         }
  1453.       }
  1454.     }
  1455.   }
  1456.   NextPar = False;
  1457. }
  1458.  
  1459. static void DecodeRETIcc_RETScc(Word Code)
  1460. {
  1461.   LongWord CondCode = Lo(Code),
  1462.            DFlag = ((LongWord)Hi(Code)) << 21;
  1463.  
  1464.   if (!ChkArgCnt(0, 0));
  1465.   else if ((DFlag & (1ul << 21)) && !ChkMinCPU(CPU32040));
  1466.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1467.   else
  1468.   {
  1469.     DAsmCode[0] = 0x78000000 + DFlag + (CondCode << 16);
  1470.     CodeLen = 1;
  1471.   }
  1472.   NextPar = False;
  1473. }
  1474.  
  1475. static void DecodeTRAPcc(Word Code)
  1476. {
  1477.   if (!ChkArgCnt(1, 1));
  1478.   else if ((Code & 0x80) && !ChkMinCPU(CPU32040));
  1479.   else if (ThisPar) WrError(ErrNum_ParNotPossible);
  1480.   else
  1481.   {
  1482.     Boolean OK;
  1483.     LongWord HReg = EvalStrIntExpression(&ArgStr[1], Is4x() ? UInt9 : UInt4, &OK);
  1484.  
  1485.     if (OK)
  1486.     {
  1487.       DAsmCode[0] = 0x74000000 + HReg + (((LongWord)Code) << 16);
  1488.       CodeLen = 1;
  1489.     }
  1490.   }
  1491.   NextPar = False;
  1492. }
  1493.  
  1494. /*-------------------------------------------------------------------------*/
  1495. /* Befehlstabellenverwaltung */
  1496.  
  1497. static void AddCondition(const char *NName, Byte NCode)
  1498. {
  1499.   char InstName[30];
  1500.  
  1501.   if (*NName)
  1502.   {
  1503.     as_snprintf(InstName, sizeof(InstName), "LDI%s", NName);
  1504.     AddInstTable(InstTable, InstName, 0x5000 | NCode, DecodeLDIcc_LDFcc);
  1505.     as_snprintf(InstName, sizeof(InstName), "LDF%s", NName);
  1506.     AddInstTable(InstTable, InstName, 0x4000 | NCode, DecodeLDIcc_LDFcc);
  1507.   }
  1508.   as_snprintf(InstName, sizeof(InstName), "B%s", NName);
  1509.   AddInstTable(InstTable, InstName, 0x0000 | NCode, DecodeBcc);
  1510.   as_snprintf(InstName, sizeof(InstName), "B%sD", NName);
  1511.   AddInstTable(InstTable, InstName, 0x0100 | NCode, DecodeBcc);
  1512.   as_snprintf(InstName, sizeof(InstName), "B%sAF", NName);
  1513.   AddInstTable(InstTable, InstName, 0x0580 | NCode, DecodeBcc);
  1514.   as_snprintf(InstName, sizeof(InstName), "B%sAT", NName);
  1515.   AddInstTable(InstTable, InstName, 0x0380 | NCode, DecodeBcc);
  1516.   if (*NName)
  1517.   {
  1518.     as_snprintf(InstName, sizeof(InstName), "LAJ%s", NName);
  1519.     AddInstTable(InstTable, InstName, 0x4180 | NCode, DecodeBcc);
  1520.     as_snprintf(InstName, sizeof(InstName), "CALL%s", NName);
  1521.     AddInstTable(InstTable, InstName, NCode, DecodeCALLcc);
  1522.   }
  1523.   as_snprintf(InstName, sizeof(InstName), "DB%s", NName);
  1524.   AddInstTable(InstTable, InstName, NCode, DecodeDBcc);
  1525.   as_snprintf(InstName, sizeof(InstName), "DB%sD", NName);
  1526.   AddInstTable(InstTable, InstName, 0x100 | NCode, DecodeDBcc);
  1527.   as_snprintf(InstName, sizeof(InstName), "RETI%s", NName);
  1528.   AddInstTable(InstTable, InstName, NCode, DecodeRETIcc_RETScc);
  1529.   as_snprintf(InstName, sizeof(InstName), "RETI%sD", NName);
  1530.   AddInstTable(InstTable, InstName, 0x100 | NCode, DecodeRETIcc_RETScc);
  1531.   as_snprintf(InstName, sizeof(InstName), "RETS%s", NName);
  1532.   AddInstTable(InstTable, InstName, 0x400 | NCode, DecodeRETIcc_RETScc);
  1533.   as_snprintf(InstName, sizeof(InstName), "TRAP%s", NName);
  1534.   AddInstTable(InstTable, InstName, NCode, DecodeTRAPcc);
  1535.   as_snprintf(InstName, sizeof(InstName), "LAT%s", NName);
  1536.   AddInstTable(InstTable, InstName, 0x80 | NCode, DecodeTRAPcc);
  1537. }
  1538.  
  1539. static void AddFixed(const char *NName, LongWord NCode)
  1540. {
  1541.   order_array_rsv_end(FixedOrders, FixedOrder);
  1542.   FixedOrders[InstrZ].Code = NCode;
  1543.   AddInstTable(InstTable, NName, InstrZ++, DecodeFixed);
  1544. }
  1545.  
  1546. static void AddSing(const char *NName, LongWord NCode, Byte NMask)
  1547. {
  1548.   order_array_rsv_end(SingOrders, SingOrder);
  1549.   SingOrders[InstrZ].Code = NCode;
  1550.   SingOrders[InstrZ].Mask = NMask;
  1551.   AddInstTable(InstTable, NName, InstrZ++, DecodeSing);
  1552. }
  1553.  
  1554. static void AddGen(const char *NName, CPUVar NMin, Boolean NMay1, Boolean NMay3,
  1555.                    Word NCode, Word NCode3,
  1556.                    Boolean NOnly, Boolean NSwap, Boolean NImm, Boolean NComm,
  1557.                    Byte NMask1, Byte NMask3,
  1558.                    Byte C20, Byte C21, Byte C22, Byte C23, Byte C24,
  1559.                    Byte C25, Byte C26, Byte C27, Byte C30, Byte C31,
  1560.                    Byte C32, Byte C33, Byte C34, Byte C35, Byte C36,
  1561.                    Byte C37)
  1562. {
  1563.   char NName3[30];
  1564.   size_t z;
  1565.  
  1566.   order_array_rsv_end(GenOrders, GenOrder);
  1567.  
  1568.   as_snprintf(NName3, sizeof(NName3), "%s3", NName);
  1569.  
  1570.   GenOrders[InstrZ].ParIndex =
  1571.   GenOrders[InstrZ].ParIndex3 = -1;
  1572.   for (z = 0; z < as_array_size(ParOrders); z++)
  1573.   {
  1574.     if (!strcmp(ParOrders[z], NName))
  1575.       GenOrders[InstrZ].ParIndex = z;
  1576.     if (!strcmp(ParOrders[z], NName3))
  1577.       GenOrders[InstrZ].ParIndex3 = z;
  1578.   }
  1579.  
  1580.   GenOrders[InstrZ].NameLen = strlen(NName);
  1581.   GenOrders[InstrZ].MinCPU = NMin;
  1582.   GenOrders[InstrZ].May1 = NMay1; GenOrders[InstrZ].May3 = NMay3;
  1583.   GenOrders[InstrZ].Code = NCode; GenOrders[InstrZ].Code3 = NCode3;
  1584.   GenOrders[InstrZ].OnlyMem = NOnly; GenOrders[InstrZ].SwapOps = NSwap;
  1585.   GenOrders[InstrZ].ImmFloat = NImm;
  1586.   GenOrders[InstrZ].Commutative = NComm;
  1587.   GenOrders[InstrZ].ParMask = NMask1; GenOrders[InstrZ].Par3Mask = NMask3;
  1588.   GenOrders[InstrZ].PCodes[0] = C20;  GenOrders[InstrZ].PCodes[1] = C21;
  1589.   GenOrders[InstrZ].PCodes[2] = C22;  GenOrders[InstrZ].PCodes[3] = C23;
  1590.   GenOrders[InstrZ].PCodes[4] = C24;  GenOrders[InstrZ].PCodes[5] = C25;
  1591.   GenOrders[InstrZ].PCodes[6] = C26;  GenOrders[InstrZ].PCodes[7] = C27;
  1592.   GenOrders[InstrZ].P3Codes[0] = C30; GenOrders[InstrZ].P3Codes[1] = C31;
  1593.   GenOrders[InstrZ].P3Codes[2] = C32; GenOrders[InstrZ].P3Codes[3] = C33;
  1594.   GenOrders[InstrZ].P3Codes[4] = C34; GenOrders[InstrZ].P3Codes[5] = C35;
  1595.   GenOrders[InstrZ].P3Codes[6] = C36; GenOrders[InstrZ].P3Codes[7] = C37;
  1596.  
  1597.   AddInstTable(InstTable, NName, InstrZ, DecodeGen);
  1598.   AddInstTable(InstTable, NName3, InstrZ | 0x8000, DecodeGen);
  1599.   InstrZ++;
  1600. }
  1601.  
  1602. static void InitFields(void)
  1603. {
  1604.   InstTable = CreateInstTable(607);
  1605.   SetDynamicInstTable(InstTable);
  1606.  
  1607.   AddInstTable(InstTable, "NOP", 0, DecodeNOP);
  1608.   AddInstTable(InstTable, "LDP", 0, DecodeLDP);
  1609.   AddInstTable(InstTable, "RPTB", 0, Is4x() ? DecodeRPTB_C4x : DecodeRPTB_C3x);
  1610.   AddInstTable(InstTable, "BR"  , 0x0160, Is4x() ? DecodeBR_BRD_CALL_LAJ_C4x : DecodeBR_BRD_CALL_C3x);
  1611.   AddInstTable(InstTable, "BRD" , 0x0361, Is4x() ? DecodeBR_BRD_CALL_LAJ_C4x : DecodeBR_BRD_CALL_C3x);
  1612.   AddInstTable(InstTable, "CALL", 0x0162, Is4x() ? DecodeBR_BRD_CALL_LAJ_C4x : DecodeBR_BRD_CALL_C3x);
  1613.   AddInstTable(InstTable, "LAJ" , 0x0363, Is4x() ? DecodeBR_BRD_CALL_LAJ_C4x : DecodeBR_BRD_CALL_C3x);
  1614.   AddTI34xPseudo(InstTable);
  1615.  
  1616.   AddCondition("U"  , 0x00); AddCondition("LO" , 0x01);
  1617.   AddCondition("LS" , 0x02); AddCondition("HI" , 0x03);
  1618.   AddCondition("HS" , 0x04); AddCondition("EQ" , 0x05);
  1619.   AddCondition("NE" , 0x06); AddCondition("LT" , 0x07);
  1620.   AddCondition("LE" , 0x08); AddCondition("GT" , 0x09);
  1621.   AddCondition("GE" , 0x0a); AddCondition("Z"  , 0x05);
  1622.   AddCondition("NZ" , 0x06); AddCondition("P"  , 0x09);
  1623.   AddCondition("N"  , 0x07); AddCondition("NN" , 0x0a);
  1624.   AddCondition("NV" , 0x0c); AddCondition("V"  , 0x0d);
  1625.   AddCondition("NUF", 0x0e); AddCondition("UF" , 0x0f);
  1626.   AddCondition("NC" , 0x04); AddCondition("C"  , 0x01);
  1627.   AddCondition("NLV", 0x10); AddCondition("LV" , 0x11);
  1628.   AddCondition("NLUF", 0x12);AddCondition("LUF", 0x13);
  1629.   AddCondition("ZUF", 0x14); AddCondition(""   , 0x00);
  1630.  
  1631.   InstrZ = 0;
  1632.   AddFixed("IDLE", 0x06000000); AddFixed("SIGI", 0x16000000);
  1633.   AddFixed("SWI" , 0x66000000);
  1634.  
  1635.   InstrZ = 0;
  1636.   AddInstTable(InstTable, "ROL" , InstrZ++, DecodeRot);
  1637.   AddInstTable(InstTable, "ROLC", InstrZ++, DecodeRot);
  1638.   AddInstTable(InstTable, "ROR" , InstrZ++, DecodeRot);
  1639.   AddInstTable(InstTable, "RORC", InstrZ++, DecodeRot);
  1640.  
  1641.   InstrZ = 0;
  1642.   AddInstTable(InstTable, "POP"  , InstrZ++, DecodeStk);
  1643.   AddInstTable(InstTable, "POPF" , InstrZ++, DecodeStk);
  1644.   AddInstTable(InstTable, "PUSH" , InstrZ++, DecodeStk);
  1645.   AddInstTable(InstTable, "PUSHF", InstrZ++, DecodeStk);
  1646.  
  1647.   AddInstTable(InstTable, "LDEP", 0x00ec, DecodeLdExp);
  1648.   AddInstTable(InstTable, "LDPE", 0x00ed, DecodeLdExp);
  1649.   AddInstTable(InstTable, "LDHI", 0x007f, DecodeRegImm);
  1650.   AddInstTable(InstTable, "LDPK", 0x003e, DecodeLDPK);
  1651.   AddInstTable(InstTable, "STIK", 0x002a, DecodeSTIK);
  1652.  
  1653.   InstrZ = 0;
  1654. /*        Name      MinCPU    May1   May3   Cd    Cd3   OnlyM  Swap   ImmF   Comm   PM1 PM3     */
  1655.   AddGen("ABSF"   , CPU32030, True , False, 0x00, 0xff, False, False, True , False, 4, 0,
  1656.          0xff, 0xff, 0x04, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1657.   AddGen("ABSI"   , CPU32030, True , False, 0x01, 0xff, False, False, False, False, 8, 0,
  1658.          0xff, 0xff, 0xff, 0x05, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1659.   AddGen("ADDC"   , CPU32030, False, True , 0x02, 0x00, False, False, False, True,  0, 0,
  1660.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1661.   AddGen("ADDF"   , CPU32030, False, True , 0x03, 0x01, False, False, True , True,  0, 4,
  1662.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0x06, 0xff, 0xff, 0xff, 0xff, 0xff);
  1663.   AddGen("ADDI"   , CPU32030, False, True , 0x04, 0x02, False, False, False, True,  0, 8,
  1664.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x07, 0xff, 0xff, 0xff, 0xff);
  1665.   AddGen("AND"    , CPU32030, False, True , 0x05, 0x03, False, False, False, True,  0, 8,
  1666.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x08, 0xff, 0xff, 0xff, 0xff);
  1667.   AddGen("ANDN"   , CPU32030, False, True , 0x06, 0x04, False, False, False, False, 0, 0,
  1668.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1669.   AddGen("ASH"    , CPU32030, False, True , 0x07, 0x05, False, False, False, False, 0, 8,
  1670.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x09, 0xff, 0xff, 0xff, 0xff);
  1671.   AddGen("CMPF"   , CPU32030, False, True , 0x08, 0x06, False, False, True , False, 0, 0,
  1672.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1673.   AddGen("CMPI"   , CPU32030, False, True , 0x09, 0x07, False, False, False, False, 0, 0,
  1674.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1675.   AddGen("FIX"    , CPU32030, True , False, 0x0a, 0xff, False, False, True , False, 8, 0,
  1676.          0xff, 0xff, 0xff, 0x0a, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1677.   AddGen("FLOAT"  , CPU32030, True , False, 0x0b, 0xff, False, False, False, False, 4, 0,
  1678.          0xff, 0xff, 0x0b, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1679.   AddGen("FRIEEE" , CPU32040, False, False, 0x38, 0xff, True , False, True , False, 4, 0,
  1680.          0xff, 0xff, 0x19, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1681.   AddGen("LB0"    , CPU32040, False, False,0x160, 0xff, False, False, False, False, 0, 0,
  1682.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1683.   AddGen("LB1"    , CPU32040, False, False,0x161, 0xff, False, False, False, False, 0, 0,
  1684.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1685.   AddGen("LB2"    , CPU32040, False, False,0x162, 0xff, False, False, False, False, 0, 0,
  1686.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1687.   AddGen("LB3"    , CPU32040, False, False,0x163, 0xff, False, False, False, False, 0, 0,
  1688.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1689.   AddGen("LBU0"   , CPU32040, False, False,0x164, 0xff, False, False, False, False, 0, 0,
  1690.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1691.   AddGen("LBU1"   , CPU32040, False, False,0x165, 0xff, False, False, False, False, 0, 0,
  1692.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1693.   AddGen("LBU2"   , CPU32040, False, False,0x166, 0xff, False, False, False, False, 0, 0,
  1694.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1695.   AddGen("LBU3"   , CPU32040, False, False,0x167, 0xff, False, False, False, False, 0, 0,
  1696.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1697.   AddGen("LH0"    , CPU32040, False, False,0x174, 0xff, False, False, False, False, 0, 0,
  1698.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1699.   AddGen("LH1"    , CPU32040, False, False,0x175, 0xff, False, False, False, False, 0, 0,
  1700.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1701.   AddGen("LHU0"   , CPU32040, False, False,0x176, 0xff, False, False, False, False, 0, 0,
  1702.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1703.   AddGen("LHU1"   , CPU32040, False, False,0x177, 0xff, False, False, False, False, 0, 0,
  1704.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1705.   AddGen("LDE"    , CPU32030, False, False, 0x0d, 0xff, False, False, True , False, 0, 0,
  1706.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1707.   AddGen("LDF"    , CPU32030, False, False, 0x0e, 0xff, False, False, True , False, 5, 0,
  1708.          0x02, 0xff, 0x0c, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1709.   AddGen("LDFI"   , CPU32030, False, False, 0x0f, 0xff, True , False, True , False, 0, 0,
  1710.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1711.   AddGen("LDI"    , CPU32030, False, False, 0x10, 0xff, False, False, False, False, 10, 0,
  1712.          0xff, 0x03, 0xff, 0x0d, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1713.   AddGen("LDII"   , CPU32030, False, False, 0x11, 0xff, True , False, False, False, 0, 0,
  1714.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1715.   AddGen("LDM"    , CPU32030, False, False, 0x12, 0xff, False, False, True , False, 0, 0,
  1716.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1717.   AddGen("LSH"    , CPU32030, False, True , 0x13, 0x08, False, False, False, False, 0, 8,
  1718.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1719.   AddGen("LWL0"   , CPU32040, False, False,0x168, 0xff, False, False, False, False, 0, 0,
  1720.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1721.   AddGen("LWL1"   , CPU32040, False, False,0x169, 0xff, False, False, False, False, 0, 0,
  1722.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1723.   AddGen("LWL2"   , CPU32040, False, False,0x16a, 0xff, False, False, False, False, 0, 0,
  1724.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1725.   AddGen("LWL3"   , CPU32040, False, False,0x16b, 0xff, False, False, False, False, 0, 0,
  1726.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1727.   AddGen("LWR0"   , CPU32040, False, False,0x16c, 0xff, False, False, False, False, 0, 0,
  1728.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1729.   AddGen("LWR1"   , CPU32040, False, False,0x16d, 0xff, False, False, False, False, 0, 0,
  1730.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1731.   AddGen("LWR2"   , CPU32040, False, False,0x16e, 0xff, False, False, False, False, 0, 0,
  1732.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1733.   AddGen("LWR3"   , CPU32040, False, False,0x16f, 0xff, False, False, False, False, 0, 0,
  1734.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1735.   AddGen("MB0"    , CPU32040, False, False,0x170, 0xff, False, False, False, False, 0, 0,
  1736.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1737.   AddGen("MB1"    , CPU32040, False, False,0x171, 0xff, False, False, False, False, 0, 0,
  1738.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1739.   AddGen("MB2"    , CPU32040, False, False,0x172, 0xff, False, False, False, False, 0, 0,
  1740.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1741.   AddGen("MB3"    , CPU32040, False, False,0x173, 0xff, False, False, False, False, 0, 0,
  1742.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1743.   AddGen("MH0"    , CPU32040, False, False,0x178, 0xff, False, False, False, False, 0, 0,
  1744.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1745.   AddGen("MH1"    , CPU32040, False, False,0x179, 0xff, False, False, False, False, 0, 0,
  1746.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x0e, 0xff, 0xff, 0xff, 0xff);
  1747.   AddGen("MPYF"   , CPU32030, False, True , 0x14, 0x09, False, False, True , True,  0,52,
  1748.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0x0f, 0xff, 0x00, 0x01, 0xff, 0xff);
  1749.   AddGen("MPYI"   , CPU32030, False, True , 0x15, 0x0a, False, False, False, True,  0,200,
  1750.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x10, 0xff, 0xff, 0x02, 0x03);
  1751.   AddGen("MPYSHI" , CPU32040, False, True , 0x3b, 0x11, False, False, False, True,  0, 0,
  1752.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1753.   AddGen("MPYUHI" , CPU32040, False, True , 0x3c, 0x12, False, False, False, True,  0, 0,
  1754.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1755.   AddGen("NEGB"   , CPU32030, True , False, 0x16, 0xff, False, False, False, False, 0, 0,
  1756.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1757.   AddGen("NEGF"   , CPU32030, True , False, 0x17, 0xff, False, False, True , False, 4, 0,
  1758.          0xff, 0xff, 0x11, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1759.   AddGen("NEGI"   , CPU32030, True , False, 0x18, 0xff, False, False, False, False, 8, 0,
  1760.          0xff, 0xff, 0xff, 0x12, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1761.   AddGen("NORM"   , CPU32030, True , False, 0x1a, 0xff, False, False, True , False, 0, 0,
  1762.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1763.   AddGen("NOT"    , CPU32030, True , False, 0x1b, 0xff, False, False, False, False, 8, 0,
  1764.          0xff, 0xff, 0xff, 0x13, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1765.   AddGen("OR"     , CPU32030, False, True , 0x20, 0x0b, False, False, False, True,  0, 8,
  1766.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x14, 0xff, 0xff, 0xff, 0xff);
  1767.   AddGen("RCPF"   , CPU32040, False, False, 0x3a, 0xff, False, False, True , False, 0, 0,
  1768.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x14, 0xff, 0xff, 0xff, 0xff);
  1769.   AddGen("RND"    , CPU32030, True , False, 0x22, 0xff, False, False, True , False, 0, 0,
  1770.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1771.   AddGen("RSQRF"  , CPU32040, False, False, 0x39, 0xff, False, False, True , False, 0, 0,
  1772.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x14, 0xff, 0xff, 0xff, 0xff);
  1773.   AddGen("STF"    , CPU32030, False, False, 0x28, 0xff, True , True , True , False, 4, 0,
  1774.          0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1775.   AddGen("STFI"   , CPU32030, False, False, 0x29, 0xff, True , True , True , False, 0, 0,
  1776.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1777.   AddGen("STI"    , CPU32030, False, False, 0x2a, 0xff, True , True , False, False, 8, 0,
  1778.          0xff, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1779.   AddGen("STII"   , CPU32030, False, False, 0x2b, 0xff, True , True , False, False, 0, 0,
  1780.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1781.   AddGen("SUBB"   , CPU32030, False, True , 0x2d, 0x0c, False, False, False, False, 0, 0,
  1782.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1783.   AddGen("SUBC"   , CPU32030, False, False, 0x2e, 0xff, False, False, False, False, 0, 0,
  1784.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1785.   AddGen("SUBF"   , CPU32030, False, True , 0x2f, 0x0d, False, False, True , False, 0, 4,
  1786.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0x15, 0xff, 0xff, 0xff, 0xff, 0xff);
  1787.   AddGen("SUBI"   , CPU32030, False, True , 0x30, 0x0e, False, False, False, False, 0, 8,
  1788.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x16, 0xff, 0xff, 0xff, 0xff);
  1789.   AddGen("SUBRB"  , CPU32030, False, False, 0x31, 0xff, False, False, False, False, 0, 0,
  1790.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1791.   AddGen("SUBRF"  , CPU32030, False, False, 0x32, 0xff, False, False, True , False, 0, 0,
  1792.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1793.   AddGen("SUBRI"  , CPU32030, False, False, 0x33, 0xff, False, False, False, False, 0, 0,
  1794.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1795.   AddGen("TOIEEE" , CPU32040, False, False, 0x37, 0xff, False, False, True , False, 4, 0,
  1796.          0xff, 0xff, 0x18, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1797.   AddGen("TSTB"   , CPU32030, False, True , 0x34, 0x0f, False, False, False, False, 0, 0,
  1798.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
  1799.   AddGen("XOR"    , CPU32030, False, True , 0x35, 0x10, False, False, False, True,  0, 8,
  1800.          0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0x17, 0xff, 0xff, 0xff, 0xff);
  1801.  
  1802.   InstrZ = 0;
  1803.   AddSing("IACK", 0x1b000000, 6);
  1804.   AddSing("RPTS", 0x139b0000, 15);
  1805.  
  1806.   AddInstTable(InstTable, "LDA", 0x03d, DecodeLDA);
  1807. }
  1808.  
  1809. static void DeinitFields(void)
  1810. {
  1811.   DestroyInstTable(InstTable);
  1812.  
  1813.   order_array_free(FixedOrders);
  1814.   order_array_free(GenOrders);
  1815.   order_array_free(SingOrders);
  1816. }
  1817.  
  1818. static void MakeCode_3203X(void)
  1819. {
  1820.   CodeLen = 0;
  1821.   DontPrint = False;
  1822.  
  1823.   ThisPar = (!strcmp(LabPart.str.p_str, "||"));
  1824.   if ((strlen(OpPart.str.p_str) > 2) && (!strncmp(OpPart.str.p_str, "||", 2)))
  1825.   {
  1826.     ThisPar = True;
  1827.     strmov(OpPart.str.p_str, OpPart.str.p_str + 2);
  1828.   }
  1829.   if ((!NextPar) && (ThisPar))
  1830.   {
  1831.     WrError(ErrNum_ParNotPossible);
  1832.     return;
  1833.   }
  1834.   ARs = 0;
  1835.  
  1836.   /* zu ignorierendes */
  1837.  
  1838.   if (Memo(""))
  1839.     return;
  1840.  
  1841.   if (!LookupInstTable(InstTable, OpPart.str.p_str))
  1842.   {
  1843.     WrStrErrorPos(ErrNum_UnknownInstruction, &OpPart);
  1844.     NextPar = False;
  1845.   }
  1846. }
  1847.  
  1848. static void InitCode_3203x(void)
  1849. {
  1850.   DPValue = 0;
  1851. }
  1852.  
  1853. static Boolean IsDef_3203X(void)
  1854. {
  1855.   return (!strcmp(LabPart.str.p_str, "||"));
  1856. }
  1857.  
  1858. static void SwitchFrom_3203X(void)
  1859. {
  1860.   DeinitFields();
  1861. }
  1862.  
  1863. static void SwitchTo_3203X(void)
  1864. {
  1865. #define ASSUME3203Count sizeof(ASSUME3203s) / sizeof(*ASSUME3203s)
  1866.   static ASSUMERec ASSUME3203s[] =
  1867.   {
  1868.     { "DP", &DPValue, -1, 0xff, 0x100, NULL }
  1869.   };
  1870.   const TFamilyDescr *pDescr;
  1871.  
  1872.   pDescr = FindFamilyByName("TMS320C3x/C4x");
  1873.  
  1874.   TurnWords = False;
  1875.   SetIntConstMode(eIntConstModeIntel);
  1876.  
  1877.   PCSymbol = "$";
  1878.   HeaderID = pDescr->Id;
  1879.   NOPCode = 0x0c800000;
  1880.   DivideChars = ",";
  1881.   HasAttrs = False;
  1882.  
  1883.   ValidSegs = 1 << SegCode;
  1884.   Grans[SegCode] = 4; ListGrans[SegCode] = 4; SegInits[SegCode] = 0;
  1885.   if (MomCPU == CPU32040)
  1886.   {
  1887.     SegLimits[SegCode] = 0xfffffffful;
  1888.     CxxRegs = C4XRegs;
  1889.   }
  1890.   else if (MomCPU == CPU32044)
  1891.   {
  1892.     SegLimits[SegCode] = 0x1ffffful;
  1893.     CxxRegs = C4XRegs;
  1894.   }
  1895.   else /* C3x */
  1896.   {
  1897.     SegLimits[SegCode] = 0xfffffful;
  1898.     CxxRegs = C3XRegs;
  1899.   }
  1900.  
  1901.   onoff_packing_add(True);
  1902.  
  1903.   pASSUMERecs = ASSUME3203s;
  1904.   ASSUMERecCnt = ASSUME3203Count;
  1905.  
  1906.   MakeCode = MakeCode_3203X;
  1907.   IsDef = IsDef_3203X;
  1908.   SwitchFrom = SwitchFrom_3203X;
  1909.   InitFields();
  1910.   NextPar = False;
  1911. }
  1912.  
  1913. void code3203x_init(void)
  1914. {
  1915.   CPU32030 = AddCPU("320C30", SwitchTo_3203X);
  1916.   CPU32031 = AddCPU("320C31", SwitchTo_3203X);
  1917.   CPU32040 = AddCPU("320C40", SwitchTo_3203X);
  1918.   CPU32044 = AddCPU("320C44", SwitchTo_3203X);
  1919.  
  1920.   AddInitPassProc(InitCode_3203x);
  1921. }
  1922.