Subversion Repositories pentevo

Rev

Blame | Last modification | View Log | Download | RSS feed | ?url?

  1. /* code1802.c */
  2. /****************************************************************************/
  3. /* SPDX-License-Identifier: GPL-2.0-only OR GPL-3.0-only                    */
  4. /*                                                                          */
  5. /* AS                                                                       */
  6. /* Code Generator for Intersil 1802                                         */
  7. /*                                                                          */
  8. /****************************************************************************/
  9.  
  10. #include "stdinc.h"
  11. #include <string.h>
  12.  
  13. #include "bpemu.h"
  14. #include "strutil.h"
  15. #include "asmdef.h"
  16. #include "asmsub.h"
  17. #include "asmpars.h"
  18. #include "asmitree.h"
  19. #include "codepseudo.h"
  20. #include "codevars.h"
  21. #include "intpseudo.h"
  22. #include "headids.h"
  23. #include "errmsg.h"
  24.  
  25. #include "code1802.h"
  26.  
  27. /*-------------------------------------------------------------------------*/
  28. /* Variables */
  29.  
  30. typedef struct
  31. {
  32.   Word Code;
  33.   CPUVar MinCPU;
  34. } tOrder;
  35.  
  36. static tOrder *FixedOrders, *RegOrders, *RegNoZeroOrders,
  37.               *RegImm16Orders, *RegLBranchOrders, *ImmOrders,
  38.               *SBranchOrders, *LBranchOrders, *IOOrders;
  39.  
  40. static CPUVar CPU1802,
  41.               CPU1804, CPU1805, CPU1806,
  42.               CPU1804A, CPU1805A, CPU1806A;
  43.  
  44. /*-------------------------------------------------------------------------*/
  45. /* Subroutines */
  46.  
  47. static Boolean PutCode(const tOrder *pOrder)
  48. {
  49.   if (ChkMinCPU(pOrder->MinCPU))
  50.   {
  51.     if (Hi(pOrder->Code))
  52.       BAsmCode[CodeLen++] = Hi(pOrder->Code);
  53.     BAsmCode[CodeLen++] = Lo(pOrder->Code);
  54.     return True;
  55.   }
  56.   else
  57.     return False;
  58. }
  59.  
  60. /*-------------------------------------------------------------------------*/
  61. /* Coders */
  62.  
  63. static void DecodePORT(Word Opcode)
  64. {
  65.   UNUSED(Opcode);
  66.  
  67.   CodeEquate(SegIO, 1, 0x7);
  68. }
  69.  
  70. static void DecodeFixed(Word Index)
  71. {
  72.   const tOrder *pOrder = FixedOrders + Index;
  73.  
  74.   if (ChkArgCnt(0, 0))
  75.     PutCode(pOrder);
  76. }
  77.  
  78. static void DecodeReg(Word Index)
  79. {
  80.   const tOrder *pOrder = RegOrders + Index;
  81.   Boolean OK;
  82.  
  83.   if (ChkArgCnt(1, 1)
  84.    && PutCode(pOrder))
  85.   {
  86.     BAsmCode[CodeLen - 1] |= EvalStrIntExpression(&ArgStr[1], UInt4, &OK);
  87.     if (!OK)
  88.       CodeLen = 0;
  89.   }
  90. }
  91.  
  92. static void DecodeRegNoZero(Word Index)
  93. {
  94.   const tOrder *pOrder = RegNoZeroOrders + Index;
  95.  
  96.   if (ChkArgCnt(1, 1)
  97.    && PutCode(pOrder))
  98.   {
  99.     Boolean OK;
  100.     Byte Reg;
  101.     tSymbolFlags Flags;
  102.  
  103.     Reg = EvalStrIntExpressionWithFlags(&ArgStr[1], UInt4, &OK, &Flags);
  104.     if (!OK) CodeLen = 0;
  105.     else if (!mFirstPassUnknown(Flags) && (0 == Reg))
  106.     {
  107.       WrStrErrorPos(ErrNum_InvReg, &ArgStr[1]);
  108.       CodeLen = 0;
  109.     }
  110.     else
  111.       BAsmCode[CodeLen - 1] |= Reg;
  112.   }
  113. }
  114.  
  115. static void DecodeRegImm16(Word Index)
  116. {
  117.   const tOrder *pOrder = RegImm16Orders + Index;
  118.   Boolean OK;
  119.  
  120.   if (ChkArgCnt(2, 2)
  121.    && PutCode(pOrder))
  122.   {
  123.     BAsmCode[CodeLen - 1] |= EvalStrIntExpression(&ArgStr[1], UInt4, &OK);
  124.     if (!OK) CodeLen = 0;
  125.     else
  126.     {
  127.       Word Arg = EvalStrIntExpression(&ArgStr[2], Int16, &OK);
  128.  
  129.       if (!OK) CodeLen = 0;
  130.       else
  131.       {
  132.         BAsmCode[CodeLen++] = Hi(Arg);
  133.         BAsmCode[CodeLen++] = Lo(Arg);
  134.       }
  135.     }
  136.   }
  137. }
  138.  
  139. static void DecodeRegLBranch(Word Index)
  140. {
  141.   const tOrder *pOrder = RegLBranchOrders + Index;
  142.  
  143.   if (ChkArgCnt(2, 2)
  144.    && PutCode(pOrder))
  145.   {
  146.     tEvalResult EvalResult;
  147.  
  148.     BAsmCode[CodeLen - 1] |= EvalStrIntExpressionWithResult(&ArgStr[1], UInt4, &EvalResult);
  149.     if (!EvalResult.OK) CodeLen = 0;
  150.     else
  151.     {
  152.       Word Addr = EvalStrIntExpressionWithResult(&ArgStr[2], UInt16, &EvalResult);
  153.       if (!EvalResult.OK)
  154.         CodeLen = 0;
  155.       else
  156.       {
  157.         ChkSpace(SegCode, EvalResult.AddrSpaceMask);
  158.         BAsmCode[CodeLen++] = Hi(Addr);
  159.         BAsmCode[CodeLen++] = Lo(Addr);
  160.       }
  161.     }
  162.   }
  163. }
  164.  
  165. static void DecodeImm(Word Index)
  166. {
  167.   const tOrder *pOrder = ImmOrders + Index;
  168.   Boolean OK;
  169.  
  170.   if (ChkArgCnt(1, 1)
  171.    && PutCode(pOrder))
  172.   {
  173.     BAsmCode[CodeLen++] = EvalStrIntExpression(&ArgStr[1], Int8, &OK);
  174.     if (!OK) CodeLen = 0;
  175.   }
  176. }
  177.  
  178. static void DecodeSBranch(Word Index)
  179. {
  180.   const tOrder *pOrder = SBranchOrders + Index;
  181.  
  182.   if (ChkArgCnt(1, 1)
  183.    && PutCode(pOrder))
  184.   {
  185.     tEvalResult EvalResult;
  186.     Word Addr = EvalStrIntExpressionWithResult(&ArgStr[1], UInt16, &EvalResult);
  187.  
  188.     if (!EvalResult.OK || !ChkSamePage(EProgCounter() + 1, Addr, 8, EvalResult.Flags))
  189.       CodeLen = 0;
  190.     else
  191.     {
  192.       ChkSpace(SegCode, EvalResult.AddrSpaceMask);
  193.       BAsmCode[CodeLen++] = Lo(Addr);
  194.     }
  195.   }
  196. }
  197.  
  198. static void DecodeLBranch(Word Index)
  199. {
  200.   const tOrder *pOrder = LBranchOrders + Index;
  201.  
  202.   if (ChkArgCnt(1, 1)
  203.    && PutCode(pOrder))
  204.   {
  205.     tEvalResult EvalResult;
  206.     Word Addr = EvalStrIntExpressionWithResult(&ArgStr[1], UInt16, &EvalResult);
  207.  
  208.     if (!EvalResult.OK) CodeLen = 0;
  209.     else
  210.     {
  211.       ChkSpace(SegCode, EvalResult.AddrSpaceMask);
  212.       BAsmCode[CodeLen++] = Hi(Addr);
  213.       BAsmCode[CodeLen++] = Lo(Addr);
  214.     }
  215.   }
  216. }
  217.  
  218. static void DecodeJump(Word Index)
  219. {
  220.   const tOrder *pOrder = LBranchOrders + Index;
  221.  
  222.   if (ChkArgCnt(1, 1) && ChkMinCPU(pOrder->MinCPU))
  223.   {
  224.     tEvalResult EvalResult;
  225.     Word Addr = EvalStrIntExpressionWithResult(&ArgStr[1], UInt16, &EvalResult);
  226.  
  227.     if (EvalResult.OK)
  228.     {
  229.       ChkSpace(SegCode, EvalResult.AddrSpaceMask);
  230.       if (Hi(EProgCounter() + 1) == Hi(Addr))
  231.         BAsmCode[CodeLen++] = pOrder->Code ^ 0xf0;
  232.       else
  233.       {
  234.         BAsmCode[CodeLen++] = pOrder->Code;
  235.         BAsmCode[CodeLen++] = Hi(Addr);
  236.       }
  237.       BAsmCode[CodeLen++] = Lo(Addr);
  238.     }
  239.   }
  240. }
  241.  
  242. static void DecodeIO(Word Index)
  243. {
  244.   const tOrder *pOrder = IOOrders + Index;
  245.   Boolean OK;
  246.  
  247.   if (ChkArgCnt(1, 1))
  248.   {
  249.     tSymbolFlags Flags;
  250.  
  251.     BAsmCode[0] = EvalStrIntExpressionWithFlags(&ArgStr[1], UInt3, &OK, &Flags);
  252.     if (OK)
  253.     {
  254.       if (mFirstPassUnknown(Flags)) BAsmCode[0] = 1;
  255.       if (BAsmCode[0] == 0) WrError(ErrNum_UnderRange);
  256.       else
  257.       {
  258.         BAsmCode[0] |= pOrder->Code;
  259.         CodeLen = 1;
  260.       }
  261.     }
  262.   }
  263. }
  264.  
  265. /*-------------------------------------------------------------------------*/
  266. /* Instruction Hash Table Handling */
  267.  
  268. static void AddFixed(const char *pName, Word Code, CPUVar MinCPU)
  269. {
  270.   order_array_rsv_end(FixedOrders, tOrder);
  271.   FixedOrders[InstrZ].Code = Code;
  272.   FixedOrders[InstrZ].MinCPU = MinCPU;
  273.   AddInstTable(InstTable, pName, InstrZ++, DecodeFixed);
  274. }
  275.  
  276. static void AddReg(const char *pName, Word Code, CPUVar MinCPU)
  277. {
  278.   order_array_rsv_end(RegOrders, tOrder);
  279.   RegOrders[InstrZ].Code = Code;
  280.   RegOrders[InstrZ].MinCPU = MinCPU;
  281.   AddInstTable(InstTable, pName, InstrZ++, DecodeReg);
  282. }
  283.  
  284. static void AddRegNoZero(const char *pName, Word Code, CPUVar MinCPU)
  285. {
  286.   order_array_rsv_end(RegNoZeroOrders, tOrder);
  287.   RegNoZeroOrders[InstrZ].Code = Code;
  288.   RegNoZeroOrders[InstrZ].MinCPU = MinCPU;
  289.   AddInstTable(InstTable, pName, InstrZ++, DecodeRegNoZero);
  290. }
  291.  
  292. static void AddRegImm16(const char *pName, Word Code, CPUVar MinCPU)
  293. {
  294.   order_array_rsv_end(RegImm16Orders, tOrder);
  295.   RegImm16Orders[InstrZ].Code = Code;
  296.   RegImm16Orders[InstrZ].MinCPU = MinCPU;
  297.   AddInstTable(InstTable, pName, InstrZ++, DecodeRegImm16);
  298. }
  299.  
  300. static void AddImm(const char *pName, Word Code, CPUVar MinCPU)
  301. {
  302.   order_array_rsv_end(ImmOrders, tOrder);
  303.   ImmOrders[InstrZ].Code = Code;
  304.   ImmOrders[InstrZ].MinCPU = MinCPU;
  305.   AddInstTable(InstTable, pName, InstrZ++, DecodeImm);
  306. }
  307.  
  308. static void AddRegLBranch(const char *pName, Word Code, CPUVar MinCPU)
  309. {
  310.   order_array_rsv_end(RegLBranchOrders, tOrder);
  311.   RegLBranchOrders[InstrZ].Code = Code;
  312.   RegLBranchOrders[InstrZ].MinCPU = MinCPU;
  313.   AddInstTable(InstTable, pName, InstrZ++, DecodeRegLBranch);
  314. }
  315.  
  316. static void AddLBranch(const char *pName, Word Code, CPUVar MinCPU)
  317. {
  318.   order_array_rsv_end(LBranchOrders, tOrder);
  319.   LBranchOrders[InstrZ].Code = Code;
  320.   LBranchOrders[InstrZ].MinCPU = MinCPU;
  321.   AddInstTable(InstTable, pName, InstrZ, DecodeLBranch);
  322.   if (!strcmp(pName, "LBR"))
  323.     AddInstTable(InstTable, "JMP", InstrZ, DecodeJump);
  324.   else if (!strcmp(pName, "NLBR"));
  325.   else
  326.   {
  327.     char JName[10];
  328.  
  329.     as_snprintf(JName, sizeof(JName), "J%s", pName + 2);
  330.     AddInstTable(InstTable, JName, InstrZ, DecodeJump);
  331.   }
  332.   InstrZ++;
  333. }
  334.  
  335. static void AddSBranch(const char *pName, Word Code, CPUVar MinCPU)
  336. {
  337.   order_array_rsv_end(SBranchOrders, tOrder);
  338.   SBranchOrders[InstrZ].Code = Code;
  339.   SBranchOrders[InstrZ].MinCPU = MinCPU;
  340.   AddInstTable(InstTable, pName, InstrZ++, DecodeSBranch);
  341. }
  342.  
  343. static void AddIO(const char *pName, Word Code, CPUVar MinCPU)
  344. {
  345.   order_array_rsv_end(IOOrders, tOrder);
  346.   IOOrders[InstrZ].Code = Code;
  347.   IOOrders[InstrZ].MinCPU = MinCPU;
  348.   AddInstTable(InstTable, pName, InstrZ++, DecodeIO);
  349. }
  350.  
  351. static void InitFields(void)
  352. {
  353.   SetDynamicInstTable((InstTable = CreateInstTable(203)));
  354.  
  355.   AddInstTable(InstTable, "PORT", 0, DecodePORT);
  356.  
  357.   InstrZ = 0;
  358.   AddFixed("LDX"  , 0x00f0, CPU1802);
  359.   AddFixed("LDXA" , 0x0072, CPU1802);
  360.   AddFixed("STXD" , 0x0073, CPU1802);
  361.   AddFixed("IRX"  , 0x0060, CPU1802);
  362.   AddFixed("OR"   , 0x00f1, CPU1802);
  363.   AddFixed("XOR"  , 0x00f3, CPU1802);
  364.   AddFixed("AND"  , 0x00f2, CPU1802);
  365.   AddFixed("SHR"  , 0x00f6, CPU1802);
  366.   AddFixed("SHRC" , 0x0076, CPU1802);
  367.   AddFixed("RSHR" , 0x0076, CPU1802);
  368.   AddFixed("SHL"  , 0x00fe, CPU1802);
  369.   AddFixed("SHLC" , 0x007e, CPU1802);
  370.   AddFixed("RSHL" , 0x007e, CPU1802);
  371.   AddFixed("ADD"  , 0x00f4, CPU1802);
  372.   AddFixed("ADC"  , 0x0074, CPU1802);
  373.   AddFixed("SD"   , 0x00f5, CPU1802);
  374.   AddFixed("SDB"  , 0x0075, CPU1802);
  375.   AddFixed("SM"   , 0x00f7, CPU1802);
  376.   AddFixed("SMB"  , 0x0077, CPU1802);
  377.   AddFixed("DADD" , 0x68f4, CPU1804A);
  378.   AddFixed("DADC" , 0x6874, CPU1804A);
  379.   AddFixed("DSM"  , 0x68f7, CPU1804A);
  380.   AddFixed("DSMB" , 0x6877, CPU1804A);
  381.   AddFixed("SKP"  , 0x0038, CPU1802);
  382.   AddFixed("LSKP" , 0x00c8, CPU1802);
  383.   AddFixed("LSZ"  , 0x00ce, CPU1802);
  384.   AddFixed("LSNZ" , 0x00c6, CPU1802);
  385.   AddFixed("LSDF" , 0x00cf, CPU1802);
  386.   AddFixed("LSNF" , 0x00c7, CPU1802);
  387.   AddFixed("LSQ"  , 0x00cd, CPU1802);
  388.   AddFixed("LSNQ" , 0x00c5, CPU1802);
  389.   AddFixed("LSIE" , 0x00cc, CPU1802);
  390.   AddFixed("IDL"  , 0x0000, CPU1802);
  391.   AddFixed("NOP"  , 0x00c4, CPU1802);
  392.   AddFixed("SEQ"  , 0x007b, CPU1802);
  393.   AddFixed("REQ"  , 0x007a, CPU1802);
  394.   AddFixed("SAV"  , 0x0078, CPU1802);
  395.   AddFixed("MARK" , 0x0079, CPU1802);
  396.   AddFixed("RET"  , 0x0070, CPU1802);
  397.   AddFixed("DIS"  , 0x0071, CPU1802);
  398.   AddFixed("LDC"  , 0x6806, CPU1804);
  399.   AddFixed("GEC"  , 0x6808, CPU1804);
  400.   AddFixed("STPC" , 0x6800, CPU1804);
  401.   AddFixed("DTC"  , 0x6801, CPU1804);
  402.   AddFixed("STM"  , 0x6807, CPU1804);
  403.   AddFixed("SCM1" , 0x6805, CPU1804);
  404.   AddFixed("SCM2" , 0x6803, CPU1804);
  405.   AddFixed("SPM1" , 0x6804, CPU1804);
  406.   AddFixed("SPM2" , 0x6802, CPU1804);
  407.   AddFixed("ETQ"  , 0x6809, CPU1804);
  408.   AddFixed("XIE"  , 0x680a, CPU1804);
  409.   AddFixed("XID"  , 0x680b, CPU1804);
  410.   AddFixed("CIE"  , 0x680c, CPU1804);
  411.   AddFixed("CID"  , 0x680d, CPU1804);
  412.   AddFixed("DSAV" , 0x6876, CPU1804A);
  413.  
  414.   InstrZ = 0;
  415.   AddReg("LDA"  , 0x0040, CPU1802);
  416.   AddReg("STR"  , 0x0050, CPU1802);
  417.   AddReg("RLXA" , 0x6860, CPU1804);
  418.   AddReg("RSXD" , 0x68a0, CPU1804);
  419.   AddReg("INC"  , 0x0010, CPU1802);
  420.   AddReg("DEC"  , 0x0020, CPU1802);
  421.   AddReg("GLO"  , 0x0080, CPU1802);
  422.   AddReg("PLO"  , 0x00a0, CPU1802);
  423.   AddReg("GHI"  , 0x0090, CPU1802);
  424.   AddReg("PHI"  , 0x00b0, CPU1802);
  425.   AddReg("RNX"  , 0x68b0, CPU1804);
  426.   AddReg("SEP"  , 0x00d0, CPU1802);
  427.   AddReg("SEX"  , 0x00e0, CPU1802);
  428.   AddReg("SRET" , 0x6890, CPU1804);
  429.  
  430.   InstrZ = 0;
  431.   AddRegNoZero("LDN"  , 0x0000, CPU1802);
  432.  
  433.   InstrZ = 0;
  434.   AddRegImm16("RLDI" , 0x68c0, CPU1804);
  435.  
  436.   InstrZ = 0;
  437.   AddImm("LDI"  , 0x00f8, CPU1802);
  438.   AddImm("ORI"  , 0x00f9, CPU1802);
  439.   AddImm("XRI"  , 0x00fb, CPU1802);
  440.   AddImm("ANI"  , 0x00fa, CPU1802);
  441.   AddImm("ADI"  , 0x00fc, CPU1802);
  442.   AddImm("ADCI" , 0x007c, CPU1802);
  443.   AddImm("SDI"  , 0x00fd, CPU1802);
  444.   AddImm("SDBI" , 0x007d, CPU1802);
  445.   AddImm("SMI"  , 0x00ff, CPU1802);
  446.   AddImm("SMBI" , 0x007f, CPU1802);
  447.   AddImm("DADI" , 0x68fc, CPU1804A);
  448.   AddImm("DACI" , 0x687c, CPU1804A);
  449.   AddImm("DSMI" , 0x68ff, CPU1804A);
  450.   AddImm("DSBI" , 0x687f, CPU1804A);
  451.  
  452.   InstrZ = 0;
  453.   AddRegLBranch("DBNZ" , 0x6820, CPU1804A);
  454.   AddRegLBranch("SCAL" , 0x6880, CPU1804);
  455.  
  456.   InstrZ = 0;
  457.   AddLBranch("LBR"  , 0x00c0, CPU1802);
  458.   AddLBranch("NLBR" , 0x00c8, CPU1802);
  459.   AddLBranch("LBZ"  , 0x00c2, CPU1802);
  460.   AddLBranch("LBNZ" , 0x00ca, CPU1802);
  461.   AddLBranch("LBDF" , 0x00c3, CPU1802);
  462.   AddLBranch("LBPZ" , 0x00c3, CPU1802);
  463.   AddLBranch("LBGE" , 0x00c3, CPU1802);
  464.   AddLBranch("LBNF" , 0x00cb, CPU1802);
  465.   AddLBranch("LBM"  , 0x00cb, CPU1802);
  466.   AddLBranch("LBL"  , 0x00cb, CPU1802);
  467.   AddLBranch("LBQ"  , 0x00c1, CPU1802);
  468.   AddLBranch("LBNQ" , 0x00c9, CPU1802);
  469.  
  470.   InstrZ = 0;
  471.   AddSBranch("BR"   , 0x0030, CPU1802);
  472.   AddSBranch("NBR"  , 0x0038, CPU1802);
  473.   AddSBranch("BZ"   , 0x0032, CPU1802);
  474.   AddSBranch("BNZ"  , 0x003a, CPU1802);
  475.   AddSBranch("BDF"  , 0x0033, CPU1802);
  476.   AddSBranch("BPZ"  , 0x0033, CPU1802);
  477.   AddSBranch("BGE"  , 0x0033, CPU1802);
  478.   AddSBranch("BNF"  , 0x003b, CPU1802);
  479.   AddSBranch("BM"   , 0x003b, CPU1802);
  480.   AddSBranch("BL"   , 0x003b, CPU1802);
  481.   AddSBranch("BQ"   , 0x0031, CPU1802);
  482.   AddSBranch("BNQ"  , 0x0039, CPU1802);
  483.   AddSBranch("B1"   , 0x0034, CPU1802);
  484.   AddSBranch("BN1"  , 0x003c, CPU1802);
  485.   AddSBranch("B2"   , 0x0035, CPU1802);
  486.   AddSBranch("BN2"  , 0x003d, CPU1802);
  487.   AddSBranch("B3"   , 0x0036, CPU1802);
  488.   AddSBranch("BN3"  , 0x003e, CPU1802);
  489.   AddSBranch("B4"   , 0x0037, CPU1802);
  490.   AddSBranch("BN4"  , 0x003f, CPU1802);
  491.   AddSBranch("BCI"  , 0x683e, CPU1804);
  492.   AddSBranch("BXI"  , 0x683f, CPU1804);
  493.  
  494.   InstrZ = 0;
  495.   AddIO("OUT"  , 0x0060, CPU1802);
  496.   AddIO("INP"  , 0x0068, CPU1802);
  497. }
  498.  
  499. static void DeinitFields(void)
  500. {
  501.   order_array_free(FixedOrders);
  502.   order_array_free(RegOrders);
  503.   order_array_free(RegNoZeroOrders);
  504.   order_array_free(RegImm16Orders);
  505.   order_array_free(RegLBranchOrders);
  506.   order_array_free(ImmOrders);
  507.   order_array_free(SBranchOrders);
  508.   order_array_free(LBranchOrders);
  509.   order_array_free(IOOrders);
  510.  
  511.   DestroyInstTable(InstTable);
  512. }
  513.  
  514. /*-------------------------------------------------------------------------*/
  515. /* Interface to Upper Level */
  516.  
  517. static void MakeCode_1802(void)
  518. {
  519.   CodeLen = 0; DontPrint = False;
  520.  
  521.   /* to be ignored */
  522.  
  523.   if (*OpPart.str.p_str == '\0') return;
  524.  
  525.   /* Pseudo Instructions */
  526.  
  527.   if (DecodeIntelPseudo(True)) return;
  528.  
  529.   /* search */
  530.  
  531.   if (!LookupInstTable(InstTable, OpPart.str.p_str))
  532.     WrStrErrorPos(ErrNum_UnknownInstruction, &OpPart);
  533. }
  534.  
  535. static Boolean IsDef_1802(void)
  536. {
  537.   return Memo("PORT");
  538. }
  539.  
  540. static void SwitchFrom_1802(void)
  541. {
  542.   DeinitFields();
  543. }
  544.  
  545. static void SwitchTo_1802(void)
  546. {
  547.   const TFamilyDescr *FoundDescr;
  548.  
  549.   FoundDescr = FindFamilyByName("1802");
  550.  
  551.   TurnWords = FALSE;
  552.   SetIntConstMode(eIntConstModeIntel);
  553.  
  554.   PCSymbol = "$";
  555.   HeaderID = FoundDescr->Id;
  556.   NOPCode = 0xc4;
  557.   DivideChars = ",";
  558.   HasAttrs = False;
  559.  
  560.   ValidSegs = (1 << SegCode) | (1 << SegIO);
  561.   Grans[SegCode ] = 1; ListGrans[SegCode ] = 1; SegInits[SegCode ] = 0;
  562.   SegLimits[SegCode ] = 0xffff;
  563.   Grans[SegIO   ] = 1; ListGrans[SegIO   ] = 1; SegInits[SegIO   ] = 1;
  564.   SegLimits[SegIO   ] = 0x7;
  565.  
  566.   MakeCode = MakeCode_1802;
  567.   IsDef = IsDef_1802;
  568.  
  569.   InitFields();
  570.   SwitchFrom = SwitchFrom_1802;
  571. }
  572.  
  573. /*-------------------------------------------------------------------------*/
  574. /* Module Initialization */
  575.  
  576. void code1802_init(void)
  577. {
  578.   CPU1802  = AddCPU("1802", SwitchTo_1802);
  579.   CPU1804  = AddCPU("1804", SwitchTo_1802);
  580.   CPU1805  = AddCPU("1805", SwitchTo_1802);
  581.   CPU1806  = AddCPU("1806", SwitchTo_1802);
  582.   CPU1804A = AddCPU("1804A", SwitchTo_1802);
  583.   CPU1805A = AddCPU("1805A", SwitchTo_1802);
  584.   CPU1806A = AddCPU("1806A", SwitchTo_1802);
  585. }
  586.