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  1. // part of NeoGS project (c) 2007-2008 NedoPC
  2. //
  3.  
  4. // SPI mode 0 8-bit master module
  5. //
  6. // short diagram for speed=0 (Fclk/Fspi=2, no rdy shown)
  7. //
  8. // clock:   ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^ (positive edges)
  9. // counter: |00|00|10|11|12|13|14|15|16|17|18|19|1A|1B|1C|1D|1E|1F|00|00|00 // internal!
  10. // sck:   ___________/``\__/``\__/``\__/``\__/``\__/``\__/``\__/``\_______
  11. // sdo:   --------< do7 X do6 X do5 X do4 X do3 X do2 X do1 X do0 >-------
  12. // sdi:   --------< di7 X di6 X di5 X di4 X di3 X di2 X di1 X di0 >-------
  13. // bsync: ________/`````\_________________________________________________
  14. // start: _____/``\_______________________________________________________
  15. // din:   -----<IN>-------------------------------------------------------
  16. // dout:   old old old old old old old old old old old old old | new new new
  17. //
  18. // data on sdo must be latched by slave on rising sck edge. data on sdo changes on falling edge of sck
  19. //
  20. // data from sdi is latched by master on positive edge of sck, while slave changes it on falling edge.
  21. //  WARNING: slave must emit valid di7 bit BEFORE first pulse on sck!
  22. //
  23. // bsync is 1 while do7 is outting, otherwise it is 0
  24. //
  25. // start is synchronous pulse, which starts all transfer and also latches din data on the same clock edge
  26. //  as it is registered high. start can be given anytime (only when speed=0),
  27. //  so it is functioning then as synchronous reset. when speed!=0, there is global enable for majority of
  28. //  flipflops in the module, so start can't be accepted at any time
  29. //
  30. // dout updates with freshly received data at the clock edge in which sck goes high for the last time, thus
  31. //  latching last bit on sdi.
  32. //
  33. // sdo emits last bit shifted out after the transfer end
  34. //
  35. // when speed=0, data transfer rate could be as fast as one byte every 16 clock pulses. To achieve that,
  36. //   start must be pulsed high simultaneously with the last high pulse of sck
  37. //
  38. // speed[1:0] determines Fclk/Fspi
  39. //
  40. //  speed | Fclk/Fspi
  41. //  ------+----------
  42. //  2'b00 | 2
  43. //  2'b01 | 4
  44. //  2'b10 | 8
  45. //  2'b11 | 16
  46. //
  47. // for speed=0 you can start new transfer as fast as every 16 clocks
  48. // for speed=1 - every 34 clocks.
  49. // alternatively, you can check rdy output: it goes to 0 after start pulse and when it goes back to 1, you can
  50. // issue another start at the next clock cycle. See spi2_modelled.png and .zip (modelsim project)
  51. //
  52. // warning: if using rdy-driven transfers and speed=0, new transfer will be started every 18 clocks.
  53. //  it is recommended to use rdy-driven transfers when speed!=0
  54. //
  55. // warning: this module does not contain asynchronous reset. Provided clock is stable, start=0
  56. //  and speed=0, module returns to initial ready state after maximum of 18+8=26 clocks. To reset module
  57. //  to the known state from any operational state, set speed=0 and start=1 for 8 clocks
  58. //  (that starts Fclk/Fspi=2 speed transfer for sure), then remain start=0, speed=0 for at least 18 clocks.
  59.  
  60. module spi2(
  61.  
  62.         clock, // system clock
  63.  
  64.         sck,   // SPI bus pins...
  65.         sdo,   //
  66.         sdi,   //
  67.         bsync, // ...and bsync for vs1001
  68.  
  69.         start, // positive strobe that starts transfer
  70.         rdy,   // ready (idle) - when module can accept data
  71.  
  72.         speed, // =2'b00 - sck full speed (1/2 of clock), =2'b01 - half (1/4 of clock), =2'b10 - one fourth (1/8 of clock), =2'b11 - one eighth (1/16 of clock)
  73.  
  74.         din,  // input
  75.         dout  // and output 8bit busses
  76. );
  77.  
  78.         input clock;
  79.  
  80.  
  81.         output sck;
  82.         wire   sck;
  83.  
  84.         output sdo;
  85.  
  86.         input sdi;
  87.  
  88.         output reg bsync;
  89.  
  90.         input start;
  91.  
  92.         output rdy;
  93.  
  94.  
  95.         input [1:0] speed;
  96.  
  97.         input [7:0] din;
  98.  
  99.         output reg [7:0] dout;
  100.  
  101.  
  102.  
  103.         // internal regs
  104.  
  105.         reg [4:0] counter; // governs transmission
  106.  
  107.         wire enable_n; // =1 when transmission in progress
  108.  
  109.         reg [6:0] shiftin; // shifting in data from sdi before emitting it on dout
  110.  
  111.         reg [7:0] shiftout; // shifting out data to the sdo
  112.  
  113.         wire ena_shout_load; // enable load of shiftout register
  114.  
  115.         wire g_ena;
  116.         reg [2:0] wcnt;
  117.  
  118.  
  119.         initial // for simulation only!
  120.         begin
  121.                 counter = 5'b10000;
  122.                 shiftout = 8'd0;
  123.                 shiftout = 7'd0;
  124.                 bsync = 1'd0;
  125.                 dout = 1'b0;
  126.         end
  127.  
  128.  
  129.         // rdy is enable_n
  130.         assign rdy = enable_n;
  131.  
  132.         // sck is low bit of counter
  133.         assign sck = counter[0];
  134.  
  135.         // enable_n is high bit of counter
  136.         assign enable_n = counter[4];
  137.  
  138.         // sdo is high bit of shiftout
  139.         assign sdo = shiftout[7];
  140.  
  141.         assign ena_shout_load = (start | sck) & g_ena;
  142.  
  143.  
  144.  
  145.  
  146.         always @(posedge clock)
  147.         begin
  148.                 if( g_ena )
  149.                 begin
  150.                         if( start )
  151.                         begin
  152.                                 counter <= 5'b00000; // enable_n = 0; sck = 0;
  153.                                 bsync <= 1'b1; // begin bsync pulse
  154.                         end
  155.                         else
  156.                         begin
  157.                                 if( !sck ) // on the rising edge of sck
  158.                                 begin
  159.                           shiftin[6:0] <= { shiftin[5:0], sdi };
  160.  
  161.                                         if( (&counter[3:1]) && (!enable_n) )
  162.                                                 dout <= { shiftin[6:0], sdi }; // update dout at the last sck rising edge
  163.                                 end
  164.                                 else // on the falling edge of sck
  165.                                 begin
  166.                                         bsync <= 1'b0;
  167.                                 end
  168.  
  169.                                 if( !enable_n )
  170.                                         counter <= counter + 5'd1;
  171.                         end
  172.                 end
  173.         end
  174.  
  175.  
  176.         // shiftout treatment is done so just to save LCELLs in acex1k
  177.         always @(posedge clock)
  178.         begin
  179.                 if( ena_shout_load )
  180.                 begin
  181.                         if( start )
  182.                                 shiftout <= din;
  183.                         else // sck
  184.                                 shiftout[7:0] <= { shiftout[6:0], shiftout[0] }; // last bit remains after end of exchange
  185.                 end
  186.         end
  187.  
  188.  
  189.         // slow speeds - governed by g_ena
  190.         always @(posedge clock)
  191.         begin
  192.                 if( speed!=2'b00 )
  193.                 begin
  194.                         if( start )
  195.                                 wcnt <= 3'b001;
  196.                         else if( enable_n )
  197.                                 wcnt <= 3'b000;
  198.                         else
  199.                                 wcnt <= wcnt + 3'd1;
  200.                 end
  201.                 else
  202.                         wcnt <= 3'b000;
  203.         end
  204.  
  205.         assign g_ena = (speed==2'b00) ? 1'b1 :
  206.                        (speed==2'b01) ? (wcnt[0]  == 1'b0   ) :
  207.                        (speed==2'b10) ? (wcnt[1:0]== 2'b00  ) :
  208.                                         (wcnt[2:0]== 3'b000 ) ;
  209.  
  210.  
  211. endmodule
  212.  
  213.