WebSVN – pentevo – /scorpevo/flasher/fpga/db/main.tan.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 18:42:11 2011 " "Info: Processing started: Mon Nov 14 18:42:11 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off fpga -c main " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fpga -c main" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]~mem_cell_wa1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]~mem_cell_wa1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]~mem_cell_din1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[1\]~mem_cell_wa1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[1\]~mem_cell_wa1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[1\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[1\]~mem_cell_din1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[2\]~mem_cell_wa1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[2\]~mem_cell_wa1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[2\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[2\]~mem_cell_din1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[3\]~mem_cell_wa1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[3\]~mem_cell_wa1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[3\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[3\]~mem_cell_din1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[4\]~mem_cell_wa1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[4\]~mem_cell_wa1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[4\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[4\]~mem_cell_din1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[5\]~mem_cell_wa1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[5\]~mem_cell_wa1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[5\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[5\]~mem_cell_din1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\]~mem_cell_wa1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\]~mem_cell_wa1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\]~mem_cell_din1\" is a latch" {  } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 -1}
{ "Warning" "WTAN_CLOCK_SETTING_NOT_USED" "Z80 clock " "Warning: Clock Setting \"Z80 clock\" is unassigned" {  } {  } 0 0 "Clock Setting \"%1!s!\" is unassigned" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_RESULT" "fclk register lpm_counter:hcharcount_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[5\] register vred\[1\]~reg0 -1.286 ns " "Info: Slack time is -1.286 ns for clock \"fclk\" between source register \"lpm_counter:hcharcount_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[5\]\" and destination register \"vred\[1\]~reg0\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "27.03 MHz 37.0 ns " "Info: Fmax is 27.03 MHz (period= 37.0 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "33.214 ns + Largest register register " "Info: + Largest register to register requirement is 33.214 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "35.714 ns + " "Info: + Setup relationship between source and destination is 35.714 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 35.714 ns " "Info: + Latch edge is 35.714 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination fclk 35.714 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"fclk\" is 35.714 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source fclk 35.714 ns 0.000 ns  50 " "Info: Clock period of Source clock \"fclk\" is 35.714 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.500 ns + Largest " "Info: + Largest clock skew is -0.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fclk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"fclk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns fclk 1 CLK PIN_183 106 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_183; Fanout = 106; CLK Node = 'fclk'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { fclk } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.400 ns) 3.000 ns vred\[1\]~reg0 2 REG IOC_132 1 " "Info: 2: + IC(0.400 ns) + CELL(0.400 ns) = 3.000 ns; Loc. = IOC_132; Fanout = 1; REG Node = 'vred\[1\]~reg0'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { fclk vred[1]~reg0 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 182 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 86.67 % ) " "Info: Total cell delay = 2.600 ns ( 86.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 13.33 % ) " "Info: Total interconnect delay = 0.400 ns ( 13.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { fclk vred[1]~reg0 } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { fclk {} fclk~out {} vred[1]~reg0 {} } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.200ns 0.400ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fclk source 3.500 ns - Longest register " "Info: - Longest clock path from clock \"fclk\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns fclk 1 CLK PIN_183 106 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_183; Fanout = 106; CLK Node = 'fclk'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { fclk } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns lpm_counter:hcharcount_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[5\] 2 REG LC6_I16 3 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC6_I16; Fanout = 3; REG Node = 'lpm_counter:hcharcount_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[5\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { fclk lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { fclk lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { fclk vred[1]~reg0 } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { fclk {} fclk~out {} vred[1]~reg0 {} } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.200ns 0.400ns } "" } } { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { fclk lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns - " "Info: - Micro clock to output delay of source is 0.700 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns - " "Info: - Micro setup delay of destination is 1.300 ns" {  } { { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 182 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { fclk vred[1]~reg0 } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { fclk {} fclk~out {} vred[1]~reg0 {} } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.200ns 0.400ns } "" } } { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { fclk lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "34.500 ns - Longest register register " "Info: - Longest register to register delay is 34.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:hcharcount_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[5\] 1 REG LC6_I16 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_I16; Fanout = 3; REG Node = 'lpm_counter:hcharcount_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[5\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.600 ns) 1.900 ns lpm_add_sub:Add6\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~COUT 2 COMB LC3_I18 2 " "Info: 2: + IC(1.300 ns) + CELL(0.600 ns) = 1.900 ns; Loc. = LC3_I18; Fanout = 2; COMB Node = 'lpm_add_sub:Add6\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~COUT'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~COUT } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.000 ns lpm_add_sub:Add6\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~COUT 3 COMB LC4_I18 2 " "Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 2.000 ns; Loc. = LC4_I18; Fanout = 2; COMB Node = 'lpm_add_sub:Add6\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~COUT'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.100 ns" { lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~COUT lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~COUT } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.100 ns lpm_add_sub:Add6\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\]~COUT 4 COMB LC5_I18 2 " "Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 2.100 ns; Loc. = LC5_I18; Fanout = 2; COMB Node = 'lpm_add_sub:Add6\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\]~COUT'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.100 ns" { lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~COUT lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~COUT } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.200 ns lpm_add_sub:Add6\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[5\]~COUT 5 COMB LC6_I18 1 " "Info: 5: + IC(0.000 ns) + CELL(0.100 ns) = 2.200 ns; Loc. = LC6_I18; Fanout = 1; COMB Node = 'lpm_add_sub:Add6\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[5\]~COUT'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.100 ns" { lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~COUT lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~COUT } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.500 ns lpm_add_sub:Add6\|addcore:adder\|unreg_res_node\[6\] 6 COMB LC7_I18 7 " "Info: 6: + IC(0.000 ns) + CELL(1.300 ns) = 3.500 ns; Loc. = LC7_I18; Fanout = 7; COMB Node = 'lpm_add_sub:Add6\|addcore:adder\|unreg_res_node\[6\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~COUT lpm_add_sub:Add6|addcore:adder|unreg_res_node[6] } "NODE_NAME" } } { "addcore.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/addcore.tdf" 98 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(6.300 ns) 12.000 ns lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\]~mem_cell_ra0 7 MEM EC10_H 1 " "Info: 7: + IC(2.200 ns) + CELL(6.300 ns) = 12.000 ns; Loc. = EC10_H; Fanout = 1; MEM Node = 'lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\]~mem_cell_ra0'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "8.500 ns" { lpm_add_sub:Add6|addcore:adder|unreg_res_node[6] lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6]~mem_cell_ra0 } "NODE_NAME" } } { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 12.000 ns lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\] 8 MEM EC10_H 8 " "Info: 8: + IC(0.000 ns) + CELL(0.000 ns) = 12.000 ns; Loc. = EC10_H; Fanout = 8; MEM Node = 'lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6]~mem_cell_ra0 lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6] } "NODE_NAME" } } { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(6.300 ns) 21.200 ns lpm_rom0:chargen\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~mem_cell_ra0 9 MEM EC9_G 1 " "Info: 9: + IC(2.900 ns) + CELL(6.300 ns) = 21.200 ns; Loc. = EC9_G; Fanout = 1; MEM Node = 'lpm_rom0:chargen\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~mem_cell_ra0'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.200 ns" { lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6] lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 21.200 ns lpm_rom0:chargen\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\] 10 MEM EC9_G 1 " "Info: 10: + IC(0.000 ns) + CELL(0.000 ns) = 21.200 ns; Loc. = EC9_G; Fanout = 1; MEM Node = 'lpm_rom0:chargen\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0] } "NODE_NAME" } } { "altrom.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.400 ns) 23.900 ns Mux0~4 11 COMB LC2_G2 1 " "Info: 11: + IC(1.300 ns) + CELL(1.400 ns) = 23.900 ns; Loc. = LC2_G2; Fanout = 1; COMB Node = 'Mux0~4'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0] Mux0~4 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 283 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.500 ns) 25.600 ns Mux0~5 12 COMB LC3_G2 1 " "Info: 12: + IC(0.200 ns) + CELL(1.500 ns) = 25.600 ns; Loc. = LC3_G2; Fanout = 1; COMB Node = 'Mux0~5'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { Mux0~4 Mux0~5 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 283 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.900 ns) 26.700 ns Mux0~15 13 COMB LC7_G2 1 " "Info: 13: + IC(0.200 ns) + CELL(0.900 ns) = 26.700 ns; Loc. = LC7_G2; Fanout = 1; COMB Node = 'Mux0~15'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { Mux0~5 Mux0~15 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 283 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 28.200 ns Mux0~10 14 COMB LC8_G2 5 " "Info: 14: + IC(0.000 ns) + CELL(1.500 ns) = 28.200 ns; Loc. = LC8_G2; Fanout = 5; COMB Node = 'Mux0~10'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { Mux0~15 Mux0~10 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 283 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.400 ns) 30.700 ns vred\[1\]~6 15 COMB LC6_G1 1 " "Info: 15: + IC(1.100 ns) + CELL(1.400 ns) = 30.700 ns; Loc. = LC6_G1; Fanout = 1; COMB Node = 'vred\[1\]~6'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { Mux0~10 vred[1]~6 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 182 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.000 ns) 34.500 ns vred\[1\]~reg0 16 REG IOC_132 1 " "Info: 16: + IC(1.800 ns) + CELL(2.000 ns) = 34.500 ns; Loc. = IOC_132; Fanout = 1; REG Node = 'vred\[1\]~reg0'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { vred[1]~6 vred[1]~reg0 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 182 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.500 ns ( 68.12 % ) " "Info: Total cell delay = 23.500 ns ( 68.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "11.000 ns ( 31.88 % ) " "Info: Total interconnect delay = 11.000 ns ( 31.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "34.500 ns" { lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~COUT lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~COUT lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~COUT lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~COUT lpm_add_sub:Add6|addcore:adder|unreg_res_node[6] lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6]~mem_cell_ra0 lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6] lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0] Mux0~4 Mux0~5 Mux0~15 Mux0~10 vred[1]~6 vred[1]~reg0 } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "34.500 ns" { lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] {} lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~COUT {} lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~COUT {} lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~COUT {} lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~COUT {} lpm_add_sub:Add6|addcore:adder|unreg_res_node[6] {} lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6]~mem_cell_ra0 {} lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6] {} lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 {} lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0] {} Mux0~4 {} Mux0~5 {} Mux0~15 {} Mux0~10 {} vred[1]~6 {} vred[1]~reg0 {} } { 0.000ns 1.300ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns 0.000ns 2.900ns 0.000ns 1.300ns 0.200ns 0.200ns 0.000ns 1.100ns 1.800ns } { 0.000ns 0.600ns 0.100ns 0.100ns 0.100ns 1.300ns 6.300ns 0.000ns 6.300ns 0.000ns 1.400ns 1.500ns 0.900ns 1.500ns 1.400ns 2.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { fclk vred[1]~reg0 } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { fclk {} fclk~out {} vred[1]~reg0 {} } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.200ns 0.400ns } "" } } { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { fclk lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "34.500 ns" { lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~COUT lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~COUT lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~COUT lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~COUT lpm_add_sub:Add6|addcore:adder|unreg_res_node[6] lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6]~mem_cell_ra0 lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6] lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0] Mux0~4 Mux0~5 Mux0~15 Mux0~10 vred[1]~6 vred[1]~reg0 } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "34.500 ns" { lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] {} lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~COUT {} lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~COUT {} lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~COUT {} lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~COUT {} lpm_add_sub:Add6|addcore:adder|unreg_res_node[6] {} lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6]~mem_cell_ra0 {} lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6] {} lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0 {} lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0] {} Mux0~4 {} Mux0~5 {} Mux0~15 {} Mux0~10 {} vred[1]~6 {} vred[1]~reg0 {} } { 0.000ns 1.300ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns 0.000ns 2.900ns 0.000ns 1.300ns 0.200ns 0.200ns 0.000ns 1.100ns 1.800ns } { 0.000ns 0.600ns 0.100ns 0.100ns 0.100ns 1.300ns 6.300ns 0.000ns 6.300ns 0.000ns 1.400ns 1.500ns 0.900ns 1.500ns 1.400ns 2.000ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'fclk' 16 " "Warning: Can't achieve timing requirement Clock Setup: 'fclk' along 16 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_RESULT" "spick register indata\[4\] register indata\[5\] 176.344 ns " "Info: Slack time is 176.344 ns for clock \"spick\" between source register \"indata\[4\]\" and destination register \"indata\[5\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "166.67 MHz " "Info: Fmax is restricted to 166.67 MHz due to tcl and tch limits" {  } {  } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "179.444 ns + Largest register register " "Info: + Largest register to register requirement is 179.444 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "180.844 ns + " "Info: + Setup relationship between source and destination is 180.844 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 180.844 ns " "Info: + Latch edge is 180.844 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination spick 180.844 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"spick\" is 180.844 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source spick 180.844 ns 0.000 ns  50 " "Info: Clock period of Source clock \"spick\" is 180.844 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "spick destination 3.500 ns + Shortest register " "Info: + Shortest clock path from clock \"spick\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns spick 1 CLK PIN_184 20 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_184; Fanout = 20; CLK Node = 'spick'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { spick } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns indata\[5\] 2 REG LC6_H22 6 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC6_H22; Fanout = 6; REG Node = 'indata\[5\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { spick indata[5] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 323 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick indata[5] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} indata[5] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "spick source 3.500 ns - Longest register " "Info: - Longest clock path from clock \"spick\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns spick 1 CLK PIN_184 20 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_184; Fanout = 20; CLK Node = 'spick'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { spick } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns indata\[4\] 2 REG LC1_H4 6 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_H4; Fanout = 6; REG Node = 'indata\[4\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { spick indata[4] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 323 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick indata[4] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} indata[4] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick indata[5] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} indata[5] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick indata[4] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} indata[4] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns - " "Info: - Micro clock to output delay of source is 0.700 ns" {  } { { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 323 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns - " "Info: - Micro setup delay of destination is 0.700 ns" {  } { { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 323 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick indata[5] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} indata[5] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick indata[4] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} indata[4] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.100 ns - Longest register register " "Info: - Longest register to register delay is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns indata\[4\] 1 REG LC1_H4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_H4; Fanout = 6; REG Node = 'indata\[4\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { indata[4] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 323 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(0.900 ns) 3.100 ns indata\[5\] 2 REG LC6_H22 6 " "Info: 2: + IC(2.200 ns) + CELL(0.900 ns) = 3.100 ns; Loc. = LC6_H22; Fanout = 6; REG Node = 'indata\[5\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { indata[4] indata[5] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 323 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns ( 29.03 % ) " "Info: Total cell delay = 0.900 ns ( 29.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns ( 70.97 % ) " "Info: Total interconnect delay = 2.200 ns ( 70.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { indata[4] indata[5] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { indata[4] {} indata[5] {} } { 0.000ns 2.200ns } { 0.000ns 0.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick indata[5] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} indata[5] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick indata[4] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} indata[4] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { indata[4] indata[5] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { indata[4] {} indata[5] {} } { 0.000ns 2.200ns } { 0.000ns 0.900ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "fclk register lpm_counter:voffset_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\] register lpm_counter:voffset_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\] 800 ps " "Info: Minimum slack time is 800 ps for clock \"fclk\" between source register \"lpm_counter:voffset_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\]\" and destination register \"lpm_counter:voffset_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.900 ns + Shortest register register " "Info: + Shortest register to register delay is 0.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:voffset_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\] 1 REG LC7_I17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_I17; Fanout = 2; REG Node = 'lpm_counter:voffset_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns lpm_counter:voffset_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\] 2 REG LC7_I17 2 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = LC7_I17; Fanout = 2; REG Node = 'lpm_counter:voffset_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns ( 100.00 % ) " "Info: Total cell delay = 0.900 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "0.900 ns" { lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] {} lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] {} } { 0.000ns 0.000ns } { 0.000ns 0.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.100 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.100 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination fclk 35.714 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"fclk\" is 35.714 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source fclk 35.714 ns 0.000 ns  50 " "Info: Clock period of Source clock \"fclk\" is 35.714 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fclk destination 3.500 ns + Longest register " "Info: + Longest clock path from clock \"fclk\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns fclk 1 CLK PIN_183 106 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_183; Fanout = 106; CLK Node = 'fclk'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { fclk } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns lpm_counter:voffset_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\] 2 REG LC7_I17 2 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC7_I17; Fanout = 2; REG Node = 'lpm_counter:voffset_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { fclk lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { fclk lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fclk source 3.500 ns - Shortest register " "Info: - Shortest clock path from clock \"fclk\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns fclk 1 CLK PIN_183 106 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_183; Fanout = 106; CLK Node = 'fclk'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { fclk } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns lpm_counter:voffset_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\] 2 REG LC7_I17 2 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC7_I17; Fanout = 2; REG Node = 'lpm_counter:voffset_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { fclk lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { fclk lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { fclk lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns - " "Info: - Micro clock to output delay of source is 0.700 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.800 ns + " "Info: + Micro hold delay of destination is 0.800 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { fclk lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "0.900 ns" { lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] {} lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] {} } { 0.000ns 0.000ns } { 0.000ns 0.900ns } "" } } { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { fclk lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "spick register bitptr\[0\] register bitptr\[0\] 1.0 ns " "Info: Minimum slack time is 1.0 ns for clock \"spick\" between source register \"bitptr\[0\]\" and destination register \"bitptr\[0\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.100 ns + Shortest register register " "Info: + Shortest register to register delay is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bitptr\[0\] 1 REG LC1_H21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_H21; Fanout = 5; REG Node = 'bitptr\[0\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { bitptr[0] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 336 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.900 ns) 1.100 ns bitptr\[0\] 2 REG LC1_H21 5 " "Info: 2: + IC(0.200 ns) + CELL(0.900 ns) = 1.100 ns; Loc. = LC1_H21; Fanout = 5; REG Node = 'bitptr\[0\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { bitptr[0] bitptr[0] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 336 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns ( 81.82 % ) " "Info: Total cell delay = 0.900 ns ( 81.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 18.18 % ) " "Info: Total interconnect delay = 0.200 ns ( 18.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { bitptr[0] bitptr[0] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "1.100 ns" { bitptr[0] {} bitptr[0] {} } { 0.000ns 0.200ns } { 0.000ns 0.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.100 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.100 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 90.422 ns " "Info: + Latch edge is 90.422 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination spick 180.844 ns 90.422 ns inverted 50 " "Info: Clock period of Destination clock \"spick\" is 180.844 ns with inverted offset of 90.422 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 90.422 ns " "Info: - Launch edge is 90.422 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source spick 180.844 ns 90.422 ns inverted 50 " "Info: Clock period of Source clock \"spick\" is 180.844 ns with inverted offset of 90.422 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "spick destination 3.500 ns + Longest register " "Info: + Longest clock path from clock \"spick\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns spick 1 CLK PIN_184 20 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_184; Fanout = 20; CLK Node = 'spick'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { spick } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns bitptr\[0\] 2 REG LC1_H21 5 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_H21; Fanout = 5; REG Node = 'bitptr\[0\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { spick bitptr[0] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 336 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick bitptr[0] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} bitptr[0] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "spick source 3.500 ns - Shortest register " "Info: - Shortest clock path from clock \"spick\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns spick 1 CLK PIN_184 20 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_184; Fanout = 20; CLK Node = 'spick'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { spick } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns bitptr\[0\] 2 REG LC1_H21 5 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_H21; Fanout = 5; REG Node = 'bitptr\[0\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { spick bitptr[0] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 336 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick bitptr[0] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} bitptr[0] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick bitptr[0] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} bitptr[0] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} bitptr[0] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns - " "Info: - Micro clock to output delay of source is 0.700 ns" {  } { { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 336 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.800 ns + " "Info: + Micro hold delay of destination is 0.800 ns" {  } { { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 336 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick bitptr[0] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} bitptr[0] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} bitptr[0] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { bitptr[0] bitptr[0] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "1.100 ns" { bitptr[0] {} bitptr[0] {} } { 0.000ns 0.200ns } { 0.000ns 0.900ns } "" } } { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick bitptr[0] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} bitptr[0] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} bitptr[0] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "outdata\[6\] d\[6\] fclk 6.500 ns register " "Info: tsu for register \"outdata\[6\]\" (data pin = \"d\[6\]\", clock pin = \"fclk\") is 6.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.300 ns + Longest pin register " "Info: + Longest pin to register delay is 9.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns d\[6\] 1 PIN PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_12; Fanout = 1; PIN Node = 'd\[6\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[6] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns d\[6\]~9 2 COMB IOC_12 1 " "Info: 2: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = IOC_12; Fanout = 1; COMB Node = 'd\[6\]~9'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { d[6] d[6]~9 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.300 ns) + CELL(1.000 ns) 9.300 ns outdata\[6\] 3 REG LC3_H20 1 " "Info: 3: + IC(5.300 ns) + CELL(1.000 ns) = 9.300 ns; Loc. = LC3_H20; Fanout = 1; REG Node = 'outdata\[6\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.300 ns" { d[6]~9 outdata[6] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 339 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 43.01 % ) " "Info: Total cell delay = 4.000 ns ( 43.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.300 ns ( 56.99 % ) " "Info: Total interconnect delay = 5.300 ns ( 56.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.300 ns" { d[6] d[6]~9 outdata[6] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "9.300 ns" { d[6] {} d[6]~9 {} outdata[6] {} } { 0.000ns 0.000ns 5.300ns } { 0.000ns 3.000ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 339 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fclk destination 3.500 ns - Shortest register " "Info: - Shortest clock path from clock \"fclk\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns fclk 1 CLK PIN_183 106 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_183; Fanout = 106; CLK Node = 'fclk'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { fclk } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns outdata\[6\] 2 REG LC3_H20 1 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC3_H20; Fanout = 1; REG Node = 'outdata\[6\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { fclk outdata[6] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 339 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { fclk outdata[6] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} outdata[6] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.300 ns" { d[6] d[6]~9 outdata[6] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "9.300 ns" { d[6] {} d[6]~9 {} outdata[6] {} } { 0.000ns 0.000ns 5.300ns } { 0.000ns 3.000ns 1.000ns } "" } } { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { fclk outdata[6] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { fclk {} fclk~out {} outdata[6] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "spick spidi bitptr\[1\] 20.200 ns register " "Info: tco from clock \"spick\" to destination pin \"spidi\" through register \"bitptr\[1\]\" is 20.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "spick source 3.500 ns + Longest register " "Info: + Longest clock path from clock \"spick\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns spick 1 CLK PIN_184 20 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_184; Fanout = 20; CLK Node = 'spick'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { spick } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns bitptr\[1\] 2 REG LC2_H24 6 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC2_H24; Fanout = 6; REG Node = 'bitptr\[1\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { spick bitptr[1] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 336 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick bitptr[1] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} bitptr[1] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 336 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.000 ns + Longest register pin " "Info: + Longest register to pin delay is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bitptr\[1\] 1 REG LC2_H24 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_H24; Fanout = 6; REG Node = 'bitptr\[1\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { bitptr[1] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 336 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.600 ns) 2.900 ns Mux1~0 2 COMB LC6_H20 1 " "Info: 2: + IC(1.300 ns) + CELL(1.600 ns) = 2.900 ns; Loc. = LC6_H20; Fanout = 1; COMB Node = 'Mux1~0'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { bitptr[1] Mux1~0 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 381 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.500 ns) 4.600 ns Mux1~1 3 COMB LC2_H20 1 " "Info: 3: + IC(0.200 ns) + CELL(1.500 ns) = 4.600 ns; Loc. = LC2_H20; Fanout = 1; COMB Node = 'Mux1~1'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { Mux1~0 Mux1~1 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 381 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.500 ns) 8.000 ns spidi~1 4 COMB LC7_H2 1 " "Info: 4: + IC(1.900 ns) + CELL(1.500 ns) = 8.000 ns; Loc. = LC7_H2; Fanout = 1; COMB Node = 'spidi~1'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { Mux1~1 spidi~1 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.600 ns) 9.800 ns spidi~2 5 COMB LC5_H2 1 " "Info: 5: + IC(0.200 ns) + CELL(1.600 ns) = 9.800 ns; Loc. = LC5_H2; Fanout = 1; COMB Node = 'spidi~2'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { spidi~1 spidi~2 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(4.900 ns) 16.000 ns spidi 6 PIN PIN_158 0 " "Info: 6: + IC(1.300 ns) + CELL(4.900 ns) = 16.000 ns; Loc. = PIN_158; Fanout = 0; PIN Node = 'spidi'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.200 ns" { spidi~2 spidi } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns ( 69.38 % ) " "Info: Total cell delay = 11.100 ns ( 69.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns ( 30.63 % ) " "Info: Total interconnect delay = 4.900 ns ( 30.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { bitptr[1] Mux1~0 Mux1~1 spidi~1 spidi~2 spidi } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "16.000 ns" { bitptr[1] {} Mux1~0 {} Mux1~1 {} spidi~1 {} spidi~2 {} spidi {} } { 0.000ns 1.300ns 0.200ns 1.900ns 0.200ns 1.300ns } { 0.000ns 1.600ns 1.500ns 1.500ns 1.600ns 4.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick bitptr[1] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} bitptr[1] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { bitptr[1] Mux1~0 Mux1~1 spidi~1 spidi~2 spidi } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "16.000 ns" { bitptr[1] {} Mux1~0 {} Mux1~1 {} spidi~1 {} spidi~2 {} spidi {} } { 0.000ns 1.300ns 0.200ns 1.900ns 0.200ns 1.300ns } { 0.000ns 1.600ns 1.500ns 1.500ns 1.600ns 4.900ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "sddi spidi 19.000 ns Longest " "Info: Longest tpd from source pin \"sddi\" to destination pin \"spidi\" is 19.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns sddi 1 PIN PIN_115 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_115; Fanout = 1; PIN Node = 'sddi'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { sddi } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.400 ns) + CELL(1.600 ns) 11.000 ns spidi~1 2 COMB LC7_H2 1 " "Info: 2: + IC(6.400 ns) + CELL(1.600 ns) = 11.000 ns; Loc. = LC7_H2; Fanout = 1; COMB Node = 'spidi~1'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { sddi spidi~1 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.600 ns) 12.800 ns spidi~2 3 COMB LC5_H2 1 " "Info: 3: + IC(0.200 ns) + CELL(1.600 ns) = 12.800 ns; Loc. = LC5_H2; Fanout = 1; COMB Node = 'spidi~2'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { spidi~1 spidi~2 } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(4.900 ns) 19.000 ns spidi 4 PIN PIN_158 0 " "Info: 4: + IC(1.300 ns) + CELL(4.900 ns) = 19.000 ns; Loc. = PIN_158; Fanout = 0; PIN Node = 'spidi'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.200 ns" { spidi~2 spidi } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns ( 58.42 % ) " "Info: Total cell delay = 11.100 ns ( 58.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.900 ns ( 41.58 % ) " "Info: Total interconnect delay = 7.900 ns ( 41.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "19.000 ns" { sddi spidi~1 spidi~2 spidi } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "19.000 ns" { sddi {} sddi~out {} spidi~1 {} spidi~2 {} spidi {} } { 0.000ns 0.000ns 6.400ns 0.200ns 1.300ns } { 0.000ns 3.000ns 1.600ns 1.600ns 4.900ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "number\[7\] spics_n spick -0.600 ns register " "Info: th for register \"number\[7\]\" (data pin = \"spics_n\", clock pin = \"spick\") is -0.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "spick destination 3.500 ns + Longest register " "Info: + Longest clock path from clock \"spick\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns spick 1 CLK PIN_184 20 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_184; Fanout = 20; CLK Node = 'spick'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { spick } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns number\[7\] 2 REG LC7_H3 5 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC7_H3; Fanout = 5; REG Node = 'number\[7\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { spick number[7] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 323 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick number[7] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} number[7] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.800 ns + " "Info: + Micro hold delay of destination is 0.800 ns" {  } { { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 323 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns spics_n 1 PIN PIN_182 14 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_182; Fanout = 14; PIN Node = 'spics_n'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { spics_n } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 107 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(0.900 ns) 4.900 ns number\[7\] 2 REG LC7_H3 5 " "Info: 2: + IC(1.800 ns) + CELL(0.900 ns) = 4.900 ns; Loc. = LC7_H3; Fanout = 5; REG Node = 'number\[7\]'" {  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { spics_n number[7] } "NODE_NAME" } } { "main.v" "" { Text "C:/Documents and Settings/Ewgeny7/╨рсюўшщ ёЄюы/ScorpEvo_6/flasher/fpga/main.v" 323 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns ( 63.27 % ) " "Info: Total cell delay = 3.100 ns ( 63.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns ( 36.73 % ) " "Info: Total interconnect delay = 1.800 ns ( 36.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { spics_n number[7] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "4.900 ns" { spics_n {} spics_n~out {} number[7] {} } { 0.000ns 0.000ns 1.800ns } { 0.000ns 2.200ns 0.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { spick number[7] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { spick {} spick~out {} number[7] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { spics_n number[7] } "NODE_NAME" } } { "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/90/quartus/bin/Technology_Viewer.qrui" "4.900 ns" { spics_n {} spics_n~out {} number[7] {} } { 0.000ns 0.000ns 1.800ns } { 0.000ns 2.200ns 0.900ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WTAN_REQUIREMENTS_NOT_MET_SLOW" "" "Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details." {  } {  } 1 0 "Timing requirements for slow timing model timing analysis were not met. See Report window for details." 0 0 "" 0 -1}
{ "Warning" "WTAN_INVALID_ASSIGNMENTS_FOUND" "" "Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details" {  } {  } 0 0 "Found invalid timing assignments -- see Ignored Timing Assignments report for details" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 19 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "135 " "Info: Peak virtual memory: 135 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 18:42:12 2011 " "Info: Processing ended: Mon Nov 14 18:42:12 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Subversion Repositories pentevo

?pathlinks? – Rev 1029
