Subversion Repositories pentevo

|main
fclk => main_osc[2].CLK
fclk => main_osc[1].CLK
fclk => main_osc[0].CLK
fclk => hcharcount[5].CLK
fclk => hcharcount[4].CLK
fclk => hcharcount[3].CLK
fclk => hcharcount[2].CLK
fclk => hcharcount[1].CLK
fclk => hcharcount[0].CLK
fclk => hcount[8].CLK
fclk => hcount[7].CLK
fclk => hcount[6].CLK
fclk => hcount[5].CLK
fclk => hcount[4].CLK
fclk => hcount[3].CLK
fclk => hcount[2].CLK
fclk => hcount[1].CLK
fclk => hcount[0].CLK
fclk => hblank.CLK
fclk => hsync.CLK
fclk => csync.CLK
fclk => vgrn[1]~reg0.CLK
fclk => vgrn[0]~reg0.CLK
fclk => vred[1]~reg0.CLK
fclk => vred[0]~reg0.CLK
fclk => vblu[1]~reg0.CLK
fclk => vblu[0]~reg0.CLK
fclk => voffset[6].CLK
fclk => voffset[5].CLK
fclk => voffset[4].CLK
fclk => voffset[3].CLK
fclk => voffset[2].CLK
fclk => voffset[1].CLK
fclk => voffset[0].CLK
fclk => vcharline[2].CLK
fclk => vcharline[1].CLK
fclk => vcharline[0].CLK
fclk => vcount[9].CLK
fclk => vcount[8].CLK
fclk => vcount[7].CLK
fclk => vcount[6].CLK
fclk => vcount[5].CLK
fclk => vcount[4].CLK
fclk => vcount[3].CLK
fclk => vcount[2].CLK
fclk => vcount[1].CLK
fclk => vcount[0].CLK
fclk => vblank.CLK
fclk => vsync.CLK
fclk => spicsn_resync[1].CLK
fclk => spicsn_resync[0].CLK
fclk => flash_cs.CLK
fclk => flash_oe.CLK
fclk => flash_we.CLK
fclk => flash_data_out[7].CLK
fclk => flash_data_out[6].CLK
fclk => flash_data_out[5].CLK
fclk => flash_data_out[4].CLK
fclk => flash_data_out[3].CLK
fclk => flash_data_out[2].CLK
fclk => flash_data_out[1].CLK
fclk => flash_data_out[0].CLK
fclk => flash_addr[18].CLK
fclk => flash_addr[17].CLK
fclk => flash_addr[16].CLK
fclk => flash_addr[15].CLK
fclk => flash_addr[14].CLK
fclk => flash_addr[13].CLK
fclk => flash_addr[12].CLK
fclk => flash_addr[11].CLK
fclk => flash_addr[10].CLK
fclk => flash_addr[9].CLK
fclk => flash_addr[8].CLK
fclk => flash_addr[7].CLK
fclk => flash_addr[6].CLK
fclk => flash_addr[5].CLK
fclk => flash_addr[4].CLK
fclk => flash_addr[3].CLK
fclk => flash_addr[2].CLK
fclk => flash_addr[1].CLK
fclk => flash_addr[0].CLK
fclk => scr_tv_mode.CLK
fclk => scr_char[6].CLK
fclk => scr_char[5].CLK
fclk => scr_char[4].CLK
fclk => scr_char[3].CLK
fclk => scr_char[2].CLK
fclk => scr_char[1].CLK
fclk => scr_char[0].CLK
fclk => scr_wren_c.CLK
fclk => scr_addr[9].CLK
fclk => scr_addr[8].CLK
fclk => scr_addr[7].CLK
fclk => scr_addr[6].CLK
fclk => scr_addr[5].CLK
fclk => scr_addr[4].CLK
fclk => scr_addr[3].CLK
fclk => scr_addr[2].CLK
fclk => scr_addr[1].CLK
fclk => scr_addr[0].CLK
fclk => outdata[7].CLK
fclk => outdata[6].CLK
fclk => outdata[5].CLK
fclk => outdata[4].CLK
fclk => outdata[3].CLK
fclk => outdata[2].CLK
fclk => outdata[1].CLK
fclk => outdata[0].CLK
clkz_out <= main_osc[2].DB_MAX_OUTPUT_PORT_TYPE
clkz_in => ~NO_FANOUT~
iorq_n => ~NO_FANOUT~
mreq_n => ~NO_FANOUT~
rd_n => ~NO_FANOUT~
wr_n => ~NO_FANOUT~
m1_n => ~NO_FANOUT~
rfsh_n => ~NO_FANOUT~
int_n => ~NO_FANOUT~
nmi_n => ~NO_FANOUT~
wait_n => ~NO_FANOUT~
res <= <VCC>
d[0] <= d[0]~7
d[1] <= d[1]~6
d[2] <= d[2]~5
d[3] <= d[3]~4
d[4] <= d[4]~3
d[5] <= d[5]~2
d[6] <= d[6]~1
d[7] <= d[7]~0
a[0] <= flash_addr[0].DB_MAX_OUTPUT_PORT_TYPE
a[1] <= flash_addr[1].DB_MAX_OUTPUT_PORT_TYPE
a[2] <= flash_addr[2].DB_MAX_OUTPUT_PORT_TYPE
a[3] <= flash_addr[3].DB_MAX_OUTPUT_PORT_TYPE
a[4] <= flash_addr[4].DB_MAX_OUTPUT_PORT_TYPE
a[5] <= flash_addr[5].DB_MAX_OUTPUT_PORT_TYPE
a[6] <= flash_addr[6].DB_MAX_OUTPUT_PORT_TYPE
a[7] <= flash_addr[7].DB_MAX_OUTPUT_PORT_TYPE
a[8] <= flash_addr[8].DB_MAX_OUTPUT_PORT_TYPE
a[9] <= flash_addr[9].DB_MAX_OUTPUT_PORT_TYPE
a[10] <= flash_addr[10].DB_MAX_OUTPUT_PORT_TYPE
a[11] <= flash_addr[11].DB_MAX_OUTPUT_PORT_TYPE
a[12] <= flash_addr[12].DB_MAX_OUTPUT_PORT_TYPE
a[13] <= flash_addr[13].DB_MAX_OUTPUT_PORT_TYPE
a[14] <= <GND>
a[15] <= <GND>
csrom <= flash_cs.DB_MAX_OUTPUT_PORT_TYPE
romoe_n <= flash_oe.DB_MAX_OUTPUT_PORT_TYPE
romwe_n <= flash_we.DB_MAX_OUTPUT_PORT_TYPE
rompg0_n <= flash_addr[14].DB_MAX_OUTPUT_PORT_TYPE
dos_n <= flash_addr[15].DB_MAX_OUTPUT_PORT_TYPE
rompg2 <= flash_addr[16].DB_MAX_OUTPUT_PORT_TYPE
rompg3 <= flash_addr[17].DB_MAX_OUTPUT_PORT_TYPE
rompg4 <= flash_addr[18].DB_MAX_OUTPUT_PORT_TYPE
iorqge1 => ~NO_FANOUT~
iorqge2 => ~NO_FANOUT~
iorq1_n <= <VCC>
iorq2_n <= <VCC>
rd[0] => ~NO_FANOUT~
rd[1] => ~NO_FANOUT~
rd[2] => ~NO_FANOUT~
rd[3] => ~NO_FANOUT~
rd[4] => ~NO_FANOUT~
rd[5] => ~NO_FANOUT~
rd[6] => ~NO_FANOUT~
rd[7] => ~NO_FANOUT~
rd[8] => ~NO_FANOUT~
rd[9] => ~NO_FANOUT~
rd[10] => ~NO_FANOUT~
rd[11] => ~NO_FANOUT~
rd[12] => ~NO_FANOUT~
rd[13] => ~NO_FANOUT~
rd[14] => ~NO_FANOUT~
rd[15] => ~NO_FANOUT~
ra[0] => ~NO_FANOUT~
ra[1] => ~NO_FANOUT~
ra[2] => ~NO_FANOUT~
ra[3] => ~NO_FANOUT~
ra[4] => ~NO_FANOUT~
ra[5] => ~NO_FANOUT~
ra[6] => ~NO_FANOUT~
ra[7] => ~NO_FANOUT~
ra[8] => ~NO_FANOUT~
ra[9] => ~NO_FANOUT~
rwe_n <= <VCC>
rucas_n <= <VCC>
rlcas_n <= <VCC>
rras0_n <= <VCC>
rras1_n <= <VCC>
vred[0] <= vred[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vred[1] <= vred[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vgrn[0] <= vgrn[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vgrn[1] <= vgrn[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vblu[0] <= vblu[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vblu[1] <= vblu[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vhsync <= hsync.DB_MAX_OUTPUT_PORT_TYPE
vvsync <= vsync.DB_MAX_OUTPUT_PORT_TYPE
vcsync <= csync.DB_MAX_OUTPUT_PORT_TYPE
ay_clk => ~NO_FANOUT~
ay_bdir <= <GND>
ay_bc1 <= <GND>
beep <= spiint_n.DB_MAX_OUTPUT_PORT_TYPE
ide_a[0] => ~NO_FANOUT~
ide_a[1] => ~NO_FANOUT~
ide_a[2] => ~NO_FANOUT~
ide_d[0] => ~NO_FANOUT~
ide_d[1] => ~NO_FANOUT~
ide_d[2] => ~NO_FANOUT~
ide_d[3] => ~NO_FANOUT~
ide_d[4] => ~NO_FANOUT~
ide_d[5] => ~NO_FANOUT~
ide_d[6] => ~NO_FANOUT~
ide_d[7] => ~NO_FANOUT~
ide_d[8] => ~NO_FANOUT~
ide_d[9] => ~NO_FANOUT~
ide_d[10] => ~NO_FANOUT~
ide_d[11] => ~NO_FANOUT~
ide_d[12] => ~NO_FANOUT~
ide_d[13] => ~NO_FANOUT~
ide_d[14] => ~NO_FANOUT~
ide_d[15] => ~NO_FANOUT~
ide_dir <= <VCC>
ide_rdy => ~NO_FANOUT~
ide_cs0_n <= <VCC>
ide_cs1_n <= <VCC>
ide_rs_n <= <GND>
ide_rd_n <= <VCC>
ide_wr_n <= <VCC>
vg_clk => ~NO_FANOUT~
vg_cs_n <= <VCC>
vg_res_n <= <GND>
vg_hrdy => ~NO_FANOUT~
vg_rclk => ~NO_FANOUT~
vg_rawr => ~NO_FANOUT~
vg_a[0] => ~NO_FANOUT~
vg_a[1] => ~NO_FANOUT~
vg_wrd => ~NO_FANOUT~
vg_side => ~NO_FANOUT~
step => ~NO_FANOUT~
vg_sl => ~NO_FANOUT~
vg_sr => ~NO_FANOUT~
vg_tr43 => ~NO_FANOUT~
rdat_b_n => ~NO_FANOUT~
vg_wf_de => ~NO_FANOUT~
vg_drq => ~NO_FANOUT~
vg_irq => ~NO_FANOUT~
vg_wd => ~NO_FANOUT~
sdcs_n <= sdcs_n~0.DB_MAX_OUTPUT_PORT_TYPE
sddo <= sddo~0.DB_MAX_OUTPUT_PORT_TYPE
sdclk <= sdclk~0.DB_MAX_OUTPUT_PORT_TYPE
sddi => spidi~0.DATAB
spics_n => bitptr[2].PRESET
spics_n => bitptr[1].PRESET
spics_n => bitptr[0].PRESET
spics_n => spicsn_resync[0].DATAIN
spics_n => sd_selected.IN0
spics_n => sdcs_n~0.IN0
spics_n => indata[0].ENA
spics_n => indata[1].ENA
spics_n => indata[2].ENA
spics_n => indata[3].ENA
spics_n => indata[4].ENA
spics_n => indata[5].ENA
spics_n => indata[6].ENA
spics_n => indata[7].ENA
spics_n => number[0].ENA
spics_n => number[1].ENA
spics_n => number[2].ENA
spics_n => number[3].ENA
spics_n => number[4].ENA
spics_n => number[5].ENA
spics_n => number[6].ENA
spics_n => number[7].ENA
spick => number[7].CLK
spick => number[6].CLK
spick => number[5].CLK
spick => number[4].CLK
spick => number[3].CLK
spick => number[2].CLK
spick => number[1].CLK
spick => number[0].CLK
spick => indata[7].CLK
spick => indata[6].CLK
spick => indata[5].CLK
spick => indata[4].CLK
spick => indata[3].CLK
spick => indata[2].CLK
spick => indata[1].CLK
spick => indata[0].CLK
spick => sdclk~0.DATAB
spick => bitptr[2].CLK
spick => bitptr[1].CLK
spick => bitptr[0].CLK
spido => sddo~0.DATAB
spido => indata[0].DATAIN
spido => number[0].DATAIN
spidi <= spidi~0.DB_MAX_OUTPUT_PORT_TYPE
spiint_n => beep.DATAIN


|main|lpm_ram_dp0:scr_mem
data[0] => data[0]~6.IN1
data[1] => data[1]~5.IN1
data[2] => data[2]~4.IN1
data[3] => data[3]~3.IN1
data[4] => data[4]~2.IN1
data[5] => data[5]~1.IN1
data[6] => data[6]~0.IN1
rdaddress[0] => rdaddress[0]~9.IN1
rdaddress[1] => rdaddress[1]~8.IN1
rdaddress[2] => rdaddress[2]~7.IN1
rdaddress[3] => rdaddress[3]~6.IN1
rdaddress[4] => rdaddress[4]~5.IN1
rdaddress[5] => rdaddress[5]~4.IN1
rdaddress[6] => rdaddress[6]~3.IN1
rdaddress[7] => rdaddress[7]~2.IN1
rdaddress[8] => rdaddress[8]~1.IN1
rdaddress[9] => rdaddress[9]~0.IN1
wraddress[0] => wraddress[0]~9.IN1
wraddress[1] => wraddress[1]~8.IN1
wraddress[2] => wraddress[2]~7.IN1
wraddress[3] => wraddress[3]~6.IN1
wraddress[4] => wraddress[4]~5.IN1
wraddress[5] => wraddress[5]~4.IN1
wraddress[6] => wraddress[6]~3.IN1
wraddress[7] => wraddress[7]~2.IN1
wraddress[8] => wraddress[8]~1.IN1
wraddress[9] => wraddress[9]~0.IN1
wren => wren~0.IN1
q[0] <= lpm_ram_dp:lpm_ram_dp_component.q
q[1] <= lpm_ram_dp:lpm_ram_dp_component.q
q[2] <= lpm_ram_dp:lpm_ram_dp_component.q
q[3] <= lpm_ram_dp:lpm_ram_dp_component.q
q[4] <= lpm_ram_dp:lpm_ram_dp_component.q
q[5] <= lpm_ram_dp:lpm_ram_dp_component.q
q[6] <= lpm_ram_dp:lpm_ram_dp_component.q


|main|lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component
data[0] => altdpram:sram.data[0]
data[1] => altdpram:sram.data[1]
data[2] => altdpram:sram.data[2]
data[3] => altdpram:sram.data[3]
data[4] => altdpram:sram.data[4]
data[5] => altdpram:sram.data[5]
data[6] => altdpram:sram.data[6]
rdaddress[0] => altdpram:sram.rdaddress[0]
rdaddress[1] => altdpram:sram.rdaddress[1]
rdaddress[2] => altdpram:sram.rdaddress[2]
rdaddress[3] => altdpram:sram.rdaddress[3]
rdaddress[4] => altdpram:sram.rdaddress[4]
rdaddress[5] => altdpram:sram.rdaddress[5]
rdaddress[6] => altdpram:sram.rdaddress[6]
rdaddress[7] => altdpram:sram.rdaddress[7]
rdaddress[8] => altdpram:sram.rdaddress[8]
rdaddress[9] => altdpram:sram.rdaddress[9]
wraddress[0] => altdpram:sram.wraddress[0]
wraddress[1] => altdpram:sram.wraddress[1]
wraddress[2] => altdpram:sram.wraddress[2]
wraddress[3] => altdpram:sram.wraddress[3]
wraddress[4] => altdpram:sram.wraddress[4]
wraddress[5] => altdpram:sram.wraddress[5]
wraddress[6] => altdpram:sram.wraddress[6]
wraddress[7] => altdpram:sram.wraddress[7]
wraddress[8] => altdpram:sram.wraddress[8]
wraddress[9] => altdpram:sram.wraddress[9]
rdclock => ~NO_FANOUT~
rdclken => ~NO_FANOUT~
wrclock => ~NO_FANOUT~
wrclken => ~NO_FANOUT~
rden => ~NO_FANOUT~
wren => altdpram:sram.wren
q[0] <= altdpram:sram.q[0]
q[1] <= altdpram:sram.q[1]
q[2] <= altdpram:sram.q[2]
q[3] <= altdpram:sram.q[3]
q[4] <= altdpram:sram.q[4]
q[5] <= altdpram:sram.q[5]
q[6] <= altdpram:sram.q[6]


|main|lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram
wren => segment[0][6].WE
wren => segment[0][5].WE
wren => segment[0][4].WE
wren => segment[0][3].WE
wren => segment[0][2].WE
wren => segment[0][1].WE
wren => segment[0][0].WE
data[0] => segment[0][0].DATAIN
data[1] => segment[0][1].DATAIN
data[2] => segment[0][2].DATAIN
data[3] => segment[0][3].DATAIN
data[4] => segment[0][4].DATAIN
data[5] => segment[0][5].DATAIN
data[6] => segment[0][6].DATAIN
wraddress[0] => segment[0][6].WADDR
wraddress[0] => segment[0][5].WADDR
wraddress[0] => segment[0][4].WADDR
wraddress[0] => segment[0][3].WADDR
wraddress[0] => segment[0][2].WADDR
wraddress[0] => segment[0][1].WADDR
wraddress[0] => segment[0][0].WADDR
wraddress[1] => segment[0][6].WADDR1
wraddress[1] => segment[0][5].WADDR1
wraddress[1] => segment[0][4].WADDR1
wraddress[1] => segment[0][3].WADDR1
wraddress[1] => segment[0][2].WADDR1
wraddress[1] => segment[0][1].WADDR1
wraddress[1] => segment[0][0].WADDR1
wraddress[2] => segment[0][6].WADDR2
wraddress[2] => segment[0][5].WADDR2
wraddress[2] => segment[0][4].WADDR2
wraddress[2] => segment[0][3].WADDR2
wraddress[2] => segment[0][2].WADDR2
wraddress[2] => segment[0][1].WADDR2
wraddress[2] => segment[0][0].WADDR2
wraddress[3] => segment[0][6].WADDR3
wraddress[3] => segment[0][5].WADDR3
wraddress[3] => segment[0][4].WADDR3
wraddress[3] => segment[0][3].WADDR3
wraddress[3] => segment[0][2].WADDR3
wraddress[3] => segment[0][1].WADDR3
wraddress[3] => segment[0][0].WADDR3
wraddress[4] => segment[0][6].WADDR4
wraddress[4] => segment[0][5].WADDR4
wraddress[4] => segment[0][4].WADDR4
wraddress[4] => segment[0][3].WADDR4
wraddress[4] => segment[0][2].WADDR4
wraddress[4] => segment[0][1].WADDR4
wraddress[4] => segment[0][0].WADDR4
wraddress[5] => segment[0][6].WADDR5
wraddress[5] => segment[0][5].WADDR5
wraddress[5] => segment[0][4].WADDR5
wraddress[5] => segment[0][3].WADDR5
wraddress[5] => segment[0][2].WADDR5
wraddress[5] => segment[0][1].WADDR5
wraddress[5] => segment[0][0].WADDR5
wraddress[6] => segment[0][6].WADDR6
wraddress[6] => segment[0][5].WADDR6
wraddress[6] => segment[0][4].WADDR6
wraddress[6] => segment[0][3].WADDR6
wraddress[6] => segment[0][2].WADDR6
wraddress[6] => segment[0][1].WADDR6
wraddress[6] => segment[0][0].WADDR6
wraddress[7] => segment[0][6].WADDR7
wraddress[7] => segment[0][5].WADDR7
wraddress[7] => segment[0][4].WADDR7
wraddress[7] => segment[0][3].WADDR7
wraddress[7] => segment[0][2].WADDR7
wraddress[7] => segment[0][1].WADDR7
wraddress[7] => segment[0][0].WADDR7
wraddress[8] => segment[0][6].WADDR8
wraddress[8] => segment[0][5].WADDR8
wraddress[8] => segment[0][4].WADDR8
wraddress[8] => segment[0][3].WADDR8
wraddress[8] => segment[0][2].WADDR8
wraddress[8] => segment[0][1].WADDR8
wraddress[8] => segment[0][0].WADDR8
wraddress[9] => segment[0][6].WADDR9
wraddress[9] => segment[0][5].WADDR9
wraddress[9] => segment[0][4].WADDR9
wraddress[9] => segment[0][3].WADDR9
wraddress[9] => segment[0][2].WADDR9
wraddress[9] => segment[0][1].WADDR9
wraddress[9] => segment[0][0].WADDR9
inclock => ~NO_FANOUT~
inclocken => ~NO_FANOUT~
rden => segment[0][6].RE
rden => segment[0][5].RE
rden => segment[0][4].RE
rden => segment[0][3].RE
rden => segment[0][2].RE
rden => segment[0][1].RE
rden => segment[0][0].RE
rdaddress[0] => segment[0][6].RADDR
rdaddress[0] => segment[0][5].RADDR
rdaddress[0] => segment[0][4].RADDR
rdaddress[0] => segment[0][3].RADDR
rdaddress[0] => segment[0][2].RADDR
rdaddress[0] => segment[0][1].RADDR
rdaddress[0] => segment[0][0].RADDR
rdaddress[1] => segment[0][6].RADDR1
rdaddress[1] => segment[0][5].RADDR1
rdaddress[1] => segment[0][4].RADDR1
rdaddress[1] => segment[0][3].RADDR1
rdaddress[1] => segment[0][2].RADDR1
rdaddress[1] => segment[0][1].RADDR1
rdaddress[1] => segment[0][0].RADDR1
rdaddress[2] => segment[0][6].RADDR2
rdaddress[2] => segment[0][5].RADDR2
rdaddress[2] => segment[0][4].RADDR2
rdaddress[2] => segment[0][3].RADDR2
rdaddress[2] => segment[0][2].RADDR2
rdaddress[2] => segment[0][1].RADDR2
rdaddress[2] => segment[0][0].RADDR2
rdaddress[3] => segment[0][6].RADDR3
rdaddress[3] => segment[0][5].RADDR3
rdaddress[3] => segment[0][4].RADDR3
rdaddress[3] => segment[0][3].RADDR3
rdaddress[3] => segment[0][2].RADDR3
rdaddress[3] => segment[0][1].RADDR3
rdaddress[3] => segment[0][0].RADDR3
rdaddress[4] => segment[0][6].RADDR4
rdaddress[4] => segment[0][5].RADDR4
rdaddress[4] => segment[0][4].RADDR4
rdaddress[4] => segment[0][3].RADDR4
rdaddress[4] => segment[0][2].RADDR4
rdaddress[4] => segment[0][1].RADDR4
rdaddress[4] => segment[0][0].RADDR4
rdaddress[5] => segment[0][6].RADDR5
rdaddress[5] => segment[0][5].RADDR5
rdaddress[5] => segment[0][4].RADDR5
rdaddress[5] => segment[0][3].RADDR5
rdaddress[5] => segment[0][2].RADDR5
rdaddress[5] => segment[0][1].RADDR5
rdaddress[5] => segment[0][0].RADDR5
rdaddress[6] => segment[0][6].RADDR6
rdaddress[6] => segment[0][5].RADDR6
rdaddress[6] => segment[0][4].RADDR6
rdaddress[6] => segment[0][3].RADDR6
rdaddress[6] => segment[0][2].RADDR6
rdaddress[6] => segment[0][1].RADDR6
rdaddress[6] => segment[0][0].RADDR6
rdaddress[7] => segment[0][6].RADDR7
rdaddress[7] => segment[0][5].RADDR7
rdaddress[7] => segment[0][4].RADDR7
rdaddress[7] => segment[0][3].RADDR7
rdaddress[7] => segment[0][2].RADDR7
rdaddress[7] => segment[0][1].RADDR7
rdaddress[7] => segment[0][0].RADDR7
rdaddress[8] => segment[0][6].RADDR8
rdaddress[8] => segment[0][5].RADDR8
rdaddress[8] => segment[0][4].RADDR8
rdaddress[8] => segment[0][3].RADDR8
rdaddress[8] => segment[0][2].RADDR8
rdaddress[8] => segment[0][1].RADDR8
rdaddress[8] => segment[0][0].RADDR8
rdaddress[9] => segment[0][6].RADDR9
rdaddress[9] => segment[0][5].RADDR9
rdaddress[9] => segment[0][4].RADDR9
rdaddress[9] => segment[0][3].RADDR9
rdaddress[9] => segment[0][2].RADDR9
rdaddress[9] => segment[0][1].RADDR9
rdaddress[9] => segment[0][0].RADDR9
outclock => ~NO_FANOUT~
outclocken => ~NO_FANOUT~
aclr => ~NO_FANOUT~
byteena[0] => ~NO_FANOUT~
wraddressstall => ~NO_FANOUT~
rdaddressstall => ~NO_FANOUT~
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT


|main|lpm_rom0:chargen
address[0] => address[0]~9.IN1
address[1] => address[1]~8.IN1
address[2] => address[2]~7.IN1
address[3] => address[3]~6.IN1
address[4] => address[4]~5.IN1
address[5] => address[5]~4.IN1
address[6] => address[6]~3.IN1
address[7] => address[7]~2.IN1
address[8] => address[8]~1.IN1
address[9] => address[9]~0.IN1
q[0] <= lpm_rom:lpm_rom_component.q
q[1] <= lpm_rom:lpm_rom_component.q
q[2] <= lpm_rom:lpm_rom_component.q
q[3] <= lpm_rom:lpm_rom_component.q
q[4] <= lpm_rom:lpm_rom_component.q
q[5] <= lpm_rom:lpm_rom_component.q
q[6] <= lpm_rom:lpm_rom_component.q
q[7] <= lpm_rom:lpm_rom_component.q


|main|lpm_rom0:chargen|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
address[8] => altrom:srom.address[8]
address[9] => altrom:srom.address[9]
inclock => ~NO_FANOUT~
outclock => ~NO_FANOUT~
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE


|main|lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7
address[7] => segment[0][6].WADDR7
address[7] => segment[0][6].RADDR7
address[7] => segment[0][5].WADDR7
address[7] => segment[0][5].RADDR7
address[7] => segment[0][4].WADDR7
address[7] => segment[0][4].RADDR7
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
address[8] => segment[0][7].WADDR8
address[8] => segment[0][7].RADDR8
address[8] => segment[0][6].WADDR8
address[8] => segment[0][6].RADDR8
address[8] => segment[0][5].WADDR8
address[8] => segment[0][5].RADDR8
address[8] => segment[0][4].WADDR8
address[8] => segment[0][4].RADDR8
address[8] => segment[0][3].WADDR8
address[8] => segment[0][3].RADDR8
address[8] => segment[0][2].WADDR8
address[8] => segment[0][2].RADDR8
address[8] => segment[0][1].WADDR8
address[8] => segment[0][1].RADDR8
address[8] => segment[0][0].WADDR8
address[8] => segment[0][0].RADDR8
address[9] => segment[0][7].WADDR9
address[9] => segment[0][7].RADDR9
address[9] => segment[0][6].WADDR9
address[9] => segment[0][6].RADDR9
address[9] => segment[0][5].WADDR9
address[9] => segment[0][5].RADDR9
address[9] => segment[0][4].WADDR9
address[9] => segment[0][4].RADDR9
address[9] => segment[0][3].WADDR9
address[9] => segment[0][3].RADDR9
address[9] => segment[0][2].WADDR9
address[9] => segment[0][2].RADDR9
address[9] => segment[0][1].WADDR9
address[9] => segment[0][1].RADDR9
address[9] => segment[0][0].WADDR9
address[9] => segment[0][0].RADDR9
clocki => ~NO_FANOUT~
clocko => ~NO_FANOUT~
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT