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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 18:42:00 2011 " "Info: Processing started: Mon Nov 14 18:42:00 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off fpga -c main " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fpga -c main" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}{ "Info" "IMPP_MPP_USER_DEVICE" "main EP1K50QC208-3 " "Info: Selected device EP1K50QC208-3 for design \"main\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}{ "Info" "IFCHECKER_NON_REGISTERED_RAM_FOUND" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\] " "Info: Design contains non-registered write enable \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[0\]\". Random data may be written to it during initialization." { } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } } } 0 0 "Design contains non-registered write enable \"%1!s!\". Random data may be written to it during initialization." 0 0 "" 0 -1}{ "Info" "IFCHECKER_NON_REGISTERED_RAM_FOUND" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[1\] " "Info: Design contains non-registered write enable \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[1\]\". Random data may be written to it during initialization." { } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } } } 0 0 "Design contains non-registered write enable \"%1!s!\". Random data may be written to it during initialization." 0 0 "" 0 -1}{ "Info" "IFCHECKER_NON_REGISTERED_RAM_FOUND" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[2\] " "Info: Design contains non-registered write enable \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[2\]\". Random data may be written to it during initialization." { } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } } } 0 0 "Design contains non-registered write enable \"%1!s!\". Random data may be written to it during initialization." 0 0 "" 0 -1}{ "Info" "IFCHECKER_NON_REGISTERED_RAM_FOUND" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[3\] " "Info: Design contains non-registered write enable \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[3\]\". Random data may be written to it during initialization." { } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } } } 0 0 "Design contains non-registered write enable \"%1!s!\". Random data may be written to it during initialization." 0 0 "" 0 -1}{ "Info" "IFCHECKER_NON_REGISTERED_RAM_FOUND" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[4\] " "Info: Design contains non-registered write enable \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[4\]\". Random data may be written to it during initialization." { } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } } } 0 0 "Design contains non-registered write enable \"%1!s!\". Random data may be written to it during initialization." 0 0 "" 0 -1}{ "Info" "IFCHECKER_NON_REGISTERED_RAM_FOUND" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[5\] " "Info: Design contains non-registered write enable \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[5\]\". Random data may be written to it during initialization." { } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } } } 0 0 "Design contains non-registered write enable \"%1!s!\". Random data may be written to it during initialization." 0 0 "" 0 -1}{ "Info" "IFCHECKER_NON_REGISTERED_RAM_FOUND" "lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\] " "Info: Design contains non-registered write enable \"lpm_ram_dp0:scr_mem\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[6\]\". Random data may be written to it during initialization." { } { { "altdpram.tdf" "" { Text "f:/altera/90/quartus/libraries/megafunctions/altdpram.tdf" 195 2 0 } } } 0 0 "Design contains non-registered write enable \"%1!s!\". Random data may be written to it during initialization." 0 0 "" 0 -1}{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}{ "Info" "IF10KE_F10KE_WIRE_LUT_INSERTED" "6 " "Info: Inserted 6 logic cells in first fitting attempt" { } { } 0 0 "Inserted %1!d! logic cells in first fitting attempt" 0 0 "" 0 -1}{ "Info" "IFIT_FIT_ATTEMPT" "1 Mon Nov 14 2011 18:42:02 " "Info: Started fitting attempt 1 on Mon Nov 14 2011 at 18:42:02" { } { } 0 0 "Started fitting attempt %1!d! on %2!s! at %3!s!" 0 0 "" 0 -1}{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "180 " "Info: Peak virtual memory: 180 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 18:42:05 2011 " "Info: Processing ended: Mon Nov 14 18:42:05 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}