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  1. // ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
  2. //
  3. // frame INT generation
  4.  
  5. /*
  6.     This file is part of ZX-Evo Base Configuration firmware.
  7.  
  8.     ZX-Evo Base Configuration firmware is free software:
  9.     you can redistribute it and/or modify it under the terms of
  10.     the GNU General Public License as published by
  11.     the Free Software Foundation, either version 3 of the License, or
  12.     (at your option) any later version.
  13.  
  14.     ZX-Evo Base Configuration firmware is distributed in the hope that
  15.     it will be useful, but WITHOUT ANY WARRANTY; without even
  16.     the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  17.     See the GNU General Public License for more details.
  18.  
  19.     You should have received a copy of the GNU General Public License
  20.     along with ZX-Evo Base Configuration firmware.
  21.     If not, see <http://www.gnu.org/licenses/>.
  22. */
  23.  
  24. `include "../include/tune.v"
  25.  
  26. module zint
  27. (
  28.         input  wire fclk,
  29.  
  30.         input  wire zpos,
  31.         input  wire zneg,
  32.  
  33.         input  wire int_start,
  34.  
  35.         input  wire iorq_n,
  36.         input  wire m1_n,
  37.  
  38.         input  wire wait_n,
  39.  
  40.         output reg  int_n
  41. );
  42.  
  43.         wire intend;
  44.  
  45.         reg [9:0] intctr;
  46.  
  47.         reg [1:0] wr;
  48.  
  49.  
  50. `ifdef SIMULATE
  51.         initial
  52.         begin
  53.                 intctr = 10'b1100000000;
  54.         end
  55. `endif
  56.  
  57.         always @(posedge fclk)
  58.                 wr[1:0] <= { wr[0], wait_n };
  59.  
  60.         always @(posedge fclk)
  61.         begin
  62.                 if( int_start )
  63.                         intctr <= 10'd0;
  64.                 else if( !intctr[9:8] && wr[1] )
  65.                         intctr <= intctr + 10'd1;
  66.         end
  67.  
  68.  
  69.         assign intend = intctr[9:8] || ( (!iorq_n) && (!m1_n) && zneg );
  70.  
  71.  
  72.         always @(posedge fclk)
  73.         begin
  74.                 if( int_start )
  75.                         int_n <= 1'b0;
  76.                 else if( intend )
  77.                         int_n <= 1'bZ;
  78.         end
  79.  
  80.  
  81.  
  82.  
  83.  
  84. endmodule
  85.  
  86.