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$Revision: 1.2 $G. Hutchison
 OpenCores.org
 October 2004

tv80 Core Documentation

Abstract

A synthesizable 8-bit microprocessor which is instruction-set compatable with the Z80, targetted at embedded and system-on-a-chip designs.



Table of Contents

1.  Background
2.  Verification Environment
    2.1  Memory Map
    2.2  Control Registers
        2.2.1  Simulation control (0x80)
        2.2.2  Message output (0x81)
        2.2.3  Timeout control (0x82)
        2.2.4  Max timeout (0x84, 0x83)
        2.2.5  Interrupt countdown (0x90)
        2.2.6  Checksum value (0x91)
        2.2.7  Checksum accumulate (0x92)
        2.2.8  Increment on read (0x93)
    2.3  Tool Chain
    2.4  Tests
        2.4.1  tvs80 test
3.  References
§  Author's Address




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1. Background

The tv80 core was created as a Verilog port of the VHDL T80 coreWallner, D., VHDL T80 Core, .[1], for use as a maintenence processor inside an ASIC. The tv80 has been modified since then for better synthesis timing/area results, and to incorporate several bug-fixes.

The T80, and the tv80 derived from it, attempt to maintain the original cycle timings of the Z80, but have radically different internal designs and timings. With its target being ASIC and embedded applications, the tv80 does not attempt to maintain the original pinout of the Z80.



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2. Verification Environment

2.1 Memory Map

Environment memory space is divided into a 32k ROM region and a 32k RAM region, as follows:

  0000-7FFF:  ROM
  8000-FFFF:  RAM

Environment I/O space is allocated as follows:

  00-0F:  Unused
  10-1F:  Test devices
  20-7F:  Unused
  80-9F:  Environment control
  A0-FF:  Unused

2.2 Control Registers

2.2.1 Simulation control (0x80)

2.2.2 Message output (0x81)

Write characters to this port one at a time. When the newline ('\n', ASCII 0x0A) character is written, the environment will print out the collected string.

2.2.3 Timeout control (0x82)

Bit[0] enables the timeout counter, Bit[1] resets the counter to 0. Timeout counter defaults to enabled at simulation start.

2.2.4 Max timeout (0x84, 0x83)

Holds 16-bit timeout value (amount of time in clocks before timeout error occurs).

2.2.5 Interrupt countdown (0x90)

When set, starts a countdown (in clocks) until assertion of the INT_N signal.

2.2.6 Checksum value (0x91)

This register holds the checksum value of all data written to the accumulate register. The checksum is a simple twos-complement checksum, so it can be compared with a CPU-generated checksum.

This register is readable and writeable. Writing the register sets the current checksum value.

2.2.7 Checksum accumulate (0x92)

This write-only register adds the written value to the value contained in the Checksum Value register.

2.2.8 Increment on read (0x93)

This register increments every time it is read, so reading it repeatedly generates an incrementing sequence. It can be reset by writing it to a new starting value.

2.3 Tool Chain

The minimum toolchain required to simulate the tv80 is the CVerVanvick, A., GPL Cver Simulator, .[3] Verilog simulator, and the SDCC, Small Device C Compiler, .[2] compiler/assembler/linker. In addition, to run the tvs80tvs80 test instruction test suite, the DOSBox, DOSBox, .[4] DOS emulator is required.

2.4 Tests

Most of the tests in the tv80 environment are written in C, and should be compiled with the sdcc, Small Device C Compiler, .[2] compiler.

2.4.1 tvs80 test

The tvs80 test is different than the rest of the tests, and is written in its own flavor of assembly language. This test provides a fairly comprehensive Z80 instruction test.

The assembler for this test only runs under DOS. To assemble under Unix/Linux, the "dosbox" DOS emulator, DOSBox, .[4] is required. A script to run the assembler under dosbox, as well as the tvs80.asm source, is checked in under the "tests/tvs80" directory.



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3 References

[1] Wallner, D., "VHDL T80 Core".
[2] "Small Device C Compiler".
[3] Vanvick, A., "GPL Cver Simulator".
[4] "DOSBox".


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Author's Address

  Guy Hutchison
  OpenCores.org
EMail:  ghutchis@opencores.org