rgen Register File and Decoder Generator

rgen is a Python script for generating a hierarchical set of register files and address decoders. It supports a variety of register types and multiple levels of address decoding hieararchy.

Register File Generator

Tag Definitions

tag nameattributesdescription
tv_registersname,addr_sz,data_sz,base_addr,registered_readtop-level tag for a register file
registername,type,width,defaulttag for a single logical register
fieldname,width,defaulttag for a bit field within a single register
register typeAccessdescription
configRWGeneral read-write configuration register
statusRORead-only status register
countRWIncrementing statistics register
int_mskSpecialInterrupt status & mask registers
soft_setRWSoftware set, hardware clear register
write_stbRWConfiguration register with additional strobe output
read_stbRWConfiguration register with additional strobe outout
ext_loadRWExternal-load register
userSpecialUser-defined pass-through register

config

port namedirectionsizedescription
NAMEoutputWIDTHRead-only value of config bits

Basic configuration register, read/write by the configuration side, register bits available read-only from the hardware side.

status

port namedirectionsizedescription
NAMEinputWIDTHstatus input bits

Status register, read-only by the config side, status bits are combinatorial input from the hardware side.

count

port namedirectionsizedescription
NAMEoutputWIDTHcurrent count value
NAME_incinput1When high, increment count by 1

Basic statistics register. Read/write by config side, count value available read-only from hardware side. Increment value provided for hardware side.

int_msk

port namedirectionsizedescription
NAME_setinputWIDTHset interrupt

The int_msk register type provides a pair of interrupt registers. The first register is the interrupt status register, and the second is the interrupt mask register. The interrupt status register can be set by hardware and cleared by software by writing a ‘1’ to the bit which should be cleared. Software cannot set any bits in the interrupt register, and writing ‘0’ to a bit has no effect (leave unchanged).

The paired mask register has the same number of bits as the status register, but each bit set in the mask register disables interrupt generation for the corresponding status bit. Note that even if interrupt generation is disabled, the status bit will still be set. The mask register is Read/Write by software.

The default attribute for this register type sets the default value of the mask register; the default value of the status register is always zero.

soft_set

port namedirectionsizedescription
NAMEoutputWIDTHRead-only value of config bits
NAME_clrinputWIDTHRead-only value of config bits

write_stb

port namedirectionsizedescription
NAMEoutputWIDTHRead-only value of config bits
NAME_wr_stboutput1Pulses on write to this register

read_stb

port namedirectionsizedescription
NAMEoutputWIDTHRead-only value of config bits
NAME_wr_stboutput1Pulses on read to this register

ext_load

port namedirectionsizedescription
NAME_outoutputWIDTHData from config interface
NAME_ininputWIDTHSample data in to config interface
NAME_wr_stboutput1Pulsed on final write operation
NAME_rd_stboutput1Pulsed on initial read operation

An external-load register is used to sample and cache values which may be changing over time. It is intended to be used for values which are wider than the configuration interface (otherwise, a status or write_stb register would be more appropriate). The width of an ext_load register can be wider than the data_sz width of the module, and rgen will split the logical register into multiple physical registers.

Current limitations: ext_load registers must be an even multiple of data_size otherwise syntax errors will result.

user

port namedirectionsizedescription
NAME_wr_dataoutputWIDTHData from config on write
NAME_wr_stboutput1Asserted during write operation
NAME_wr_ackinput1Assert by HW side to acknowledge write
NAME_rd_datainputWIDTHData to config on read
NAME_rd_stboutput1Asserted during read operation
NAME_rd_ackinput1Assert by HW side to acknowledge read

Register with user-defined behavior. Used to implement registers with read-side effects, or where config interface must arbitrate with the HW datapath for access to a resource. Provides full handshake for each of read and write operations.

Decoder Generator

Decoders are created using a different set of tags from the register file generator.

tag nameattributesdescription
it_decodername,addr_sz,data_sztop-level tag for an address decoder
rangeprefix,base,bitstag for an address decode range
 
rgen.py.txt · Last modified: 2011/02/24 16:12 by 10.81.24.204
 
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