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; Copyright 1991-2007 Mentor Graphics Corporation;; All Rights Reserved.;; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.;[Library]std = $MODEL_TECH/../stdieee = $MODEL_TECH/../ieeeverilog = $MODEL_TECH/../verilogvital2000 = $MODEL_TECH/../vital2000std_developerskit = $MODEL_TECH/../std_developerskitsynopsys = $MODEL_TECH/../synopsysmodelsim_lib = $MODEL_TECH/../modelsim_libsv_std = $MODEL_TECH/../sv_std;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this releasework = work[vcom]; VHDL93 variable selects language version as the default.; Default is VHDL-2002.; Value of 0 or 1987 for VHDL-1987.; Value of 1 or 1993 for VHDL-1993.; Default or value of 2 or 2002 for VHDL-2002.VHDL93 = 2002; Show source line containing error. Default is off.; Show_source = 1; Turn off unbound-component warnings. Default is on.; Show_Warning1 = 0; Turn off process-without-a-wait-statement warnings. Default is on.; Show_Warning2 = 0; Turn off null-range warnings. Default is on.; Show_Warning3 = 0; Turn off no-space-in-time-literal warnings. Default is on.; Show_Warning4 = 0; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.; Show_Warning5 = 0; Turn off optimization for IEEE std_logic_1164 package. Default is on.; Optimize_1164 = 0; Turn on resolving of ambiguous function overloading in favor of the; "explicit" function declaration (not the one automatically created by; the compiler for each type declaration). Default is off.; The .ini file has Explicit enabled so that std_logic_signed/unsigned; will match the behavior of synthesis tools.Explicit = 1; Turn off acceleration of the VITAL packages. Default is to accelerate.; NoVital = 1; Turn off VITAL compliance checking. Default is checking on.; NoVitalCheck = 1; Ignore VITAL compliance checking errors. Default is to not ignore.; IgnoreVitalErrors = 1; Turn off VITAL compliance checking warnings. Default is to show warnings.; Show_VitalChecksWarnings = 0; Turn off PSL assertion warning messages. Default is to show warnings.; Show_PslChecksWarnings = 0; Enable parsing of embedded PSL assertions. Default is enabled.; EmbeddedPsl = 0; Keep silent about case statement static warnings.; Default is to give a warning.; NoCaseStaticError = 1; Keep silent about warnings caused by aggregates that are not locally static.; Default is to give a warning.; NoOthersStaticError = 1; Treat as errors:; case statement static warnings; warnings caused by aggregates that are not locally static; Overrides NoCaseStaticError, NoOthersStaticError settings.; PedanticErrors = 1; Turn off inclusion of debugging info within design units.; Default is to include debugging info.; NoDebug = 1; Turn off "Loading..." messages. Default is messages on.; Quiet = 1; Turn on some limited synthesis rule compliance checking. Checks only:; -- signals used (read) by a process must be in the sensitivity list; CheckSynthesis = 1; Activate optimizations on expressions that do not involve signals,; waits, or function/procedure/task invocations. Default is off.; ScalarOpts = 1; Turns on lint-style checking.; Show_Lint = 1; Require the user to specify a configuration for all bindings,; and do not generate a compile time default binding for the; component. This will result in an elaboration error of; 'component not bound' if the user fails to do so. Avoids the rare; issue of a false dependency upon the unused default binding.; RequireConfigForAllDefaultBinding = 1; Perform default binding at compile time.; Default is to do default binding at load time.; BindAtCompile=1;; Inhibit range checking on subscripts of arrays. Range checking on; scalars defined with subtypes is inhibited by default.; NoIndexCheck = 1; Inhibit range checks on all (implicit and explicit) assignments to; scalar objects defined with subtypes.; NoRangeCheck = 1; Run the 0in tools from within the simulator.; Default value set to 0. Please set it to 1 to invoke 0in.; VcomZeroIn = 1; Set the options to be passed to the 0in tools.; Default value set to "". Please set it to appropriate options needed.; VcomZeroInOptions = ""; Turn on code coverage in VHDL design units. Default is off.; Coverage = sbceft; Turn off code coverage in VHDL subprograms. Default is on.; CoverageNoSub = 0; Automatically exclude VHDL case statement default branches.; Default is to not exclude.; CoverExcludeDefault = 1; Turn on code coverage in VHDL generate blocks. Default is off.; CoverGenerate = 1; Inform code coverage optimizations to respect VHDL 'H' and 'L'; values on signals in conditions and expressions, and to not automatically; convert them to '1' and '0'. Default is to automatically convert.; CoverRespectHandL = 1; Use this directory for compiler temporary files instead of "work/_temp"; CompilerTempDir = /tmp[vlog]; Turn off inclusion of debugging info within design units.; Default is to include debugging info.; NoDebug = 1; Turn on `protect compiler directive processing.; Default is to ignore `protect directives.; Protect = 1; Turn off "Loading..." messages. Default is messages on.; Quiet = 1; Turn on Verilog hazard checking (order-dependent accessing of global vars).; Default is off.; Hazard = 1; Turn on converting regular Verilog identifiers to uppercase. Allows case; insensitivity for module names. Default is no conversion.; UpCase = 1; Activate optimizations on expressions that do not involve signals,; waits, or function/procedure/task invocations. Default is off.; ScalarOpts = 1; Turns on lint-style checking.; Show_Lint = 1; Show source line containing error. Default is off.; Show_source = 1; Turn on bad option warning. Default is off.; Show_BadOptionWarning = 1; Revert back to IEEE 1364-1995 syntax, default is 0 (off).vlog95compat = 0; Turn off PSL warning messages. Default is to show warnings.; Show_PslChecksWarnings = 0; Enable parsing of embedded PSL assertions. Default is enabled.; EmbeddedPsl = 0; Set the threshold for automatically identifying sparse Verilog memories.; A memory with depth equal to or more than the sparse memory threshold gets; marked as sparse automatically, unless specified otherwise in source code.; The default is 0 (i.e. no memory is automatically given sparse status); SparseMemThreshold = 1048576; Set the maximum number of iterations permitted for a generate loop.; Restricting this permits the implementation to recognize infinite; generate loops.; GenerateLoopIterationMax = 100000; Set the maximum depth permitted for a recursive generate instantiation.; Restricting this permits the implementation to recognize infinite; recursions.; GenerateRecursionDepthMax = 200; Run the 0in tools from within the simulator.; Default value set to 0. Please set it to 1 to invoke 0in.; VlogZeroIn = 1; Set the options to be passed to the 0in tools.; Default value set to "". Please set it to appropriate options needed.; VlogZeroInOptions = ""; Run the 0in tools from within the simulator.; Default value set to 0. Please set it to 1 to invoke 0in.; VoptZeroIn = 1; Set the options to be passed to the 0in tools.; Default value set to "". Please set it to appropriate options needed.; VoptZeroInOptions = ""; Set the option to treat all files specified in a vlog invocation as a; single compilation unit. The default value is set to 0 which will treat; each file as a separate compilation unit as specified in the P1800 draft standard.; MultiFileCompilationUnit = 1; Turn on code coverage in Verilog design units. Default is off.; Coverage = sbceft; Automatically exclude Verilog case statement default branches.; Default is to not exclude.; CoverExcludeDefault = 1; Turn on code coverage in VLOG generate blocks. Default is off.; CoverGenerate = 1; Turn on code coverage in VLOG `celldefine modules and modules included; using vlog -v and -y. Default is on.; CoverCells = 0; Specify the override for the default value of "cross_num_print_missing"; option for the Cross in Covergroups. If not specified then LRM default; value of 0 (zero) is used. This is a compile time option.; SVCrossNumPrintMissingDefault = 0; Setting following to 1 would cause creation of variables which; would represent the value of Coverpoint expressions. This is used; in conjunction with "SVCoverpointExprVariablePrefix" option; in the modelsim.ini; EnableSVCoverpointExprVariable = 0; Specify the override for the prefix used in forming the variable names; which represent the Coverpoint expressions. This is used in conjunction with; "EnableSVCoverpointExprVariable" option of the modelsim.ini; The default prefix is "expr".; The variable name is; variable name => <prefix>_<coverpoint name>; SVCoverpointExprVariablePrefix = expr; Override for the default value of the SystemVerilog covergroup,; coverpoint, and cross option.goal (defined to be 100 in the LRM).; NOTE: It does not override specific assignments in SystemVerilog; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"; can override this value.; SVCovergroupGoalDefault = 100; Override for the default value of the SystemVerilog covergroup,; coverpoint, and cross type_option.goal (defined to be 100 in the LRM); NOTE: It does not override specific assignments in SystemVerilog; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"; can override this value.; SVCovergroupTypeGoalDefault = 100; Specify the override for the default value of "strobe" option for the; Covergroup Type. This is a compile time option which forces "strobe" to; a user specified default value and supersedes SystemVerilog specified; default value of '0'(zero). NOTE: This can be overriden by a runtime; modelsim.ini variable "SVCovergroupStrobeDefault".; SVCovergroupStrobeDefault = 0[sccom]; Enable use of SCV include files and library. Default is off.; UseScv = 1; Add C++ compiler options to the sccom command line by using this variable.; CppOptions = -g; Use custom C++ compiler located at this path rather than the default path.; The path should point directly at a compiler executable.; CppPath = /usr/bin/g++; Enable verbose messages from sccom. Default is off.; SccomVerbose = 1; sccom logfile. Default is no logfile.; SccomLogfile = sccom.log; Enable use of SC_MS include files and library. Default is off.; UseScMs = 1[vsim]; vopt flow; Set to turn on automatic optimization of a design.; Default is onVoptFlow = 1; vopt automatic SDF; If automatic design optimization is on, enables automatic compilation; of SDF files.; Default is on, uncomment to turn off.; VoptAutoSDFCompile = 0; Simulator resolution; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.resolution = 1ns; User time unit for run commands; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the; unit specified for Resolution. For example, if Resolution is 100ps,; then UserTimeUnit defaults to ps.; Should generally be set to default.UserTimeUnit = default; Default run lengthRunLength = 1 us; Maximum iterations that can be run without advancing simulation timeIterationLimit = 5000; Control PSL and Verilog Assume directives during simulation; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts; SimulateAssumeDirectives = 1; Control the simulation of PSL and SVA; These switches can be overridden by the vsim command line switches:; -psl, -nopsl, -sva, -nosva.; Set SimulatePSL = 0 to disable PSL simulation; Set SimulatePSL = 1 to enable PSL simulation (default); SimulatePSL = 1; Set SimulateSVA = 0 to disable SVA simulation; Set SimulateSVA = 1 to enable concurrent SVA simulation (default); SimulateSVA = 1; Directives to license manager can be set either as single value or as; space separated multi-values:; vhdl Immediately reserve a VHDL license; vlog Immediately reserve a Verilog license; plus Immediately reserve a VHDL and Verilog license; nomgc Do not look for Mentor Graphics Licenses; nomti Do not look for Model Technology Licenses; noqueue Do not wait in the license queue when a license is not available; viewsim Try for viewer license but accept simulator license(s) instead; of queuing for viewer license (PE ONLY); noviewer Disable checkout of msimviewer and vsim-viewer license; features (PE ONLY); noslvhdl Disable checkout of qhsimvh and vsim license features; noslvlog Disable checkout of qhsimvl and vsimvlog license features; nomix Disable checkout of msimhdlmix and hdlmix license features; nolnl Disable checkout of msimhdlsim and hdlsim license features; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license; features; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,; hdlmix license features; Single value:; License = plus; Multi-value:; License = noqueue plus; Stop the simulator after a VHDL/Verilog immediate assertion message; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = FatalBreakOnAssertion = 3; VHDL assertion Message Format; %S - Severity Level; %R - Report Message; %T - Time of assertion; %D - Delta; %I - Instance or Region pathname (if available); %i - Instance pathname with process; %O - Process name; %K - Kind of object path is to return: Instance, Signal, Process or Unknown; %P - Instance or Region path without leaf process; %F - File; %L - Line number of assertion or, if assertion is in a subprogram, line; from which the call is made; %% - Print '%' character; If specific format for assertion level is defined, use its format.; If specific format is not defined for assertion level:; - and if failure occurs during elaboration, use AssertionFormatBreakLine;; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion; level), use AssertionFormatBreak;; - otherwise, use AssertionFormat.; AssertionFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"; AssertionFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"; AssertionFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"; AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"; AssertionFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"; AssertionFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"; AssertionFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages; AssertFile = assert.log; Simulation Breakpoint messages; This flag controls the display of function names when reporting the location; where the simulator stops do to a breakpoint or fatal error.; Example w/function name: # Break in Process ctr at counter.vhd line 44; Example wo/function name: # Break at counter.vhd line 44ShowFunctions = 1; Default radix for all windows and commands.; Set to symbolic, ascii, binary, octal, decimal, hex, unsignedDefaultRadix = symbolic; VSIM Startup command; Startup = do startup.do; File for saving command transcriptTranscriptFile = transcript; File for saving command history; CommandHistory = cmdhist.log; Specify whether paths in simulator commands should be described; in VHDL or Verilog format.; For VHDL, PathSeparator = /; For Verilog, PathSeparator = .; Must not be the same character as DatasetSeparator.PathSeparator = /; Specify the dataset separator for fully rooted contexts.; The default is ':'. For example: sim:/top; Must not be the same character as PathSeparator.DatasetSeparator = :; Specify a unique path separator for the Signal Spy set of functions.; The default will be to use the PathSeparator variable.; Must not be the same character as DatasetSeparator.; SignalSpyPathSeparator = /; Disable VHDL assertion messages; IgnoreNote = 1; IgnoreWarning = 1; IgnoreError = 1; IgnoreFailure = 1; Disable System Verilog assertion messages; Info and Warning are disabled by default; IgnoreSVAInfo = 0; IgnoreSVAWarning = 0; IgnoreSVAError = 1; IgnoreSVAFatal = 1; Default force kind. May be freeze, drive, deposit, or default; or in other terms, fixed, wired, or charged.; A value of "default" will use the signal kind to determine the; force kind, drive for resolved signals, freeze for unresolved signals; DefaultForceKind = freeze; If zero, open files when elaborated; otherwise, open files on; first read or write. Default is 0.; DelayFileOpen = 1; Control VHDL files opened for write.; 0 = Buffered, 1 = UnbufferedUnbufferedOutput = 0; Control the number of VHDL files open concurrently.; This number should always be less than the current ulimit; setting for max file descriptors.; 0 = unlimitedConcurrentFileLimit = 40; Control the number of hierarchical regions displayed as; part of a signal name shown in the Wave window.; A value of zero tells VSIM to display the full name.; The default is 0.; WaveSignalNameWidth = 0; Turn off warnings when changing VHDL constants and generics; Default is 1 to generate warning messages; WarnConstantChange = 0; Turn off warnings from the std_logic_arith, std_logic_unsigned; and std_logic_signed packages.; StdArithNoWarnings = 1; Turn off warnings from the IEEE numeric_std and numeric_bit packages.; NumericStdNoWarnings = 1; Control the format of the (VHDL) FOR generate statement label; for each iteration. Do not quote it.; The format string here must contain the conversion codes %s and %d,; in that order, and no other conversion codes. The %s represents; the generate_label; the %d represents the generate parameter value; at a particular generate iteration (this is the position number if; the generate parameter is of an enumeration type). Embedded whitespace; is allowed (but discouraged); leading and trailing whitespace is ignored.; Application of the format must result in a unique scope name over all; such names in the design so that name lookup can function properly.; GenerateFormat = %s__%d; Specify whether checkpoint files should be compressed.; The default is 1 (compressed).; CheckpointCompressMode = 0; Specify whether to enable SystemVerilog DPI out-of-the-blue call.; Out-of-the-blue call refers to a SystemVerilog export function call; directly from a C function that don't have the proper context setup; as done in DPI-C import C functions. When this is enabled, one can; call a DPI export function (but not task) from any C code.; The default is 0 (disabled).; DpiOutOfTheBlue = 1; List of dynamically loaded objects for Verilog PLI applications; Veriuser = veriuser.sl; Specify default options for the restart command. Options can be one; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions; DefaultRestartOptions = -force; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs; (> 500 megabyte memory footprint). Default is disabled.; Specify number of megabytes to lock.; LockedMemory = 1000; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading.; This is necessary when C++ files have been compiled with aCC's -AA option.; The default behavior is to use /usr/lib/libCsup.sl.; UseCsupV2 = 1; Turn on (1) or off (0) WLF file compression.; The default is 1 (compress WLF file).; WLFCompress = 0; Specify whether to save all design hierarchy (1) in the WLF file; or only regions containing logged signals (0).; The default is 0 (save only regions with logged signals).; WLFSaveAllRegions = 1; WLF file time limit. Limit WLF file by time, as closely as possible,; to the specified amount of simulation time. When the limit is exceeded; the earliest times get truncated from the file.; If both time and size limits are specified the most restrictive is used.; UserTimeUnits are used if time units are not specified.; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}; WLFTimeLimit = 0; WLF file size limit. Limit WLF file size, as closely as possible,; to the specified number of megabytes. If both time and size limits; are specified then the most restrictive is used.; The default is 0 (no limit).; WLFSizeLimit = 1000; Specify whether or not a WLF file should be deleted when the; simulation ends. A value of 1 will cause the WLF file to be deleted.; The default is 0 (do not delete WLF file when simulation ends).; WLFDeleteOnQuit = 1; Specify whether or not a WLF file should be optimized during; simulation. If set to 0, the WLF file will not be optimized.; The default is 1, optimize the WLF file.; WLFOptimize = 0; Specify the name of the WLF file.; The default is vsim.wlf; WLFFilename = vsim.wlf; WLF reader cache size limit. Specifies the internal WLF file cache size,; in megabytes, for EACH open WLF file. A value of 0 turns off the; WLF cache.; The default setting is enabled to 256M per open WLF file.; WLFCacheSize = 1000; Specify the WLF file event collapse mode.; 0 = Preserve all events and event order. (same as -wlfnocollapse); 1 = Only record values of logged objects at the end of a simulator iteration.; (same as -wlfcollapsedelta); 2 = Only record values of logged objects at the end of a simulator time step.; (same as -wlfcollapsetime); The default is 1.; WLFCollapseMode = 0; Turn on/off undebuggable SystemC type warnings. Default is on.; ShowUndebuggableScTypeWarning = 0; Turn on/off unassociated SystemC name warnings. Default is off.; ShowUnassociatedScNameWarning = 1; Set SystemC default time unit.; Set to fs, ps, ns, us, ms, or sec with optional; prefix of 1, 10, or 100. The default is 1 ns.; The ScTimeUnit value is honored if it is coarser than Resolution.; If ScTimeUnit is finer than Resolution, it is set to the value; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,; then the default time unit will be 1 ns. However if Resolution; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.ScTimeUnit = ns; Set the SCV relationship name that will be used to identify phase; relations. If the name given to a transactor relation matches this; name, the transactions involved will be treated as phase transactionsScvPhaseRelationName = mti_phase; Customize the vsim kernel shutdown behavior at the end of the simulation.; Some common causes of the end of simulation are $finish (implicit or explicit),; sc_stop(), tf_dofinish(), and assertion failures.; This should be set to "ask", "exit", or "stop". The default is "ask".; "ask" -- In batch mode, the vsim kernel will abruptly exit.; In GUI mode, a dialog box will pop up and ask for user confirmation; whether or not to quit the simulation.; "stop" -- Cause the simulation to stay loaded in memory. This can make some; post-simulation tasks easier.; "exit" -- The simulation will abruptly exit without asking for any confirmation.; Note: these ini variables can be overriden by the vsim command; line switch "-onfinish <ask|stop|exit>".OnFinish = ask; Print "simstats" result at the end of simulation before shutdown.; If this is enabled, the simstats result will be printed out before shutdown.; The default is off.; PrintSimStats = 1; Run simulator in assertion debug mode. Default is off.; AssertionDebug = 1; Turn on/off PSL/SVA concurrent assertion pass enable. Default is on.; AssertionPassEnable = 0; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.; AssertionFailEnable = 0; Set PSL/SVA concurrent assertion pass limit. Default is -1.; Any positive integer, -1 for infinity.; AssertionPassLimit = 1; Set PSL/SVA concurrent assertion fail limit. Default is -1.; Any positive integer, -1 for infinity.; AssertionFailLimit = 1; Turn on/off PSL concurrent assertion pass log. Default is off.; The flag does not affect SVA; AssertionPassLog = 1; Turn on/off PSL concurrent assertion fail log. Default is on.; The flag does not affect SVA; AssertionFailLog = 0; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.; 0 = Continue 1 = Break 2 = Exit; AssertionFailAction = 1; Turn on/off code coverage; CodeCoverage = 0; Count all code coverage condition and expression truth table rows that match.; CoverCountAll = 1; Turn on/off all PSL/SVA cover directive enables. Default is on.; CoverEnable = 0; Turn on/off PSL/SVA cover log. Default is off.; CoverLog = 1; Set "at_least" value for all PSL/SVA cover directives. Default is 1.; CoverAtLeast = 2; Set "limit" value for all PSL/SVA cover directives. Default is -1.; Any positive integer, -1 for infinity.; CoverLimit = 1; Specify the coverage database filename. Default is "" (i.e. database is NOT automatically saved on close).; UCDBFilename = vsim.ucdb; Specify the maximum limit for the number of Cross (bin) products reported; in XML and UCDB report against a Cross. A warning is issued if the limit; is crossed.; MaxReportRhsSVCrossProducts = 1000; Specify the override for the "auto_bin_max" option for the Covergroups.; If not specified then value from Covergroup "option" is used.; SVCoverpointAutoBinMax = 64; Specify the override for the value of "cross_num_print_missing"; option for the Cross in Covergroups. If not specified then value; specified in the "option.cross_num_print_missing" is used. This; is a runtime option. NOTE: This overrides any "cross_num_print_missing"; value specified by user in source file and any SVCrossNumPrintMissingDefault; specified in modelsim.ini.; SVCrossNumPrintMissing = 0; Specify the override for the value of "strobe" option for the; Covergroup Type. If not specified then value in "type_option.strobe"; will be used. This is runtime option which forces "strobe" to; user specified value and supersedes user specified values in the; SystemVerilog Code. NOTE: This also overrides the compile time; default value override specified using "SVCovergroupStrobeDefault"; SVCovergroupStrobe = 0; Override for explicit assignments in source code to "option.goal" of; SystemVerilog covergroup, coverpoint, and cross. It also overrides the; default value of "option.goal" (defined to be 100 in the SystemVerilog; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".; SVCovergroupGoal = 100; Override for explicit assignments in source code to "type_option.goal" of; SystemVerilog covergroup, coverpoint, and cross. It also overrides the; default value of "type_option.goal" (defined to be 100 in the SystemVerilog; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".; SVCovergroupTypeGoal = 100; Specify the maximum number of Coverpoint bins in whole design for; all Covergroups.; MaxSVCoverpointBinsDesign = 2147483648; Specify maximum number of Coverpoint bins in any instance of a Covergroup; MaxSVCoverpointBinsInst = 2147483648; Specify the maximum number of Cross bins in whole design for; all Covergroups.; MaxSVCrossBinsDesign = 2147483648; Specify maximum number of Cross bins in any instance of a Covergroup; MaxSVCrossBinsInst = 2147483648; Set weight for all PSL/SVA cover directives. Default is 1.; CoverWeight = 2; Check vsim plusargs. Default is 0 (off).; 0 = Don't check plusargs; 1 = Warning on unrecognized plusarg; 2 = Error and exit on unrecognized plusarg; CheckPlusargs = 1; Load the specified shared objects with the RTLD_GLOBAL flag.; This gives global visibility to all symbols in the shared objects,; meaning that subsequently loaded shared objects can bind to symbols; in the global shared objects. The list of shared objects should; be whitespace delimited. This option is not supported on the; Windows or AIX platforms.; GlobalSharedObjectList = example1.so example2.so example3.so; Run the 0in tools from within the simulator.; Default value set to 0. Please set it to 1 to invoke 0in.; VsimZeroIn = 1; Set the options to be passed to the 0in tools.; Default value set to "". Please set it to appropriate options needed.; VsimZeroInOptions = ""; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).; Sv_Seed = 0; Maximum size of dynamic arrays that are resized during randomize().; The default is 1000. A value of 0 indicates no limit.; SolveArrayResizeMax = 1000; Error message severity when randomize() failure is detected (SystemVerilog).; The default is 0 (no error).; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal; SolveFailSeverity = 0; Enable/disable debug information for randomize() failures (SystemVerilog).; The default is 0 (disabled). Set to 1 to enable.; SolveFailDebug = 0; When SolveFailDebug is enabled, this value specifies the algorithm used to; discover conflicts between constraints for randomize() failures.; The default is "many".;; Valid schemes are:; "many" = best for determining conflicts due to many related constraints; "few" = best for determining conflicts due to few related constraints;; SolveFailDebugScheme = many; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value; specifies the maximum number of constraint subsets that will be tested for; conflicts.; The default is 0 (no limit).; SolveFailDebugLimit = 0; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value; specifies the maximum size of constraint subsets that will be tested for; conflicts.; The default value is 0 (no limit).; SolveFailDebugMaxSet = 0; Maximum size of the solution graph that may be generated during randomize().; This value can be used to force randomize() to abort if the complexity of; the constraint scenario (both in memory and time spent during evaluation); exceeds the specified limit. This value is specified in 1000s of nodes.; The default is 10000. A value of 0 indicates no limit.; SolveGraphMaxSize = 10000; Use SolveFlags to specify options that will guide the behavior of the; constraint solver. These options may improve the performance of the; constraint solver for some testcases, and decrease the performance of; the constraint solver for others.; The default value is "" (no options).;; Valid flags are:; i = disable bit interleaving for >, >=, <, <= constraints; r = reverse bit interleaving;; SolveFlags =; Specify random sequence compatiblity with a prior letter release. This; option is used to get the same random sequences during simulation as; as a prior letter release. Only prior letter releases (of the current; number release) are allowed.; Note: To achieve the same random sequences, solver optimizations and/or; bug fixes introduced since the specified release may be disabled -; yielding the performance / behavior of the prior release.; Default value set to "" (random compatibility not required).; SolveRev =; Environment variable expansion of command line arguments has been depricated; in favor shell level expansion. Universal environment variable expansion; inside -f files is support and continued support for MGC Location Maps provide; alternative methods for handling flexible pathnames.; The following line may be uncommented and the value set to 1 to re-enable this; deprecated behavior. The default value is 0.; DeprecatedEnvironmentVariableExpansion = 0; Retroactive Recording uses a limited number of private data channels in the WLF; file. Too many channels degrade WLF performance. If the limit is reached,; simulation ends with a fatal error. You may change this limit as needed, but be; aware of the implications of too many channels. The value must be an integer; greater than or equal to zero, where zero disables all retroactive recording.; RetroChannelLimit = 20; Options to give vopt when code coverage is turned on.; Default is "+acc=lprnb -opt=-merge -opt=-suppressAlways"; VoptCoverageOptions = +acc=lprnb -opt=-merge -opt=-suppressAlways; Turn on/off collapsing of bus ports in VCD dumpports outputDumpportsCollapse = 0PrintRandomizeStats = Error reading variable from kernel[lmc]; The simulator's interface to Logic Modeling's SmartModel SWIFT softwarelibsm = $MODEL_TECH/libsm.sl; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT); libsm = $MODEL_TECH/libsm.dll; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700); libswift = $LMC_HOME/lib/hp700.lib/libswift.sl; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000); libswift = $LMC_HOME/lib/ibmrs.lib/swift.o; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris); libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so; Logic Modeling's SmartModel SWIFT software (Windows NT); libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux); libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux); libswift = $LMC_HOME/lib/linux.lib/libswift.so; The simulator's interface to Logic Modeling's hardware modeler SFI softwarelibhm = $MODEL_TECH/libhm.sl; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT); libhm = $MODEL_TECH/libhm.dll; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700); libsfi = <sfi_dir>/lib/hp700/libsfi.sl; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000); libsfi = <sfi_dir>/lib/rs6000/libsfi.a; Logic Modeling's hardware modeler SFI software (Sun4 Solaris); libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so; Logic Modeling's hardware modeler SFI software (Windows NT); libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll; Logic Modeling's hardware modeler SFI software (Linux); libsfi = <sfi_dir>/lib/linux/libsfi.so[msg_system]; Change a message severity or suppress a message.; The format is: <msg directive> = <msg number>[,<msg number>...]; Examples:; note = 3009; warning = 3033; error = 3010,3016; fatal = 3016,3033; suppress = 3009,3016,3043; The command verror <msg number> can be used to get the complete; description of a message.; Control transcripting of elaboration/runtime messages.; The default is to have messages appear in the transcript and; recorded in the wlf file (messages that are recorded in the; wlf file can be viewed in the MsgViewer). The other settings; are to send messages only to the transcript or only to the; wlf file. The valid values are; both {default}; tran {transcript only}; wlf {wlf file only}; msgmode = both[Project]Project_Version = 6Project_DefaultLib = workProject_SortMethod = unusedProject_Files_Count = 10Project_File_0 = C:/D/newGS/develop/fpgaE_dma/dma/modelsim/T80_MCode.vhdProject_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1113251578 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 1 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002Project_File_1 = C:/D/newGS/develop/fpgaE_dma/dma/modelsim/T80.vhdProject_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1114718640 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 1 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2002Project_File_2 = C:/D/newGS/develop/fpgaE_dma/dma/modelsim/tb_dma1.vProject_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1223216485 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0Project_File_3 = C:/D/newGS/develop/fpgaE_dma/dma/modelsim/ram.vProject_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 last_compile 1220565008 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0Project_File_4 = C:/D/newGS/develop/fpgaE_dma/dma/modelsim/T80_RegX.vhdProject_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1113244614 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 1 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002Project_File_5 = C:/D/newGS/develop/fpgaE_dma/dma/modelsim/T80_Reg.vhdProject_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1113244618 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 1 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002Project_File_6 = C:/D/newGS/develop/fpgaE_dma/dma/modelsim/T80_ALU.vhdProject_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1158725894 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 1 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002Project_File_7 = C:/D/newGS/develop/fpgaE_dma/dma/modelsim/T80a.vhdProject_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1113244616 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 1 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002Project_File_8 = C:/D/newGS/develop/fpgaE_dma/dma/modelsim/T80_Pack.vhdProject_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1113244618 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 1 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002Project_File_9 = C:/D/newGS/develop/fpgaE_dma/dma/modelsim/rom.vProject_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1220565674 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0Project_Sim_Count = 0Project_Folder_Count = 0Echo_Compile_Output = 0Save_Compile_Report = 1Project_Opt_Count = 0ForceSoftPaths = 0ReOpenSourceFiles = 1VERILOG_DoubleClick = EditVERILOG_CustomDoubleClick =VHDL_DoubleClick = EditVHDL_CustomDoubleClick =PSL_DoubleClick = EditPSL_CustomDoubleClick =TEXT_DoubleClick = EditTEXT_CustomDoubleClick =SYSTEMC_DoubleClick = EditSYSTEMC_CustomDoubleClick =TCL_DoubleClick = EditTCL_CustomDoubleClick =MACRO_DoubleClick = EditMACRO_CustomDoubleClick =VCD_DoubleClick = EditVCD_CustomDoubleClick =SDF_DoubleClick = EditSDF_CustomDoubleClick =XML_DoubleClick = EditXML_CustomDoubleClick =LOGFILE_DoubleClick = EditLOGFILE_CustomDoubleClick =EditorState = {tabbed horizontal 1} {C:/D/newGS/develop/fpgaE_dma/dma/modelsim/tb_dma1.v 0 0} {C:/D/newGS/develop/fpgaE_dma/dma/modelsim/tb_dma1.do 0 1}Project_Major_Version = 6Project_Minor_Version = 2