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  1. // ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
  2. //
  3. // reset generator
  4.  
  5. /*
  6.     This file is part of ZX-Evo Base Configuration firmware.
  7.  
  8.     ZX-Evo Base Configuration firmware is free software:
  9.     you can redistribute it and/or modify it under the terms of
  10.     the GNU General Public License as published by
  11.     the Free Software Foundation, either version 3 of the License, or
  12.     (at your option) any later version.
  13.  
  14.     ZX-Evo Base Configuration firmware is distributed in the hope that
  15.     it will be useful, but WITHOUT ANY WARRANTY; without even
  16.     the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  17.     See the GNU General Public License for more details.
  18.  
  19.     You should have received a copy of the GNU General Public License
  20.     along with ZX-Evo Base Configuration firmware.
  21.     If not, see <http://www.gnu.org/licenses/>.
  22. */
  23.  
  24. `include "../include/tune.v"
  25.  
  26. module resetter(
  27.  
  28.         clk,
  29.  
  30.         rst_in_n,
  31.  
  32.         rst_out_n );
  33.  
  34. parameter RST_CNT_SIZE = 4;
  35.  
  36.  
  37.         input clk;
  38.  
  39.         input rst_in_n; // input of external asynchronous reset
  40.  
  41.         output rst_out_n; // output of end-synchronized reset (beginning is asynchronous to clock)
  42.         reg    rst_out_n;
  43.  
  44.  
  45.  
  46.         reg [RST_CNT_SIZE:0] rst_cnt; // one bit more for counter stopping
  47.  
  48.         reg rst1_n,rst2_n;
  49.  
  50.  
  51.  
  52. `ifdef SIMULATE
  53.         initial
  54.         begin
  55.                 rst_cnt = 0;
  56.                 rst1_n = 1'b0;
  57.                 rst2_n = 1'b0;
  58.                 rst_out_n = 1'b0;
  59.         end
  60. `endif
  61.  
  62.  
  63.         always @(posedge clk, negedge rst_in_n)
  64.         if( !rst_in_n ) // external asynchronous reset
  65.         begin
  66.                 rst_cnt <= 0;
  67.                 rst1_n <= 1'b0;
  68.                 rst2_n <= 1'b0;
  69.                 rst_out_n <= 1'b0; // this zeroing also happens after FPGA configuration, so also power-up reset happens
  70.         end
  71.         else // clocking
  72.         begin
  73.                 rst1_n <= 1'b1;
  74.                 rst2_n <= rst1_n;
  75.  
  76.                 if( rst2_n && !rst_cnt[RST_CNT_SIZE] )
  77.                 begin
  78.                         rst_cnt <= rst_cnt + 1;
  79.                 end
  80.  
  81.                 if( rst_cnt[RST_CNT_SIZE] )
  82.                 begin
  83.                         rst_out_n <= 1'b1;
  84.                 end
  85.         end
  86.  
  87.  
  88. endmodule
  89.  
  90.