Subversion Repositories pentevo

Rev

Rev 896 | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. // ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
  2. //
  3. // generates horizontal vga sync, double the rate of TV horizontal sync
  4.  
  5. /*
  6.     This file is part of ZX-Evo Base Configuration firmware.
  7.  
  8.     ZX-Evo Base Configuration firmware is free software:
  9.     you can redistribute it and/or modify it under the terms of
  10.     the GNU General Public License as published by
  11.     the Free Software Foundation, either version 3 of the License, or
  12.     (at your option) any later version.
  13.  
  14.     ZX-Evo Base Configuration firmware is distributed in the hope that
  15.     it will be useful, but WITHOUT ANY WARRANTY; without even
  16.     the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  17.     See the GNU General Public License for more details.
  18.  
  19.     You should have received a copy of the GNU General Public License
  20.     along with ZX-Evo Base Configuration firmware.
  21.     If not, see <http://www.gnu.org/licenses/>.
  22. */
  23.  
  24. `include "../include/tune.v"
  25.  
  26. module video_vga_sync_h(
  27.  
  28.         input  wire clk,
  29.  
  30.         input  wire [1:0] modes_raster,
  31.  
  32.         output reg  vga_hsync,
  33.  
  34.         output reg  scanout_start,
  35.  
  36.         input  wire hsync_start
  37. );
  38.  
  39.         localparam HSYNC_END    = 10'd106;
  40.         localparam SCANOUT_BEG  = 10'd156;
  41.  
  42.         localparam HPERIOD_224 = 10'd896;
  43.         localparam HPERIOD_228 = 10'd912;
  44.  
  45.  
  46.  
  47.         reg [9:0] hcount;
  48.  
  49.         initial
  50.         begin
  51.                 hcount = 9'd0;
  52.                 vga_hsync = 1'b0;
  53.         end
  54.  
  55.  
  56.  
  57.         always @(posedge clk)
  58.         begin
  59.                         if( hsync_start )
  60.                                 hcount <= 10'd2;
  61.                         else if ( hcount==( (modes_raster==2'b11) ? (HPERIOD_228-10'd1) : (HPERIOD_224-10'd1) ) )
  62.                                 hcount <= 10'd0;
  63.                         else
  64.                                 hcount <= hcount + 9'd1;
  65.         end
  66.  
  67.  
  68.         always @(posedge clk)
  69.         begin
  70.                 if( !hcount )
  71.                         vga_hsync <= 1'b1;
  72.                 else if( hcount==HSYNC_END )
  73.                         vga_hsync <= 1'b0;
  74.         end
  75.  
  76.  
  77.         always @(posedge clk)
  78.         begin
  79.                 if( hcount==SCANOUT_BEG )
  80.                         scanout_start <= 1'b1;
  81.                 else
  82.                         scanout_start <= 1'b0;
  83.         end
  84.  
  85.  
  86. endmodule
  87.  
  88.