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  1. // ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
  2. //
  3. // counter-based 'PFD', based on pentagon design, with filter and adopted to
  4. // 28mhz
  5.  
  6. /*
  7.     This file is part of ZX-Evo Base Configuration firmware.
  8.  
  9.     ZX-Evo Base Configuration firmware is free software:
  10.     you can redistribute it and/or modify it under the terms of
  11.     the GNU General Public License as published by
  12.     the Free Software Foundation, either version 3 of the License, or
  13.     (at your option) any later version.
  14.  
  15.     ZX-Evo Base Configuration firmware is distributed in the hope that
  16.     it will be useful, but WITHOUT ANY WARRANTY; without even
  17.     the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  18.     See the GNU General Public License for more details.
  19.  
  20.     You should have received a copy of the GNU General Public License
  21.     along with ZX-Evo Base Configuration firmware.
  22.     If not, see <http://www.gnu.org/licenses/>.
  23. */
  24.  
  25.  
  26. module fapch_counter
  27. (
  28.         input  wire fclk,
  29.  
  30.         input  wire rdat_n,
  31.  
  32.         output reg  vg_rclk,
  33.         output reg  vg_rawr
  34. );
  35.  
  36.  
  37.         reg [4:0] rdat_sync;
  38.         reg rdat_edge1, rdat_edge2;
  39.         wire rdat;
  40.         wire rwidth_ena;
  41.         reg [3:0] rwidth_cnt;
  42.         wire rclk_strobe;
  43.         reg [5:0] rclk_cnt;
  44.  
  45.         // RCLK/RAWR restore
  46.         // currently simplest counter method, no PLL whatsoever now
  47.         //
  48.         // RCLK period must be 112 clocks (@28 MHz), or 56 clocks for each state
  49.         // RAWR on time is 4 clocks
  50.  
  51.         // digital filter - removing glitches
  52.         always @(posedge fclk)
  53.                 rdat_sync[4:0] <= { rdat_sync[3:0], (~rdat_n) };
  54.  
  55.  
  56.  
  57.         always @(posedge fclk)
  58.         begin
  59.                 if( rdat_sync[4:1]==4'b1111 ) // filter beginning of strobe
  60.                         rdat_edge1 <= 1'b1;
  61.                 else if( rclk_strobe ) // filter any more strobes during same strobe half-perion
  62.                         rdat_edge1 <= 1'b0;
  63.  
  64.                 rdat_edge2 <= rdat_edge1;
  65.         end
  66.  
  67.  
  68.  
  69.         assign rdat = rdat_edge1 & (~rdat_edge2);
  70.  
  71.  
  72.  
  73.         always @(posedge fclk)
  74.                 if( rwidth_ena )
  75.                 begin
  76.                         if( rdat )
  77.                                 rwidth_cnt <= 4'd0;
  78.                         else
  79.                                 rwidth_cnt <= rwidth_cnt + 4'd1;
  80.                 end
  81.  
  82.         assign rwidth_ena = rdat | (~rwidth_cnt[2]); // [2] - 140ns, [3] - 280ns
  83.  
  84.         always @(posedge fclk)
  85.                 vg_rawr <= rwidth_cnt[2]; // RAWR has 2 clocks latency from rdat strobe
  86.  
  87.  
  88.  
  89.  
  90.         assign rclk_strobe = (rclk_cnt==6'd0);
  91.  
  92.         always @(posedge fclk)
  93.         begin
  94.                 if( rdat )
  95.                         rclk_cnt <= 6'd29; // (56/2)-1 plus halfwidth of RAWR
  96.                 else if( rclk_strobe )
  97.                         rclk_cnt <= 6'd55; // period is 56 clocks
  98.                 else
  99.                         rclk_cnt <= rclk_cnt - 6'd1;
  100.         end
  101.  
  102.         always @(posedge fclk)
  103.                 if( rclk_strobe )
  104.                         vg_rclk <= ~vg_rclk; // vg_rclk latency is 2 clocks plus a number loaded into rclk_cnt at rdat strobe
  105.  
  106. endmodule
  107.  
  108.