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Project Information c:\111\cpld_zc\zcont.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 03/14/2008 20:21:48
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
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megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Zcont
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
zcont EPM7128SLC84-6 36 10 11 126 73 98 %
User Pins: 36 10 11
Project Information c:\111\cpld_zc\zcont.rpt
** PROJECT COMPILATION MESSAGES **
Warning: GLOBAL primitive on node 'restrig' feeds logic -- non-global signal usage may result
Warning: GLOBAL primitive on node 'strobe' feeds logic -- non-global signal usage may result
Warning: TRI or OPNDRN buffer 'nmib' is permanently disabled
Info: Reserved unused input pin 'adr3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'adr4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Project Information c:\111\cpld_zc\zcont.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'strobe' chosen for auto global Clock
INFO: Signal 'restrig' chosen for auto global Clear
Project Information c:\111\cpld_zc\zcont.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
zcont@84 adr0
zcont@4 adr1
zcont@5 adr2
zcont@8 adr3
zcont@16 adr4
zcont@21 adr5
zcont@18 adr6
zcont@58 adr7
zcont@24 a8
zcont@27 a9
zcont@22 a10
zcont@29 a11
zcont@74 a12
zcont@76 a13
zcont@73 a14
zcont@70 a15
zcont@56 data0
zcont@49 data1
zcont@48 data2
zcont@33 data3
zcont@50 data4
zcont@46 data5
zcont@35 data6
zcont@34 data7
zcont@79 dbus0
zcont@68 dbus1
zcont@80 dbus2
zcont@6 dbus3
zcont@9 dbus4
zcont@10 dbus5
zcont@69 dbus6
zcont@67 dbus7
zcont@77 dos
zcont@39 ebl
zcont@41 ior
zcont@12 iorq
zcont@36 iorqce
zcont@44 iow
zcont@51 magic0
zcont@52 magic1
zcont@15 m1
zcont@25 nmi
zcont@11 rd
zcont@45 rdh
zcont@17 readonly
zcont@55 reso
zcont@1 restrig
zcont@28 sdabsent
zcont@31 sdcs
zcont@20 sddatain
zcont@37 sddatao
zcont@40 sdpower
zcont@2 sdtakt
zcont@64 sdtakto
zcont@83 strobe
zcont@30 wr
zcont@54 wrh
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
***** Logic for device 'zcont' compiled without errors.
Device: EPM7128SLC84-6
Device Options:
Turbo Bit = OFF
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** ERROR SUMMARY **
Info: Chip 'zcont' in device 'EPM7128SLC84-6' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
Info: Chip 'zcont' in device 'EPM7128SLC84-6' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R R
r E E
V s e s S S
d d d C d s t E d d V E
b b a b a a C t t a r R b b C R
u u d G u d d I a r d o G V u u C d a V
r s s r N s r r N k i r b N E s s I o 1 E
d 5 4 3 D 3 2 1 T t g 0 e D D 2 0 O s 3 D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
iorq | 12 74 | a12
VCCIO | 13 73 | a14
#TDI | 14 72 | GND
m1 | 15 71 | #TDO
adr4 | 16 70 | a15
readonly | 17 69 | dbus6
adr6 | 18 68 | dbus1
GND | 19 67 | dbus7
sddatain | 20 66 | VCCIO
adr5 | 21 65 | RESERVED
a10 | 22 EPM7128SLC84-6 64 | sdtakto
#TMS | 23 63 | RESERVED
a8 | 24 62 | #TCK
nmi | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
a9 | 27 59 | GND
sdabsent | 28 58 | adr7
a11 | 29 57 | RESERVED
wr | 30 56 | data0
sdcs | 31 55 | reso
GND | 32 54 | wrh
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
d d d i s V e s i G V i r d G d d d m m V
a a a o d C b d o N C o d a N a a a a a C
t t t r d C l p r D C w h t D t t t g g C
a a a q a I o I a a a a i i I
3 7 6 c t O w N 5 2 1 4 c c O
e a e T 0 1
o r
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 16/16(100%) 8/ 8(100%) 7/16( 43%) 34/36( 94%)
B: LC17 - LC32 15/16( 93%) 8/ 8(100%) 12/16( 75%) 35/36( 97%)
C: LC33 - LC48 16/16(100%) 8/ 8(100%) 16/16(100%) 28/36( 77%)
D: LC49 - LC64 16/16(100%) 8/ 8(100%) 16/16(100%) 34/36( 94%)
E: LC65 - LC80 16/16(100%) 8/ 8(100%) 4/16( 25%) 35/36( 97%)
F: LC81 - LC96 16/16(100%) 5/ 8( 62%) 6/16( 37%) 35/36( 97%)
G: LC97 - LC112 15/16( 93%) 6/ 8( 75%) 9/16( 56%) 35/36( 97%)
H: LC113 - LC128 16/16(100%) 6/ 8( 75%) 16/16(100%) 35/36( 97%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 57/64 ( 89%)
Total logic cells used: 126/128 ( 98%)
Total shareable expanders used: 73/128 ( 57%)
Total Turbo logic cells used: 0/128 ( 0%)
Total shareable expanders not available (n/a): 13/128 ( 10%)
Average fan-in: 5.32
Total fan-in: 671
Total input pins required: 36
Total fast input logic cells required: 0
Total output pins required: 10
Total bidirectional pins required: 11
Total reserved pins required 4
Total logic cells required: 126
Total flipflops required: 94
Total product terms required: 367
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 70
Synthesized logic cells: 14/ 128 ( 10%)
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
84 - - INPUT 0 0 0 0 0 16 13 adr0
4 (16) (A) INPUT 0 0 0 0 0 17 13 adr1
5 (14) (A) INPUT 0 0 0 0 0 6 3 adr2
8 (11) (A) INPUT 0 0 0 0 0 0 0 adr3
16 (27) (B) INPUT 0 0 0 0 0 0 0 adr4
21 (19) (B) INPUT 0 0 0 0 0 12 14 adr5
18 (24) (B) INPUT 0 0 0 0 0 12 12 adr6
58 (91) (F) INPUT 0 0 0 0 0 12 14 adr7
24 (46) (C) INPUT 0 0 0 0 0 8 5 a8
27 (43) (C) INPUT 0 0 0 0 0 0 5 a9
22 (17) (B) INPUT 0 0 0 0 0 8 5 a10
29 (38) (C) INPUT 0 0 0 0 0 0 5 a11
74 (117) (H) INPUT 0 0 0 0 0 0 5 a12
76 (120) (H) INPUT 0 0 0 0 0 0 5 a13
73 (115) (H) INPUT 0 0 0 0 0 0 5 a14
70 (109) (G) INPUT 0 0 0 0 0 3 4 a15
56 (86) (F) INPUT 0 0 0 0 0 1 8 data0
49 (73) (E) INPUT 0 0 0 0 0 0 8 data1
48 (72) (E) INPUT 0 0 0 0 0 0 8 data2
33 (64) (D) INPUT 0 0 0 0 0 0 7 data3
50 (75) (E) INPUT 0 0 0 0 0 0 7 data4
46 (69) (E) INPUT 0 0 0 0 0 0 7 data5
35 (59) (D) INPUT 0 0 0 0 0 0 7 data6
34 (61) (D) INPUT 0 0 0 0 0 0 7 data7
79 125 H BIDIR 6 1 0 11 6 1 1 dbus0
68 105 G BIDIR 6 1 0 11 6 1 1 dbus1
80 126 H BIDIR 3 0 1 11 6 0 1 dbus2
6 13 A BIDIR 3 0 1 11 6 0 1 dbus3
9 8 A BIDIR 3 0 1 11 6 0 1 dbus4
10 6 A BIDIR 1 0 1 10 3 0 1 dbus5
69 107 G BIDIR 1 0 1 10 3 0 1 dbus6
67 104 G BIDIR 1 0 1 10 3 1 0 dbus7
77 (123) (H) INPUT 0 0 0 0 0 17 12 dos
12 (3) (A) INPUT 0 0 0 0 0 15 12 iorq
36 57 D BIDIR 0 0 0 9 0 0 0 iorqce
51 (77) (E) INPUT 0 0 0 0 0 1 0 magic0
15 (29) (B) INPUT 0 0 0 0 0 6 3 m1
25 45 C BIDIR 0 0 0 0 0 0 0 nmi
11 (5) (A) INPUT 0 0 0 0 0 13 5 rd
17 (25) (B) INPUT 0 0 0 0 0 1 0 readonly
55 85 F BIDIR 0 0 0 2 0 2 0 reso
1 - - INPUT G 0 0 0 0 0 2 1 restrig
28 (40) (C) INPUT 0 0 0 0 0 1 0 sdabsent
20 (21) (B) INPUT 0 0 0 0 0 0 1 sddatain
2 - - INPUT 0 0 0 0 0 2 20 sdtakt
83 - - INPUT G 0 0 0 0 0 1 1 strobe
30 (37) (C) INPUT 0 0 0 0 0 7 11 wr
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
79 125 H TRI / 6 1 0 11 6 1 1 dbus0
68 105 G TRI / 6 1 0 11 6 1 1 dbus1
80 126 H TRI / 3 0 1 11 6 0 1 dbus2
6 13 A TRI / 3 0 1 11 6 0 1 dbus3
9 8 A TRI / 3 0 1 11 6 0 1 dbus4
10 6 A TRI / 1 0 1 10 3 0 1 dbus5
69 107 G TRI / 1 0 1 10 3 0 1 dbus6
67 104 G TRI / 1 0 1 10 3 1 0 dbus7
39 53 D OUTPUT / 0 0 0 4 0 0 0 ebl
41 49 D OUTPUT / 0 0 0 8 0 0 0 ior
36 57 D TRI / 0 0 0 9 0 0 0 iorqce
44 65 E OUTPUT / 0 0 0 8 0 0 0 iow
52 80 E OUTPUT / 0 0 0 3 0 0 0 magic1
25 45 C TRI / 0 0 0 0 0 0 0 nmi
45 67 E OUTPUT / 0 0 0 8 0 0 0 rdh
55 85 F TRI / 0 0 0 2 0 2 0 reso
31 35 C FF / 0 0 0 8 2 0 0 sdcs
37 56 D FF / 14 14 0 9 6 0 0 sddatao
40 51 D FF /! 0 0 0 8 2 0 0 sdpower
64 99 G OUTPUT / 0 0 0 1 2 0 0 sdtakto
54 83 F OUTPUT / 0 0 0 8 0 0 0 wrh
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 113 H DFFE + 0 0 0 0 1 0 9 counter0
- 81 F DFFE + 0 0 0 0 1 0 9 counter1
(14) 32 B DFFE + 0 0 0 0 1 0 9 counter2
(63) 97 G DFFE + 0 0 0 0 1 0 9 counter3
(16) 27 B DFFE + 0 0 0 0 1 0 9 counter4
(17) 25 B DFFE + 0 0 0 0 1 0 9 counter5
(20) 21 B DFFE + 0 0 0 0 1 0 9 counter6
- 82 F DFFE + 0 0 0 0 1 0 4 counter7
(73) 115 H SOFT s 7 1 0 10 0 0 0 dbus7~1
(33) 64 D SOFT s 1 0 1 7 0 0 1 iorqcc~1
(30) 37 C SOFT s 14 1 0 9 1 0 0 iorqce~1
- 10 A DFFE 0 0 0 1 1 0 1 keyd00
(62) 96 F DFFE 0 0 0 1 1 0 1 keyd01
(61) 94 F DFFE 0 0 0 1 1 0 1 keyd02
- 106 G DFFE 0 0 0 1 1 0 1 keyd03
(12) 3 A DFFE 0 0 0 1 1 0 1 keyd04
- 4 A DFFE 0 0 0 1 1 0 1 keyd05
- 2 A DFFE 0 0 0 1 1 0 1 keyd06
- 102 G DFFE 0 0 0 1 1 0 1 keyd07
- 23 B DFFE 0 0 0 1 1 0 1 keyd10
(24) 46 C DFFE 0 0 0 1 1 0 1 keyd11
- 47 C DFFE 0 0 0 1 1 0 1 keyd12
- 78 E DFFE 0 0 0 1 1 0 1 keyd13
(49) 73 E DFFE 0 0 0 1 1 0 1 keyd14
(46) 69 E DFFE 0 0 0 1 1 0 1 keyd15
- 31 B DFFE 0 0 0 1 1 0 1 keyd16
(27) 43 C DFFE 0 0 0 1 1 0 1 keyd17
(50) 75 E DFFE 0 0 0 1 1 0 1 keyd20
(60) 93 F DFFE 0 0 0 1 1 0 1 keyd21
- 95 F DFFE 0 0 0 1 1 0 1 keyd22
- 74 E DFFE 0 0 0 1 1 0 1 keyd23
- 66 E DFFE 0 0 0 1 1 0 1 keyd24
- 76 E DFFE 0 0 0 1 1 0 1 keyd25
(56) 86 F DFFE 0 0 0 1 1 0 1 keyd26
- 103 G DFFE 0 0 0 1 1 1 0 keyd27
- 26 B DFFE 0 0 0 1 1 0 1 keyd30
- 33 C DFFE 0 0 0 1 1 0 1 keyd31
(23) 48 C DFFE 0 0 0 1 1 0 1 keyd32
- 36 C DFFE 0 0 0 1 1 0 1 keyd33
- 15 A DFFE 0 0 0 1 1 0 1 keyd34
- 7 A DFFE 0 0 0 1 1 0 1 keyd35
(22) 17 B DFFE 0 0 0 1 1 0 1 keyd36
- 39 C DFFE 0 0 0 1 1 1 1 keyd37
(18) 24 B DFFE 0 0 0 1 1 0 1 keyd40
(75) 118 H DFFE 0 0 0 1 1 0 1 keyd41
- 116 H DFFE 0 0 0 1 1 0 1 keyd42
- 119 H DFFE 0 0 0 1 1 0 1 keyd43
- 9 A DFFE 0 0 0 1 1 0 1 keyd44
- 1 A DFFE 0 0 0 1 1 0 1 keyd45
(11) 5 A DFFE 0 0 0 1 1 0 1 keyd46
- 127 H DFFE 0 0 0 1 1 1 1 keyd47
- 22 B DFFE 0 0 0 1 1 1 0 mousebut0
- 114 H DFFE 0 0 0 1 1 1 0 mousebut1
(76) 120 H DFFE 0 0 0 1 1 1 0 mousebut2
(21) 19 B DFFE 0 0 0 1 1 1 0 mousex0
(74) 117 H DFFE 0 0 0 1 1 1 0 mousex1
- 124 H DFFE 0 0 0 1 1 1 0 mousex2
(81) 128 H DFFE 0 0 0 1 1 1 0 mousex3
(8) 11 A DFFE 0 0 0 1 1 1 0 mousex4
- 12 A DFFE 0 0 0 1 1 1 0 mousex5
(15) 29 B DFFE 0 0 0 1 1 1 0 mousex6
- 122 H DFFE 0 0 0 1 1 1 0 mousex7
- 70 E DFFE 0 0 0 1 1 1 0 mousey0
- 89 F DFFE 0 0 0 1 1 1 0 mousey1
(58) 91 F DFFE 0 0 0 1 1 1 0 mousey2
(48) 72 E DFFE 0 0 0 1 1 1 0 mousey3
- 68 E DFFE 0 0 0 1 1 1 0 mousey4
- 79 E DFFE 0 0 0 1 1 1 0 mousey5
- 92 F DFFE 0 0 0 1 1 1 0 mousey6
- 87 F DFFE 0 0 0 1 1 1 0 mousey7
(57) 88 F SOFT s 0 0 0 2 0 0 0 reso~1
(71) 112 G TFFE 1 1 0 1 3 0 3 sdcounter0
- 100 G TFFE 1 1 0 1 4 0 2 sdcounter1
- 111 G TFFE 1 1 0 1 5 0 1 sdcounter2
(70) 109 G TFFE 1 1 0 1 6 0 5 sdcounter3
- 62 D DFFE 0 0 0 2 2 1 1 sddatard0
(29) 38 C DFFE 0 0 0 1 3 1 1 sddatard1
- 110 G DFFE 0 0 0 1 3 1 1 sddatard2
(65) 101 G DFFE 0 0 0 1 3 1 1 sddatard3
- 71 E DFFE 0 0 0 1 3 1 1 sddatard4
- 42 C DFFE 0 0 0 1 3 1 1 sddatard5
(28) 40 C DFFE 0 0 0 1 3 1 1 sddatard6
- 98 G DFFE 0 0 0 1 3 1 0 sddatard7
- 60 D DFFE 1 0 0 8 4 0 1 sddatawr0
- 63 D DFFE 14 14 0 9 6 0 1 sddatawr1
- 52 D DFFE 14 14 0 9 6 0 1 sddatawr2
- 54 D DFFE 14 14 0 9 6 0 1 sddatawr3
- 58 D DFFE 14 14 0 9 6 0 1 sddatawr4
(35) 59 D DFFE 14 14 0 9 6 0 1 sddatawr5
(34) 61 D DFFE 14 14 0 9 6 1 0 sddatawr6
- 90 F DFFE 2 0 0 9 1 0 1 starttr
- 41 C DFFE 0 0 0 1 2 2 20 starttr1
- 34 C DFFE 1 0 0 9 1 2 23 stoptr
- 55 D DFFE 0 0 0 8 2 1 8 synchrotrig0
- 50 D DFFE 0 0 0 1 1 0 1 synchrotrig1
- 84 F SOFT s 4 0 1 7 7 1 0 ~243~1
(77) 123 H SOFT s 0 0 0 1 1 1 0 ~244~1
(51) 77 E SOFT s 4 0 1 7 7 1 0 ~258~1
- 121 H SOFT s 0 0 0 1 1 1 0 ~259~1
- 30 B SOFT s 4 0 1 7 7 1 0 ~273~1
- 20 B SOFT s 4 0 1 7 7 1 0 ~288~1
(4) 16 A SOFT s 0 0 0 1 1 1 0 ~289~1
- 18 B SOFT s 4 0 1 7 7 1 0 ~303~1
(5) 14 A SOFT s 0 0 0 1 1 1 0 ~304~1
- 44 C SOFT s 1 0 1 4 2 1 6 ~531~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------------- LC13 dbus3
| +----------------------------- LC8 dbus4
| | +--------------------------- LC6 dbus5
| | | +------------------------- LC10 keyd00
| | | | +----------------------- LC3 keyd04
| | | | | +--------------------- LC4 keyd05
| | | | | | +------------------- LC2 keyd06
| | | | | | | +----------------- LC15 keyd34
| | | | | | | | +--------------- LC7 keyd35
| | | | | | | | | +------------- LC9 keyd44
| | | | | | | | | | +----------- LC1 keyd45
| | | | | | | | | | | +--------- LC5 keyd46
| | | | | | | | | | | | +------- LC11 mousex4
| | | | | | | | | | | | | +----- LC12 mousex5
| | | | | | | | | | | | | | +--- LC16 ~289~1
| | | | | | | | | | | | | | | +- LC14 ~304~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC11 -> - * - - - - - - - - - - - - - - | * - - - - - - - | <-- mousex4
LC12 -> - - * - - - - - - - - - - - - - | * - - - - - - - | <-- mousex5
LC16 -> * - - - - - - - - - - - - - - - | * - - - - - - - | <-- ~289~1
LC14 -> - * - - - - - - - - - - - - - - | * - - - - - - - | <-- ~304~1
Pin
84 -> * * * - - - - - - - - - - - - - | * - * * * * * * | <-- adr0
4 -> * * * - - - - - - - - - - - - - | * - * * * * * * | <-- adr1
21 -> * * * - - - - - - - - - - - - - | * - * * - * * * | <-- adr5
18 -> * * * - - - - - - - - - - - - - | * - * * - * * * | <-- adr6
58 -> * * * - - - - - - - - - - - - - | * - * * - * * * | <-- adr7
24 -> * * * - - - - - - - - - - - - - | * * - - * * * * | <-- a8
22 -> * * * - - - - - - - - - - - - - | * * - - * * * * | <-- a10
70 -> * * - - - - - - - - - - - - * * | * - - - - - - * | <-- a15
56 -> - - - * - - - - - - - - - - - - | * * - - * - - - | <-- data0
50 -> - - - - * - - * - * - - * - - - | * - - - * - - - | <-- data4
46 -> - - - - - * - - * - * - - * - - | * - - - * - - - | <-- data5
35 -> - - - - - - * - - - - * - - - - | * * - - - * - - | <-- data6
77 -> * * * - - - - - - - - - - - - - | * - * * * * * * | <-- dos
12 -> * * * - - - - - - - - - - - - - | * - * * * * * * | <-- iorq
11 -> * * * - - - - - - - - - - - - - | * - * * * * * * | <-- rd
1 -> - - - - - - - - - - - - - - - - | - - - - * * - - | <-- restrig
2 -> - - - - - - - - - - - - - - - - | - - * * * - * - | <-- sdtakt
83 -> - - - - - - - - - - - - - - - - | - - - - - * - - | <-- strobe
LC113-> - - - * * * * - - - - - - - - - | * - - - - * * - | <-- counter0
LC97 -> - - - - - - - * * - - - - - - - | * * * - - - - - | <-- counter3
LC27 -> - - - - - - - - - * * * - - - - | * * - - - - - * | <-- counter4
LC25 -> - - - - - - - - - - - - * * - - | * * - - - - - * | <-- counter5
LC39 -> * - - - - - - - - - - - - - * - | * - - - - - - - | <-- keyd37
LC127-> - * - - - - - - - - - - - - - * | * - - - - - - - | <-- keyd47
LC128-> * - - - - - - - - - - - - - - - | * - - - - - - - | <-- mousex3
LC72 -> * - - - - - - - - - - - - - - - | * - - - - - - - | <-- mousey3
LC68 -> - * - - - - - - - - - - - - - - | * - - - - - - - | <-- mousey4
LC79 -> - - * - - - - - - - - - - - - - | * - - - - - - - | <-- mousey5
LC101-> * - - - - - - - - - - - - - - - | * - - - * - - - | <-- sddatard3
LC71 -> - * - - - - - - - - - - - - - - | * - * - - - - - | <-- sddatard4
LC42 -> - - * - - - - - - - - - - - - - | * - * - - - - - | <-- sddatard5
LC20 -> * - - - - - - - - - - - - - - - | * - - - - - - - | <-- ~288~1
LC18 -> - * - - - - - - - - - - - - - - | * - - - - - - - | <-- ~303~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------------- LC32 counter2
| +--------------------------- LC27 counter4
| | +------------------------- LC25 counter5
| | | +----------------------- LC21 counter6
| | | | +--------------------- LC23 keyd10
| | | | | +------------------- LC31 keyd16
| | | | | | +----------------- LC26 keyd30
| | | | | | | +--------------- LC17 keyd36
| | | | | | | | +------------- LC24 keyd40
| | | | | | | | | +----------- LC22 mousebut0
| | | | | | | | | | +--------- LC19 mousex0
| | | | | | | | | | | +------- LC29 mousex6
| | | | | | | | | | | | +----- LC30 ~273~1
| | | | | | | | | | | | | +--- LC20 ~288~1
| | | | | | | | | | | | | | +- LC18 ~303~1
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
LC27 -> - - * - - - - - * - - - - - - | * * - - - - - * | <-- counter4
LC25 -> - - - * - - - - - - * * - - - | * * - - - - - * | <-- counter5
LC26 -> - - - - - - - - - - - - - * - | - * - - - - - - | <-- keyd30
LC17 -> - - - - - - - - - - - - - * - | - * - - - - - - | <-- keyd36
LC24 -> - - - - - - - - - - - - - - * | - * - - - - - - | <-- keyd40
Pin
84 -> - - - - - - - - - - - - - - - | * - * * * * * * | <-- adr0
24 -> - - - - - - - - - - - - * * * | * * - - * * * * | <-- a8
27 -> - - - - - - - - - - - - * * * | - * - - * * - - | <-- a9
22 -> - - - - - - - - - - - - * * * | * * - - * * * * | <-- a10
29 -> - - - - - - - - - - - - * * * | - * - - * * - - | <-- a11
74 -> - - - - - - - - - - - - * * * | - * - - * * - - | <-- a12
76 -> - - - - - - - - - - - - * * * | - * - - * * - - | <-- a13
73 -> - - - - - - - - - - - - * * * | - * - - * * - - | <-- a14
56 -> - - - - * - * - * * * - - - - | * * - - * - - - | <-- data0
35 -> - - - - - * - * - - - * - - - | * * - - - * - - | <-- data6
1 -> - - - - - - - - - - - - - - - | - - - - * * - - | <-- restrig
2 -> - - - - - - - - - - - - - - - | - - * * * - * - | <-- sdtakt
83 -> - - - - - - - - - - - - - - - | - - - - - * - - | <-- strobe
LC81 -> * - - - * * - - - - - - - - - | - * * - * - - - | <-- counter1
LC97 -> - * - - - - * * - - - - - - - | * * * - - - - - | <-- counter3
LC82 -> - - - - - - - - - * - - - - - | - * - - - - - * | <-- counter7
LC75 -> - - - - - - - - - - - - * - - | - * - - - - - - | <-- keyd20
LC93 -> - - - - - - - - - - - - * - - | - * - - - - - - | <-- keyd21
LC95 -> - - - - - - - - - - - - * - - | - * - - - - - - | <-- keyd22
LC74 -> - - - - - - - - - - - - * - - | - * - - - - - - | <-- keyd23
LC66 -> - - - - - - - - - - - - * - - | - * - - - - - - | <-- keyd24
LC76 -> - - - - - - - - - - - - * - - | - * - - - - - - | <-- keyd25
LC86 -> - - - - - - - - - - - - * - - | - * - - - - - - | <-- keyd26
LC33 -> - - - - - - - - - - - - - * - | - * - - - - - - | <-- keyd31
LC48 -> - - - - - - - - - - - - - * - | - * - - - - - - | <-- keyd32
LC36 -> - - - - - - - - - - - - - * - | - * - - - - - - | <-- keyd33
LC15 -> - - - - - - - - - - - - - * - | - * - - - - - - | <-- keyd34
LC7 -> - - - - - - - - - - - - - * - | - * - - - - - - | <-- keyd35
LC118-> - - - - - - - - - - - - - - * | - * - - - - - - | <-- keyd41
LC116-> - - - - - - - - - - - - - - * | - * - - - - - - | <-- keyd42
LC119-> - - - - - - - - - - - - - - * | - * - - - - - - | <-- keyd43
LC9 -> - - - - - - - - - - - - - - * | - * - - - - - - | <-- keyd44
LC1 -> - - - - - - - - - - - - - - * | - * - - - - - - | <-- keyd45
LC5 -> - - - - - - - - - - - - - - * | - * - - - - - - | <-- keyd46
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC37 iorqce~1
| +----------------------------- LC46 keyd11
| | +--------------------------- LC47 keyd12
| | | +------------------------- LC43 keyd17
| | | | +----------------------- LC33 keyd31
| | | | | +--------------------- LC48 keyd32
| | | | | | +------------------- LC36 keyd33
| | | | | | | +----------------- LC39 keyd37
| | | | | | | | +--------------- LC45 nmi
| | | | | | | | | +------------- LC35 sdcs
| | | | | | | | | | +----------- LC38 sddatard1
| | | | | | | | | | | +--------- LC42 sddatard5
| | | | | | | | | | | | +------- LC40 sddatard6
| | | | | | | | | | | | | +----- LC41 starttr1
| | | | | | | | | | | | | | +--- LC34 stoptr
| | | | | | | | | | | | | | | +- LC44 ~531~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
LC42 -> - - - - - - - - - - - - * - - - | * - * - - - - - | <-- sddatard5
LC41 -> - - - - - - - - - - * * * - - * | - - * * * - * - | <-- starttr1
LC34 -> - - - - - - - - - - * * * * - * | - - * * * * * - | <-- stoptr
Pin
84 -> * - - - - - - - - * - - - - * - | * - * * * * * * | <-- adr0
4 -> * - - - - - - - - * - - - - * - | * - * * * * * * | <-- adr1
5 -> * - - - - - - - - - - - - - - - | - - * * * * - * | <-- adr2
21 -> * - - - - - - - - * - - - - * * | * - * * - * * * | <-- adr5
18 -> * - - - - - - - - * - - - - * - | * - * * - * * * | <-- adr6
58 -> * - - - - - - - - * - - - - * * | * - * * - * * * | <-- adr7
49 -> - * - - * - - - - - - - - - - - | - - * - - * - * | <-- data1
48 -> - - * - - * - - - - - - - - - - | - - * - - * - * | <-- data2
33 -> - - - - - - * - - - - - - - - - | - - * - * - * * | <-- data3
34 -> - - - * - - - * - - - - - - - - | - - * - - * * * | <-- data7
77 -> * - - - - - - - - * - - - - * - | * - * * * * * * | <-- dos
12 -> - - - - - - - - - * - - - - * * | * - * * * * * * | <-- iorq
15 -> * - - - - - - - - - - - - - - - | - - * * * * - * | <-- m1
11 -> * - - - - - - - - - - - - - * - | * - * * * * * * | <-- rd
1 -> - - - - - - - - - - - - - - - - | - - - - * * - - | <-- restrig
2 -> - - - - - - - - - - * * * * - - | - - * * * - * - | <-- sdtakt
83 -> - - - - - - - - - - - - - - - - | - - - - - * - - | <-- strobe
30 -> - - - - - - - - - * - - - - * * | - - * * * * - - | <-- wr
LC81 -> - * * * - - - - - - - - - - - - | - * * - * - - - | <-- counter1
LC97 -> - - - - * * * * - - - - - - - - | * * * - - - - - | <-- counter3
LC105-> - - - - - - - - - * - - - - - - | - - * * - - - - | <-- dbus1
LC64 -> * - - - - - - - - - - - - - - - | - - * - - - - - | <-- iorqcc~1
LC85 -> - - - - - - - - - * - - - - - - | - - * * - - - - | <-- reso
LC109-> - - - - - - - - - - - - - - * - | - - * - - - * - | <-- sdcounter3
LC62 -> - - - - - - - - - - * - - - - - | - - * - - - - * | <-- sddatard0
LC71 -> - - - - - - - - - - - * - - - - | * - * - - - - - | <-- sddatard4
LC90 -> - - - - - - - - - - - - - * - - | - - * - - - - - | <-- starttr
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC53 ebl
| +----------------------------- LC49 ior
| | +--------------------------- LC64 iorqcc~1
| | | +------------------------- LC57 iorqce
| | | | +----------------------- LC56 sddatao
| | | | | +--------------------- LC62 sddatard0
| | | | | | +------------------- LC60 sddatawr0
| | | | | | | +----------------- LC63 sddatawr1
| | | | | | | | +--------------- LC52 sddatawr2
| | | | | | | | | +------------- LC54 sddatawr3
| | | | | | | | | | +----------- LC58 sddatawr4
| | | | | | | | | | | +--------- LC59 sddatawr5
| | | | | | | | | | | | +------- LC61 sddatawr6
| | | | | | | | | | | | | +----- LC51 sdpower
| | | | | | | | | | | | | | +--- LC55 synchrotrig0
| | | | | | | | | | | | | | | +- LC50 synchrotrig1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D':
LC60 -> - - - - - - - * - - - - - - - - | - - - * - - - - | <-- sddatawr0
LC63 -> - - - - - - - - * - - - - - - - | - - - * - - - - | <-- sddatawr1
LC52 -> - - - - - - - - - * - - - - - - | - - - * - - - - | <-- sddatawr2
LC54 -> - - - - - - - - - - * - - - - - | - - - * - - - - | <-- sddatawr3
LC58 -> - - - - - - - - - - - * - - - - | - - - * - - - - | <-- sddatawr4
LC59 -> - - - - - - - - - - - - * - - - | - - - * - - - - | <-- sddatawr5
LC61 -> - - - - * - - - - - - - - - - - | - - - * - - - - | <-- sddatawr6
LC55 -> - - - - * - * * * * * * * - - * | - - - * - - - - | <-- synchrotrig0
LC50 -> - - - - - - - - - - - - - - * - | - - - * - - - - | <-- synchrotrig1
Pin
84 -> - * * * * - * * * * * * * * * - | * - * * * * * * | <-- adr0
4 -> * * * * * - * * * * * * * * * - | * - * * * * * * | <-- adr1
5 -> * * * * - - - - - - - - - - - - | - - * * * * - * | <-- adr2
21 -> - - * * * - * * * * * * * * * - | * - * * - * * * | <-- adr5
18 -> - - - * * - * * * * * * * * * - | * - * * - * * * | <-- adr6
58 -> - - * * * - * * * * * * * * * - | * - * * - * * * | <-- adr7
77 -> * * - * * - * * * * * * * * * - | * - * * * * * * | <-- dos
12 -> - * - - * - * * * * * * * * * - | * - * * * * * * | <-- iorq
15 -> * * * * - - - - - - - - - - - - | - - * * * * - * | <-- m1
11 -> - * * * - - - - - - - - - - - - | * - * * * * * * | <-- rd
1 -> - - - - - - - - - - - - - - - - | - - - - * * - - | <-- restrig
20 -> - - - - - * - - - - - - - - - - | - - - * - - - - | <-- sddatain
2 -> - - - - * * - * * * * * * - - * | - - * * * - * - | <-- sdtakt
83 -> - - - - - - - - - - - - - - - - | - - - - - * - - | <-- strobe
30 -> - * - - * - * * * * * * * * * - | - - * * * * - - | <-- wr
LC125-> - - - - - - * - - - - - - * - - | - - - * - - - - | <-- dbus0
LC105-> - - - - - - - * - - - - - - - - | - - * * - - - - | <-- dbus1
LC126-> - - - - - - - - * - - - - - - - | - - - * - - - - | <-- dbus2
LC13 -> - - - - - - - - - * - - - - - - | - - - * - - - - | <-- dbus3
LC8 -> - - - - - - - - - - * - - - - - | - - - * - - - - | <-- dbus4
LC6 -> - - - - - - - - - - - * - - - - | - - - * - - - - | <-- dbus5
LC107-> - - - - - - - - - - - - * - - - | - - - * - - - - | <-- dbus6
LC104-> - - - - * - - - - - - - - - - - | - - - * - - - - | <-- dbus7
LC85 -> - - - - - - - - - - - - - * - - | - - * * - - - - | <-- reso
LC41 -> - - - - * * * * * * * * * - - - | - - * * * - * - | <-- starttr1
LC34 -> - - - - * * * * * * * * * - * - | - - * * * * * - | <-- stoptr
LC44 -> - - - - * - - * * * * * * - - - | - - - * - - - - | <-- ~531~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+------------------------------- LC65 iow
| +----------------------------- LC78 keyd13
| | +--------------------------- LC73 keyd14
| | | +------------------------- LC69 keyd15
| | | | +----------------------- LC75 keyd20
| | | | | +--------------------- LC74 keyd23
| | | | | | +------------------- LC66 keyd24
| | | | | | | +----------------- LC76 keyd25
| | | | | | | | +--------------- LC80 magic1
| | | | | | | | | +------------- LC70 mousey0
| | | | | | | | | | +----------- LC72 mousey3
| | | | | | | | | | | +--------- LC68 mousey4
| | | | | | | | | | | | +------- LC79 mousey5
| | | | | | | | | | | | | +----- LC67 rdh
| | | | | | | | | | | | | | +--- LC71 sddatard4
| | | | | | | | | | | | | | | +- LC77 ~258~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'E'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'E':
LC78 -> - - - - - - - - - - - - - - - * | - - - - * - - - | <-- keyd13
LC73 -> - - - - - - - - - - - - - - - * | - - - - * - - - | <-- keyd14
LC69 -> - - - - - - - - - - - - - - - * | - - - - * - - - | <-- keyd15
Pin
84 -> * - - - - - - - - - - - - * - - | * - * * * * * * | <-- adr0
4 -> * - - - - - - - - - - - - * - - | * - * * * * * * | <-- adr1
5 -> * - - - - - - - - - - - - * - - | - - * * * * - * | <-- adr2
24 -> - - - - - - - - - - - - - - - * | * * - - * * * * | <-- a8
27 -> - - - - - - - - - - - - - - - * | - * - - * * - - | <-- a9
22 -> - - - - - - - - - - - - - - - * | * * - - * * * * | <-- a10
29 -> - - - - - - - - - - - - - - - * | - * - - * * - - | <-- a11
74 -> - - - - - - - - - - - - - - - * | - * - - * * - - | <-- a12
76 -> - - - - - - - - - - - - - - - * | - * - - * * - - | <-- a13
73 -> - - - - - - - - - - - - - - - * | - * - - * * - - | <-- a14
56 -> - - - - * - - - * * - - - - - - | * * - - * - - - | <-- data0
33 -> - * - - - * - - - - * - - - - - | - - * - * - * * | <-- data3
50 -> - - * - - - * - - - - * - - - - | * - - - * - - - | <-- data4
46 -> - - - * - - - * - - - - * - - - | * - - - * - - - | <-- data5
77 -> * - - - - - - - - - - - - * - - | * - * * * * * * | <-- dos
12 -> * - - - - - - - - - - - - * - - | * - * * * * * * | <-- iorq
51 -> - - - - - - - - * - - - - - - - | - - - - * - - - | <-- magic0
15 -> * - - - - - - - - - - - - * - - | - - * * * * - * | <-- m1
11 -> * - - - - - - - - - - - - * - - | * - * * * * * * | <-- rd
1 -> - - - - - - - - * - - - - - - - | - - - - * * - - | <-- restrig
2 -> - - - - - - - - - - - - - - * - | - - * * * - * - | <-- sdtakt
83 -> - - - - - - - - - - - - - - - - | - - - - - * - - | <-- strobe
30 -> * - - - - - - - - - - - - * - - | - - * * * * - - | <-- wr
LC81 -> - * * * - - - - - - - - - - - - | - * * - * - - - | <-- counter1
LC32 -> - - - - * * * * - - - - - - - - | - - - - * * * - | <-- counter2
LC21 -> - - - - - - - - - * * * * - - - | - - - - * * - - | <-- counter6
LC23 -> - - - - - - - - - - - - - - - * | - - - - * - - - | <-- keyd10
LC46 -> - - - - - - - - - - - - - - - * | - - - - * - - - | <-- keyd11
LC47 -> - - - - - - - - - - - - - - - * | - - - - * - - - | <-- keyd12
LC31 -> - - - - - - - - - - - - - - - * | - - - - * - - - | <-- keyd16
LC101-> - - - - - - - - - - - - - - * - | * - - - * - - - | <-- sddatard3
LC41 -> - - - - - - - - - - - - - - * - | - - * * * - * - | <-- starttr1
LC34 -> - - - - - - - - - - - - - - * - | - - * * * * * - | <-- stoptr
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+------------------------------- LC81 counter1
| +----------------------------- LC82 counter7
| | +--------------------------- LC96 keyd01
| | | +------------------------- LC94 keyd02
| | | | +----------------------- LC93 keyd21
| | | | | +--------------------- LC95 keyd22
| | | | | | +------------------- LC86 keyd26
| | | | | | | +----------------- LC89 mousey1
| | | | | | | | +--------------- LC91 mousey2
| | | | | | | | | +------------- LC92 mousey6
| | | | | | | | | | +----------- LC87 mousey7
| | | | | | | | | | | +--------- LC85 reso
| | | | | | | | | | | | +------- LC88 reso~1
| | | | | | | | | | | | | +----- LC90 starttr
| | | | | | | | | | | | | | +--- LC83 wrh
| | | | | | | | | | | | | | | +- LC84 ~243~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC96 -> - - - - - - - - - - - - - - - * | - - - - - * - - | <-- keyd01
LC94 -> - - - - - - - - - - - - - - - * | - - - - - * - - | <-- keyd02
Pin
84 -> - - - - - - - - - - - - - * * - | * - * * * * * * | <-- adr0
4 -> - - - - - - - - - - - - - * * - | * - * * * * * * | <-- adr1
5 -> - - - - - - - - - - - - - - * - | - - * * * * - * | <-- adr2
21 -> - - - - - - - - - - - - - * - - | * - * * - * * * | <-- adr5
18 -> - - - - - - - - - - - - - * - - | * - * * - * * * | <-- adr6
58 -> - - - - - - - - - - - - - * - - | * - * * - * * * | <-- adr7
24 -> - - - - - - - - - - - - - - - * | * * - - * * * * | <-- a8
27 -> - - - - - - - - - - - - - - - * | - * - - * * - - | <-- a9
22 -> - - - - - - - - - - - - - - - * | * * - - * * * * | <-- a10
29 -> - - - - - - - - - - - - - - - * | - * - - * * - - | <-- a11
74 -> - - - - - - - - - - - - - - - * | - * - - * * - - | <-- a12
76 -> - - - - - - - - - - - - - - - * | - * - - * * - - | <-- a13
73 -> - - - - - - - - - - - - - - - * | - * - - * * - - | <-- a14
49 -> - - * - * - - * - - - - - - - - | - - * - - * - * | <-- data1
48 -> - - - * - * - - * - - - - - - - | - - * - - * - * | <-- data2
35 -> - - - - - - * - - * - - - - - - | * * - - - * - - | <-- data6
34 -> - - - - - - - - - - * - - - - - | - - * - - * * * | <-- data7
77 -> - - - - - - - - - - - - - * * - | * - * * * * * * | <-- dos
12 -> - - - - - - - - - - - - - * * - | * - * * * * * * | <-- iorq
15 -> - - - - - - - - - - - - - - * - | - - * * * * - * | <-- m1
11 -> - - - - - - - - - - - - - * * - | * - * * * * * * | <-- rd
1 -> - - - - - - - - - - - * * - - - | - - - - * * - - | <-- restrig
2 -> - - - - - - - - - - - - - - - - | - - * * * - * - | <-- sdtakt
83 -> - - - - - - - - - - - * * - - - | - - - - - * - - | <-- strobe
30 -> - - - - - - - - - - - - - * * - | - - * * * * - - | <-- wr
LC113-> * - * * - - - - - - - - - - - - | * - - - - * * - | <-- counter0
LC32 -> - - - - * * * - - - - - - - - - | - - - - * * * - | <-- counter2
LC21 -> - * - - - - - * * * * - - - - - | - - - - * * - - | <-- counter6
LC10 -> - - - - - - - - - - - - - - - * | - - - - - * - - | <-- keyd00
LC106-> - - - - - - - - - - - - - - - * | - - - - - * - - | <-- keyd03
LC3 -> - - - - - - - - - - - - - - - * | - - - - - * - - | <-- keyd04
LC4 -> - - - - - - - - - - - - - - - * | - - - - - * - - | <-- keyd05
LC2 -> - - - - - - - - - - - - - - - * | - - - - - * - - | <-- keyd06
LC34 -> - - - - - - - - - - - - - * - - | - - * * * * * - | <-- stoptr
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+----------------------------- LC97 counter3
| +--------------------------- LC105 dbus1
| | +------------------------- LC107 dbus6
| | | +----------------------- LC104 dbus7
| | | | +--------------------- LC106 keyd03
| | | | | +------------------- LC102 keyd07
| | | | | | +----------------- LC103 keyd27
| | | | | | | +--------------- LC112 sdcounter0
| | | | | | | | +------------- LC100 sdcounter1
| | | | | | | | | +----------- LC111 sdcounter2
| | | | | | | | | | +--------- LC109 sdcounter3
| | | | | | | | | | | +------- LC110 sddatard2
| | | | | | | | | | | | +----- LC101 sddatard3
| | | | | | | | | | | | | +--- LC98 sddatard7
| | | | | | | | | | | | | | +- LC99 sdtakto
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'G'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC112-> - - - - - - - * * * * - - - - | - - - - - - * - | <-- sdcounter0
LC100-> - - - - - - - - * * * - - - - | - - - - - - * - | <-- sdcounter1
LC111-> - - - - - - - - - * * - - - - | - - - - - - * - | <-- sdcounter2
LC109-> - - - - - - - * * * * - - - - | - - * - - - * - | <-- sdcounter3
LC110-> - - - - - - - - - - - - * - - | - - - - - - * * | <-- sddatard2
LC98 -> - - - * - - - - - - - - - - - | - - - - - - * - | <-- sddatard7
Pin
84 -> - * * * - - - - - - - - - - - | * - * * * * * * | <-- adr0
4 -> - * * * - - - - - - - - - - - | * - * * * * * * | <-- adr1
21 -> - * * * - - - - - - - - - - - | * - * * - * * * | <-- adr5
18 -> - * * * - - - - - - - - - - - | * - * * - * * * | <-- adr6
58 -> - * * * - - - - - - - - - - - | * - * * - * * * | <-- adr7
24 -> - * * * - - - - - - - - - - - | * * - - * * * * | <-- a8
22 -> - * * * - - - - - - - - - - - | * * - - * * * * | <-- a10
33 -> - - - - * - - - - - - - - - - | - - * - * - * * | <-- data3
34 -> - - - - - * * - - - - - - - - | - - * - - * * * | <-- data7
77 -> - * * * - - - - - - - - - - - | * - * * * * * * | <-- dos
12 -> - * * * - - - - - - - - - - - | * - * * * * * * | <-- iorq
11 -> - * * * - - - - - - - - - - - | * - * * * * * * | <-- rd
17 -> - * - - - - - - - - - - - - - | - - - - - - * - | <-- readonly
1 -> - - - - - - - - - - - - - - - | - - - - * * - - | <-- restrig
2 -> - - - - - - - * * * * * * * * | - - * * * - * - | <-- sdtakt
83 -> - - - - - - - - - - - - - - - | - - - - - * - - | <-- strobe
LC113-> - - - - * * - - - - - - - - - | * - - - - * * - | <-- counter0
LC32 -> * - - - - - * - - - - - - - - | - - - - * * * - | <-- counter2
LC114-> - * - - - - - - - - - - - - - | - - - - - - * - | <-- mousebut1
LC117-> - * - - - - - - - - - - - - - | - - - - - - * - | <-- mousex1
LC29 -> - - * - - - - - - - - - - - - | - - - - - - * - | <-- mousex6
LC122-> - - - * - - - - - - - - - - - | - - - - - - * - | <-- mousex7
LC89 -> - * - - - - - - - - - - - - - | - - - - - - * - | <-- mousey1
LC92 -> - - * - - - - - - - - - - - - | - - - - - - * - | <-- mousey6
LC87 -> - - - * - - - - - - - - - - - | - - - - - - * - | <-- mousey7
LC38 -> - * - - - - - - - - - * - - - | - - - - - - * - | <-- sddatard1
LC40 -> - - * - - - - - - - - - - * - | - - - - - - * - | <-- sddatard6
LC41 -> - - - - - - - * * * * * * * * | - - * * * - * - | <-- starttr1
LC34 -> - - - - - - - * * * * * * * * | - - * * * * * - | <-- stoptr
LC77 -> - * - - - - - - - - - - - - - | - - - - - - * - | <-- ~258~1
LC121-> - * - - - - - - - - - - - - - | - - - - - - * - | <-- ~259~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------------------- LC113 counter0
| +----------------------------- LC125 dbus0
| | +--------------------------- LC126 dbus2
| | | +------------------------- LC115 dbus7~1
| | | | +----------------------- LC118 keyd41
| | | | | +--------------------- LC116 keyd42
| | | | | | +------------------- LC119 keyd43
| | | | | | | +----------------- LC127 keyd47
| | | | | | | | +--------------- LC114 mousebut1
| | | | | | | | | +------------- LC120 mousebut2
| | | | | | | | | | +----------- LC117 mousex1
| | | | | | | | | | | +--------- LC124 mousex2
| | | | | | | | | | | | +------- LC128 mousex3
| | | | | | | | | | | | | +----- LC122 mousex7
| | | | | | | | | | | | | | +--- LC123 ~244~1
| | | | | | | | | | | | | | | +- LC121 ~259~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC120-> - - * - - - - - - - - - - - - - | - - - - - - - * | <-- mousebut2
LC124-> - - * - - - - - - - - - - - - - | - - - - - - - * | <-- mousex2
LC123-> - * - - - - - - - - - - - - - - | - - - - - - - * | <-- ~244~1
Pin
84 -> - * * * - - - - - - - - - - - - | * - * * * * * * | <-- adr0
4 -> - * * * - - - - - - - - - - - - | * - * * * * * * | <-- adr1
5 -> - - - * - - - - - - - - - - - - | - - * * * * - * | <-- adr2
21 -> - * * * - - - - - - - - - - - - | * - * * - * * * | <-- adr5
18 -> - * * * - - - - - - - - - - - - | * - * * - * * * | <-- adr6
58 -> - * * * - - - - - - - - - - - - | * - * * - * * * | <-- adr7
24 -> - * * - - - - - - - - - - - - - | * * - - * * * * | <-- a8
22 -> - * * - - - - - - - - - - - - - | * * - - * * * * | <-- a10
70 -> - - * - - - - - - - - - - - * * | * - - - - - - * | <-- a15
49 -> - - - - * - - - * - * - - - - - | - - * - - * - * | <-- data1
48 -> - - - - - * - - - * - * - - - - | - - * - - * - * | <-- data2
33 -> - - - - - - * - - - - - * - - - | - - * - * - * * | <-- data3
34 -> - - - - - - - * - - - - - * - - | - - * - - * * * | <-- data7
77 -> - * * * - - - - - - - - - - - - | * - * * * * * * | <-- dos
12 -> - * * * - - - - - - - - - - - - | * - * * * * * * | <-- iorq
15 -> - - - * - - - - - - - - - - - - | - - * * * * - * | <-- m1
11 -> - * * * - - - - - - - - - - - - | * - * * * * * * | <-- rd
1 -> - - - - - - - - - - - - - - - - | - - - - * * - - | <-- restrig
28 -> - * - - - - - - - - - - - - - - | - - - - - - - * | <-- sdabsent
2 -> - - - - - - - - - - - - - - - - | - - * * * - * - | <-- sdtakt
83 -> - - - - - - - - - - - - - - - - | - - - - - * - - | <-- strobe
LC27 -> - - - - * * * * - - - - - - - - | * * - - - - - * | <-- counter4
LC25 -> - - - - - - - - - - * * * * - - | * * - - - - - * | <-- counter5
LC82 -> * - - - - - - - * * - - - - - - | - * - - - - - * | <-- counter7
LC102-> - - - - - - - - - - - - - - * - | - - - - - - - * | <-- keyd07
LC43 -> - - - - - - - - - - - - - - - * | - - - - - - - * | <-- keyd17
LC103-> - - * - - - - - - - - - - - - - | - - - - - - - * | <-- keyd27
LC22 -> - * - - - - - - - - - - - - - - | - - - - - - - * | <-- mousebut0
LC19 -> - * - - - - - - - - - - - - - - | - - - - - - - * | <-- mousex0
LC70 -> - * - - - - - - - - - - - - - - | - - - - - - - * | <-- mousey0
LC91 -> - - * - - - - - - - - - - - - - | - - - - - - - * | <-- mousey2
LC62 -> - * - - - - - - - - - - - - - - | - - * - - - - * | <-- sddatard0
LC110-> - - * - - - - - - - - - - - - - | - - - - - - * * | <-- sddatard2
LC84 -> - * - - - - - - - - - - - - - - | - - - - - - - * | <-- ~243~1
LC30 -> - - * - - - - - - - - - - - - - | - - - - - - - * | <-- ~273~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\111\cpld_zc\zcont.rpt
zcont
** EQUATIONS **
adr0 : INPUT;
adr1 : INPUT;
adr2 : INPUT;
adr3 : INPUT;
adr4 : INPUT;
adr5 : INPUT;
adr6 : INPUT;
adr7 : INPUT;
a8 : INPUT;
a9 : INPUT;
a10 : INPUT;
a11 : INPUT;
a12 : INPUT;
a13 : INPUT;
a14 : INPUT;
a15 : INPUT;
data0 : INPUT;
data1 : INPUT;
data2 : INPUT;
data3 : INPUT;
data4 : INPUT;
data5 : INPUT;
data6 : INPUT;
data7 : INPUT;
dos : INPUT;
iorq : INPUT;
magic0 : INPUT;
m1 : INPUT;
rd : INPUT;
readonly : INPUT;
restrig : INPUT;
sdabsent : INPUT;
sddatain : INPUT;
sdtakt : INPUT;
strobe : INPUT;
wr : INPUT;
-- Node name is 'counter0' from file "zcont.tdf" line 18, column 60
-- Equation name is 'counter0', location is LC113, type is buried.
counter0 = DFFE(!counter7 $ GND, GLOBAL(!strobe), GLOBAL( restrig), VCC, VCC);
-- Node name is 'counter1' from file "zcont.tdf" line 18, column 60
-- Equation name is 'counter1', location is LC081, type is buried.
counter1 = DFFE( counter0 $ GND, GLOBAL(!strobe), GLOBAL( restrig), VCC, VCC);
-- Node name is 'counter2' from file "zcont.tdf" line 18, column 60
-- Equation name is 'counter2', location is LC032, type is buried.
counter2 = DFFE( counter1 $ GND, GLOBAL(!strobe), GLOBAL( restrig), VCC, VCC);
-- Node name is 'counter3' from file "zcont.tdf" line 18, column 60
-- Equation name is 'counter3', location is LC097, type is buried.
counter3 = DFFE( counter2 $ GND, GLOBAL(!strobe), GLOBAL( restrig), VCC, VCC);
-- Node name is 'counter4' from file "zcont.tdf" line 18, column 60
-- Equation name is 'counter4', location is LC027, type is buried.
counter4 = DFFE( counter3 $ GND, GLOBAL(!strobe), GLOBAL( restrig), VCC, VCC);
-- Node name is 'counter5' from file "zcont.tdf" line 18, column 60
-- Equation name is 'counter5', location is LC025, type is buried.
counter5 = DFFE( counter4 $ GND, GLOBAL(!strobe), GLOBAL( restrig), VCC, VCC);
-- Node name is 'counter6' from file "zcont.tdf" line 18, column 60
-- Equation name is 'counter6', location is LC021, type is buried.
counter6 = DFFE( counter5 $ GND, GLOBAL(!strobe), GLOBAL( restrig), VCC, VCC);
-- Node name is 'counter7' from file "zcont.tdf" line 18, column 60
-- Equation name is 'counter7', location is LC082, type is buried.
counter7 = DFFE( counter6 $ GND, GLOBAL(!strobe), GLOBAL( restrig), VCC, VCC);
-- Node name is 'dbus0'
-- Equation name is 'dbus0', location is LC125, type is bidir.
dbus0 = TRI(_LC125, _LC115);
_LC125 = LCELL( _EQ001 $ VCC);
_EQ001 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006
# !mousebut0 & _X001 & _X003 & _X004 & _X005 & _X006;
_X001 = EXP(!adr5 & adr6 & adr7 & a10 & dos & !iorq & mousey0 & !rd);
_X002 = EXP(!adr5 & adr6 & adr7 & !a8 & !a10 & dos & !iorq & !rd);
_X003 = EXP( adr0 & adr1 & adr5 & adr6 & !adr7 & dos & !iorq & !rd &
sdabsent);
_X004 = EXP( adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq & !rd &
sddatard0);
_X005 = EXP(!adr5 & adr6 & adr7 & a8 & !a10 & dos & !iorq & mousex0 & !rd);
_X006 = EXP(!adr0 & !iorq & _LC084 & _LC123 & !rd);
-- Node name is 'dbus1'
-- Equation name is 'dbus1', location is LC105, type is bidir.
dbus1 = TRI(_LC105, _LC115);
_LC105 = LCELL( _EQ002 $ VCC);
_EQ002 = _X002 & _X007 & _X008 & _X009 & _X010 & _X011
# !mousebut1 & _X007 & _X008 & _X009 & _X010 & _X011;
_X002 = EXP(!adr5 & adr6 & adr7 & !a8 & !a10 & dos & !iorq & !rd);
_X007 = EXP(!adr5 & adr6 & adr7 & a10 & dos & !iorq & mousey1 & !rd);
_X008 = EXP( adr0 & adr1 & adr5 & adr6 & !adr7 & dos & !iorq & !rd &
readonly);
_X009 = EXP( adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq & !rd &
sddatard1);
_X010 = EXP(!adr5 & adr6 & adr7 & a8 & !a10 & dos & !iorq & mousex1 & !rd);
_X011 = EXP(!adr0 & !iorq & _LC077 & _LC121 & !rd);
-- Node name is 'dbus2'
-- Equation name is 'dbus2', location is LC126, type is bidir.
dbus2 = TRI(_LC126, _LC115);
_LC126 = LCELL( _EQ003 $ _EQ004);
_EQ003 = !adr5 & adr6 & adr7 & a8 & !a10 & dos & !iorq & mousex2 & !rd &
_X012
# !adr5 & adr6 & adr7 & !a8 & !a10 & dos & !iorq & mousebut2 &
!rd & _X012
# !adr5 & adr6 & adr7 & a10 & dos & !iorq & mousey2 & !rd &
_X012
# !adr0 & !iorq & _LC030 & !rd & _X012 & _X013;
_X012 = EXP( adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq & !rd &
sddatard2);
_X013 = EXP(!a15 & !keyd27);
_EQ004 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq & !rd &
sddatard2;
-- Node name is 'dbus3'
-- Equation name is 'dbus3', location is LC013, type is bidir.
dbus3 = TRI(_LC013, _LC115);
_LC013 = LCELL( _EQ005 $ _EQ006);
_EQ005 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq & !rd &
sddatard3 & _X014
# !adr5 & adr6 & adr7 & a10 & dos & !iorq & mousey3 & !rd &
_X014
# !adr5 & adr6 & adr7 & !a10 & dos & !iorq & mousex3 & !rd &
_X014
# !adr5 & adr6 & adr7 & !a8 & !a10 & dos & !iorq & !rd & _X014;
_X014 = EXP(!adr0 & !iorq & _LC016 & _LC020 & !rd);
_EQ006 = !adr0 & !iorq & _LC020 & !rd & _X015;
_X015 = EXP(!a15 & !keyd37);
-- Node name is 'dbus4'
-- Equation name is 'dbus4', location is LC008, type is bidir.
dbus4 = TRI(_LC008, _LC115);
_LC008 = LCELL( _EQ007 $ _EQ008);
_EQ007 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq & !rd &
sddatard4 & _X016
# !adr5 & adr6 & adr7 & a10 & dos & !iorq & mousey4 & !rd &
_X016
# !adr5 & adr6 & adr7 & !a10 & dos & !iorq & mousex4 & !rd &
_X016
# !adr5 & adr6 & adr7 & !a8 & !a10 & dos & !iorq & !rd & _X016;
_X016 = EXP(!adr0 & !iorq & _LC014 & _LC018 & !rd);
_EQ008 = !adr0 & !iorq & _LC018 & !rd & _X017;
_X017 = EXP(!a15 & !keyd47);
-- Node name is 'dbus5'
-- Equation name is 'dbus5', location is LC006, type is bidir.
dbus5 = TRI(_LC006, _LC115);
_LC006 = LCELL( _EQ009 $ GND);
_EQ009 = !adr5 & adr6 & adr7 & a8 & !a10 & dos & !iorq & mousex5 & !rd
# adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq & !rd &
sddatard5
# !adr5 & adr6 & adr7 & a10 & dos & !iorq & mousey5 & !rd
# !adr5 & adr6 & adr7 & !a8 & !a10 & dos & !iorq & !rd
# !adr0 & !iorq & !rd;
-- Node name is 'dbus6'
-- Equation name is 'dbus6', location is LC107, type is bidir.
dbus6 = TRI(_LC107, _LC115);
_LC107 = LCELL( _EQ010 $ GND);
_EQ010 = !adr5 & adr6 & adr7 & a8 & !a10 & dos & !iorq & mousex6 & !rd
# adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq & !rd &
sddatard6
# !adr5 & adr6 & adr7 & a10 & dos & !iorq & mousey6 & !rd
# !adr5 & adr6 & adr7 & !a8 & !a10 & dos & !iorq & !rd
# !adr0 & !iorq & !rd;
-- Node name is 'dbus7~1' from file "zcont.tdf" line 97, column 5
-- Equation name is 'dbus7~1', location is LC115, type is buried.
-- synthesized logic cell
_LC115 = LCELL( _EQ011 $ GND);
_EQ011 = !iorq & !rd & _X018 & _X019 & _X020 & _X021 & _X022 & _X023 &
_X024;
_X018 = EXP(!adr1 & !adr2 & !adr7 & dos & m1);
_X019 = EXP(!adr1 & !adr2 & adr5 & dos & m1);
_X020 = EXP(!adr1 & !adr2 & !adr6 & dos & m1);
_X021 = EXP( adr0 & adr5 & adr7);
_X022 = EXP( adr0 & !adr1 & !adr7);
_X023 = EXP( adr0 & !dos);
_X024 = EXP( adr0 & !adr6);
-- Node name is 'dbus7'
-- Equation name is 'dbus7', location is LC104, type is bidir.
dbus7 = TRI(_LC104, _LC115);
_LC104 = LCELL( _EQ012 $ GND);
_EQ012 = !adr5 & adr6 & adr7 & a8 & !a10 & dos & !iorq & mousex7 & !rd
# adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq & !rd &
sddatard7
# !adr5 & adr6 & adr7 & a10 & dos & !iorq & mousey7 & !rd
# !adr5 & adr6 & adr7 & !a8 & !a10 & dos & !iorq & !rd
# !adr0 & !iorq & !rd;
-- Node name is 'ebl'
-- Equation name is 'ebl', location is LC053, type is output.
ebl = LCELL( _EQ013 $ VCC);
_EQ013 = !adr1 & !adr2 & dos & m1;
-- Node name is 'ior'
-- Equation name is 'ior', location is LC049, type is output.
ior = LCELL( _EQ014 $ VCC);
_EQ014 = !adr0 & !adr1 & !adr2 & dos & !iorq & m1 & !rd & wr;
-- Node name is 'iorqcc~1' from file "zcont.tdf" line 85, column 8
-- Equation name is 'iorqcc~1', location is LC064, type is buried.
-- synthesized logic cell
_LC064 = LCELL( _EQ015 $ GND);
_EQ015 = adr0 & adr1 & adr5 & adr7
# adr0 & adr2 & adr5 & adr7
# adr1 & adr5 & adr7 & rd
# adr2 & adr5 & adr7 & rd
# adr0 & adr5 & adr7 & !m1;
-- Node name is 'iorqce'
-- Equation name is 'iorqce', location is LC057, type is bidir.
iorqce = TRI(_LC057, _LC037);
_LC057 = LCELL( _EQ016 $ GND);
_EQ016 = adr0 & adr1 & adr6 & !adr7 & dos
# !adr5 & adr6 & adr7 & dos
# !adr1 & !adr2 & dos & m1
# !adr0 & !rd;
-- Node name is 'iorqce~1' from file "zcont.tdf" line 88, column 1
-- Equation name is 'iorqce~1', location is LC037, type is buried.
-- synthesized logic cell
_LC037 = LCELL( _EQ017 $ GND);
_EQ017 = !_LC064 & _X023 & _X025 & _X026 & _X027 & _X028 & _X029 &
_X030 & _X031 & _X032 & _X033 & _X034 & _X035 & _X036 &
_X037;
_X023 = EXP( adr0 & !dos);
_X025 = EXP(!dos & rd);
_X026 = EXP(!adr0 & !adr7 & !m1 & rd);
_X027 = EXP( adr5 & adr7 & !m1 & rd);
_X028 = EXP(!adr6 & !m1 & rd);
_X029 = EXP( adr0 & !adr6 & !m1);
_X030 = EXP( adr2 & !adr6 & rd);
_X031 = EXP( adr1 & !adr6 & rd);
_X032 = EXP( adr0 & adr2 & !adr6);
_X033 = EXP( adr0 & adr1 & !adr6);
_X034 = EXP( adr0 & !adr1 & adr2 & !adr7);
_X035 = EXP( adr0 & !adr1 & !adr7 & !m1);
_X036 = EXP(!adr0 & adr2 & !adr7 & rd);
_X037 = EXP(!adr0 & adr1 & !adr7 & rd);
-- Node name is 'iow'
-- Equation name is 'iow', location is LC065, type is output.
iow = LCELL( _EQ018 $ VCC);
_EQ018 = !adr0 & !adr1 & !adr2 & dos & !iorq & m1 & rd & !wr;
-- Node name is 'keyd00' from file "zcont.tdf" line 17, column 50
-- Equation name is 'keyd00', location is LC010, type is buried.
keyd00 = DFFE( data0 $ GND, counter0, VCC, VCC, VCC);
-- Node name is 'keyd01' from file "zcont.tdf" line 17, column 50
-- Equation name is 'keyd01', location is LC096, type is buried.
keyd01 = DFFE( data1 $ GND, counter0, VCC, VCC, VCC);
-- Node name is 'keyd02' from file "zcont.tdf" line 17, column 50
-- Equation name is 'keyd02', location is LC094, type is buried.
keyd02 = DFFE( data2 $ GND, counter0, VCC, VCC, VCC);
-- Node name is 'keyd03' from file "zcont.tdf" line 17, column 50
-- Equation name is 'keyd03', location is LC106, type is buried.
keyd03 = DFFE( data3 $ GND, counter0, VCC, VCC, VCC);
-- Node name is 'keyd04' from file "zcont.tdf" line 17, column 50
-- Equation name is 'keyd04', location is LC003, type is buried.
keyd04 = DFFE( data4 $ GND, counter0, VCC, VCC, VCC);
-- Node name is 'keyd05' from file "zcont.tdf" line 17, column 50
-- Equation name is 'keyd05', location is LC004, type is buried.
keyd05 = DFFE( data5 $ GND, counter0, VCC, VCC, VCC);
-- Node name is 'keyd06' from file "zcont.tdf" line 17, column 50
-- Equation name is 'keyd06', location is LC002, type is buried.
keyd06 = DFFE( data6 $ GND, counter0, VCC, VCC, VCC);
-- Node name is 'keyd07' from file "zcont.tdf" line 17, column 50
-- Equation name is 'keyd07', location is LC102, type is buried.
keyd07 = DFFE( data7 $ GND, counter0, VCC, VCC, VCC);
-- Node name is 'keyd10' from file "zcont.tdf" line 18, column 6
-- Equation name is 'keyd10', location is LC023, type is buried.
keyd10 = DFFE( data0 $ GND, counter1, VCC, VCC, VCC);
-- Node name is 'keyd11' from file "zcont.tdf" line 18, column 6
-- Equation name is 'keyd11', location is LC046, type is buried.
keyd11 = DFFE( data1 $ GND, counter1, VCC, VCC, VCC);
-- Node name is 'keyd12' from file "zcont.tdf" line 18, column 6
-- Equation name is 'keyd12', location is LC047, type is buried.
keyd12 = DFFE( data2 $ GND, counter1, VCC, VCC, VCC);
-- Node name is 'keyd13' from file "zcont.tdf" line 18, column 6
-- Equation name is 'keyd13', location is LC078, type is buried.
keyd13 = DFFE( data3 $ GND, counter1, VCC, VCC, VCC);
-- Node name is 'keyd14' from file "zcont.tdf" line 18, column 6
-- Equation name is 'keyd14', location is LC073, type is buried.
keyd14 = DFFE( data4 $ GND, counter1, VCC, VCC, VCC);
-- Node name is 'keyd15' from file "zcont.tdf" line 18, column 6
-- Equation name is 'keyd15', location is LC069, type is buried.
keyd15 = DFFE( data5 $ GND, counter1, VCC, VCC, VCC);
-- Node name is 'keyd16' from file "zcont.tdf" line 18, column 6
-- Equation name is 'keyd16', location is LC031, type is buried.
keyd16 = DFFE( data6 $ GND, counter1, VCC, VCC, VCC);
-- Node name is 'keyd17' from file "zcont.tdf" line 18, column 6
-- Equation name is 'keyd17', location is LC043, type is buried.
keyd17 = DFFE( data7 $ GND, counter1, VCC, VCC, VCC);
-- Node name is 'keyd20' from file "zcont.tdf" line 18, column 19
-- Equation name is 'keyd20', location is LC075, type is buried.
keyd20 = DFFE( data0 $ GND, counter2, VCC, VCC, VCC);
-- Node name is 'keyd21' from file "zcont.tdf" line 18, column 19
-- Equation name is 'keyd21', location is LC093, type is buried.
keyd21 = DFFE( data1 $ GND, counter2, VCC, VCC, VCC);
-- Node name is 'keyd22' from file "zcont.tdf" line 18, column 19
-- Equation name is 'keyd22', location is LC095, type is buried.
keyd22 = DFFE( data2 $ GND, counter2, VCC, VCC, VCC);
-- Node name is 'keyd23' from file "zcont.tdf" line 18, column 19
-- Equation name is 'keyd23', location is LC074, type is buried.
keyd23 = DFFE( data3 $ GND, counter2, VCC, VCC, VCC);
-- Node name is 'keyd24' from file "zcont.tdf" line 18, column 19
-- Equation name is 'keyd24', location is LC066, type is buried.
keyd24 = DFFE( data4 $ GND, counter2, VCC, VCC, VCC);
-- Node name is 'keyd25' from file "zcont.tdf" line 18, column 19
-- Equation name is 'keyd25', location is LC076, type is buried.
keyd25 = DFFE( data5 $ GND, counter2, VCC, VCC, VCC);
-- Node name is 'keyd26' from file "zcont.tdf" line 18, column 19
-- Equation name is 'keyd26', location is LC086, type is buried.
keyd26 = DFFE( data6 $ GND, counter2, VCC, VCC, VCC);
-- Node name is 'keyd27' from file "zcont.tdf" line 18, column 19
-- Equation name is 'keyd27', location is LC103, type is buried.
keyd27 = DFFE( data7 $ GND, counter2, VCC, VCC, VCC);
-- Node name is 'keyd30' from file "zcont.tdf" line 18, column 32
-- Equation name is 'keyd30', location is LC026, type is buried.
keyd30 = DFFE( data0 $ GND, counter3, VCC, VCC, VCC);
-- Node name is 'keyd31' from file "zcont.tdf" line 18, column 32
-- Equation name is 'keyd31', location is LC033, type is buried.
keyd31 = DFFE( data1 $ GND, counter3, VCC, VCC, VCC);
-- Node name is 'keyd32' from file "zcont.tdf" line 18, column 32
-- Equation name is 'keyd32', location is LC048, type is buried.
keyd32 = DFFE( data2 $ GND, counter3, VCC, VCC, VCC);
-- Node name is 'keyd33' from file "zcont.tdf" line 18, column 32
-- Equation name is 'keyd33', location is LC036, type is buried.
keyd33 = DFFE( data3 $ GND, counter3, VCC, VCC, VCC);
-- Node name is 'keyd34' from file "zcont.tdf" line 18, column 32
-- Equation name is 'keyd34', location is LC015, type is buried.
keyd34 = DFFE( data4 $ GND, counter3, VCC, VCC, VCC);
-- Node name is 'keyd35' from file "zcont.tdf" line 18, column 32
-- Equation name is 'keyd35', location is LC007, type is buried.
keyd35 = DFFE( data5 $ GND, counter3, VCC, VCC, VCC);
-- Node name is 'keyd36' from file "zcont.tdf" line 18, column 32
-- Equation name is 'keyd36', location is LC017, type is buried.
keyd36 = DFFE( data6 $ GND, counter3, VCC, VCC, VCC);
-- Node name is 'keyd37' from file "zcont.tdf" line 18, column 32
-- Equation name is 'keyd37', location is LC039, type is buried.
keyd37 = DFFE( data7 $ GND, counter3, VCC, VCC, VCC);
-- Node name is 'keyd40' from file "zcont.tdf" line 18, column 45
-- Equation name is 'keyd40', location is LC024, type is buried.
keyd40 = DFFE( data0 $ GND, counter4, VCC, VCC, VCC);
-- Node name is 'keyd41' from file "zcont.tdf" line 18, column 45
-- Equation name is 'keyd41', location is LC118, type is buried.
keyd41 = DFFE( data1 $ GND, counter4, VCC, VCC, VCC);
-- Node name is 'keyd42' from file "zcont.tdf" line 18, column 45
-- Equation name is 'keyd42', location is LC116, type is buried.
keyd42 = DFFE( data2 $ GND, counter4, VCC, VCC, VCC);
-- Node name is 'keyd43' from file "zcont.tdf" line 18, column 45
-- Equation name is 'keyd43', location is LC119, type is buried.
keyd43 = DFFE( data3 $ GND, counter4, VCC, VCC, VCC);
-- Node name is 'keyd44' from file "zcont.tdf" line 18, column 45
-- Equation name is 'keyd44', location is LC009, type is buried.
keyd44 = DFFE( data4 $ GND, counter4, VCC, VCC, VCC);
-- Node name is 'keyd45' from file "zcont.tdf" line 18, column 45
-- Equation name is 'keyd45', location is LC001, type is buried.
keyd45 = DFFE( data5 $ GND, counter4, VCC, VCC, VCC);
-- Node name is 'keyd46' from file "zcont.tdf" line 18, column 45
-- Equation name is 'keyd46', location is LC005, type is buried.
keyd46 = DFFE( data6 $ GND, counter4, VCC, VCC, VCC);
-- Node name is 'keyd47' from file "zcont.tdf" line 18, column 45
-- Equation name is 'keyd47', location is LC127, type is buried.
keyd47 = DFFE( data7 $ GND, counter4, VCC, VCC, VCC);
-- Node name is 'magic1'
-- Equation name is 'magic1', location is LC080, type is output.
magic1 = LCELL( _EQ019 $ VCC);
_EQ019 = data0 & !magic0 & !restrig;
-- Node name is 'mousebut0' from file "zcont.tdf" line 17, column 37
-- Equation name is 'mousebut0', location is LC022, type is buried.
mousebut0 = DFFE( data0 $ GND, counter7, VCC, VCC, VCC);
-- Node name is 'mousebut1' from file "zcont.tdf" line 17, column 37
-- Equation name is 'mousebut1', location is LC114, type is buried.
mousebut1 = DFFE( data1 $ GND, counter7, VCC, VCC, VCC);
-- Node name is 'mousebut2' from file "zcont.tdf" line 17, column 37
-- Equation name is 'mousebut2', location is LC120, type is buried.
mousebut2 = DFFE( data2 $ GND, counter7, VCC, VCC, VCC);
-- Node name is 'mousex0' from file "zcont.tdf" line 17, column 7
-- Equation name is 'mousex0', location is LC019, type is buried.
mousex0 = DFFE( data0 $ GND, counter5, VCC, VCC, VCC);
-- Node name is 'mousex1' from file "zcont.tdf" line 17, column 7
-- Equation name is 'mousex1', location is LC117, type is buried.
mousex1 = DFFE( data1 $ GND, counter5, VCC, VCC, VCC);
-- Node name is 'mousex2' from file "zcont.tdf" line 17, column 7
-- Equation name is 'mousex2', location is LC124, type is buried.
mousex2 = DFFE( data2 $ GND, counter5, VCC, VCC, VCC);
-- Node name is 'mousex3' from file "zcont.tdf" line 17, column 7
-- Equation name is 'mousex3', location is LC128, type is buried.
mousex3 = DFFE( data3 $ GND, counter5, VCC, VCC, VCC);
-- Node name is 'mousex4' from file "zcont.tdf" line 17, column 7
-- Equation name is 'mousex4', location is LC011, type is buried.
mousex4 = DFFE( data4 $ GND, counter5, VCC, VCC, VCC);
-- Node name is 'mousex5' from file "zcont.tdf" line 17, column 7
-- Equation name is 'mousex5', location is LC012, type is buried.
mousex5 = DFFE( data5 $ GND, counter5, VCC, VCC, VCC);
-- Node name is 'mousex6' from file "zcont.tdf" line 17, column 7
-- Equation name is 'mousex6', location is LC029, type is buried.
mousex6 = DFFE( data6 $ GND, counter5, VCC, VCC, VCC);
-- Node name is 'mousex7' from file "zcont.tdf" line 17, column 7
-- Equation name is 'mousex7', location is LC122, type is buried.
mousex7 = DFFE( data7 $ GND, counter5, VCC, VCC, VCC);
-- Node name is 'mousey0' from file "zcont.tdf" line 17, column 21
-- Equation name is 'mousey0', location is LC070, type is buried.
mousey0 = DFFE( data0 $ GND, counter6, VCC, VCC, VCC);
-- Node name is 'mousey1' from file "zcont.tdf" line 17, column 21
-- Equation name is 'mousey1', location is LC089, type is buried.
mousey1 = DFFE( data1 $ GND, counter6, VCC, VCC, VCC);
-- Node name is 'mousey2' from file "zcont.tdf" line 17, column 21
-- Equation name is 'mousey2', location is LC091, type is buried.
mousey2 = DFFE( data2 $ GND, counter6, VCC, VCC, VCC);
-- Node name is 'mousey3' from file "zcont.tdf" line 17, column 21
-- Equation name is 'mousey3', location is LC072, type is buried.
mousey3 = DFFE( data3 $ GND, counter6, VCC, VCC, VCC);
-- Node name is 'mousey4' from file "zcont.tdf" line 17, column 21
-- Equation name is 'mousey4', location is LC068, type is buried.
mousey4 = DFFE( data4 $ GND, counter6, VCC, VCC, VCC);
-- Node name is 'mousey5' from file "zcont.tdf" line 17, column 21
-- Equation name is 'mousey5', location is LC079, type is buried.
mousey5 = DFFE( data5 $ GND, counter6, VCC, VCC, VCC);
-- Node name is 'mousey6' from file "zcont.tdf" line 17, column 21
-- Equation name is 'mousey6', location is LC092, type is buried.
mousey6 = DFFE( data6 $ GND, counter6, VCC, VCC, VCC);
-- Node name is 'mousey7' from file "zcont.tdf" line 17, column 21
-- Equation name is 'mousey7', location is LC087, type is buried.
mousey7 = DFFE( data7 $ GND, counter6, VCC, VCC, VCC);
-- Node name is 'nmi'
-- Equation name is 'nmi', location is LC045, type is bidir.
nmi = TRI(_LC045, GND);
_LC045 = LCELL( GND $ GND);
-- Node name is 'rdh'
-- Equation name is 'rdh', location is LC067, type is output.
rdh = LCELL( _EQ020 $ VCC);
_EQ020 = adr0 & !adr1 & !adr2 & dos & !iorq & m1 & !rd & wr;
-- Node name is 'reso'
-- Equation name is 'reso', location is LC085, type is bidir.
reso = TRI(_LC085, _LC088);
_LC085 = LCELL( _EQ021 $ VCC);
_EQ021 = !restrig & !strobe;
-- Node name is 'reso~1' from file "zcont.tdf" line 105, column 1
-- Equation name is 'reso~1', location is LC088, type is buried.
-- synthesized logic cell
_LC088 = LCELL( _EQ022 $ GND);
_EQ022 = !restrig & !strobe;
-- Node name is 'sdcounter0' from file "zcont.tdf" line 20, column 27
-- Equation name is 'sdcounter0', location is LC112, type is buried.
sdcounter0 = TFFE( VCC, _EQ023, VCC, starttr1, VCC);
_EQ023 = sdcounter3 & _X038;
_X038 = EXP( sdtakt & starttr1 & stoptr);
-- Node name is 'sdcounter1' from file "zcont.tdf" line 20, column 27
-- Equation name is 'sdcounter1', location is LC100, type is buried.
sdcounter1 = TFFE(!sdcounter0, _EQ024, VCC, starttr1, VCC);
_EQ024 = sdcounter3 & _X038;
_X038 = EXP( sdtakt & starttr1 & stoptr);
-- Node name is 'sdcounter2' from file "zcont.tdf" line 20, column 27
-- Equation name is 'sdcounter2', location is LC111, type is buried.
sdcounter2 = TFFE( _EQ025, _EQ026, VCC, starttr1, VCC);
_EQ025 = !sdcounter0 & !sdcounter1;
_EQ026 = sdcounter3 & _X038;
_X038 = EXP( sdtakt & starttr1 & stoptr);
-- Node name is 'sdcounter3' from file "zcont.tdf" line 20, column 27
-- Equation name is 'sdcounter3', location is LC109, type is buried.
sdcounter3 = TFFE( _EQ027, _EQ028, VCC, starttr1, VCC);
_EQ027 = !sdcounter0 & !sdcounter1 & !sdcounter2;
_EQ028 = sdcounter3 & _X038;
_X038 = EXP( sdtakt & starttr1 & stoptr);
-- Node name is 'sdcs' = 'sdcontrwr1' from file "zcont.tdf" line 20, column 10
-- Equation name is 'sdcs', location is LC035, type is output.
sdcs = DFFE( dbus1 $ GND, _EQ029, reso, VCC, VCC);
_EQ029 = adr0 & adr1 & adr5 & adr6 & !adr7 & dos & !iorq & !wr;
-- Node name is 'sddatao' = 'sddatawr7' from file "zcont.tdf" line 19, column 9
-- Equation name is 'sddatao', location is LC056, type is output.
sddatao = DFFE( _EQ030 $ GND, _EQ031, VCC, VCC, VCC);
_EQ030 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus7 & dos & !iorq &
!stoptr & !wr
# adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus7 & dos & !iorq &
!starttr1 & !wr
# sddatawr6 & starttr1 & stoptr;
_EQ031 = !_LC044 & _X038 & _X039 & _X040 & _X041 & _X042 & _X043 &
_X044 & _X045 & _X046 & _X047 & _X048 & _X049 & _X050 &
_X051;
_X038 = EXP( sdtakt & starttr1 & stoptr);
_X039 = EXP(!stoptr & !synchrotrig0);
_X040 = EXP(!adr6 & !starttr1);
_X041 = EXP( adr5 & !stoptr);
_X042 = EXP(!adr1 & !stoptr);
_X043 = EXP(!adr6 & !stoptr);
_X044 = EXP(!dos & !stoptr);
_X045 = EXP(!adr0 & !stoptr);
_X046 = EXP(!starttr1 & !synchrotrig0);
_X047 = EXP(!adr1 & !starttr1);
_X048 = EXP(!stoptr & wr);
_X049 = EXP(!dos & !starttr1);
_X050 = EXP(!adr0 & !starttr1);
_X051 = EXP( iorq & !stoptr);
-- Node name is 'sddatard0' from file "zcont.tdf" line 19, column 25
-- Equation name is 'sddatard0', location is LC062, type is buried.
sddatard0 = DFFE( sddatain $ GND, _EQ032, VCC, VCC, VCC);
_EQ032 = sdtakt & starttr1 & stoptr;
-- Node name is 'sddatard1' from file "zcont.tdf" line 19, column 25
-- Equation name is 'sddatard1', location is LC038, type is buried.
sddatard1 = DFFE( sddatard0 $ GND, _EQ033, VCC, VCC, VCC);
_EQ033 = sdtakt & starttr1 & stoptr;
-- Node name is 'sddatard2' from file "zcont.tdf" line 19, column 25
-- Equation name is 'sddatard2', location is LC110, type is buried.
sddatard2 = DFFE( sddatard1 $ GND, _EQ034, VCC, VCC, VCC);
_EQ034 = sdtakt & starttr1 & stoptr;
-- Node name is 'sddatard3' from file "zcont.tdf" line 19, column 25
-- Equation name is 'sddatard3', location is LC101, type is buried.
sddatard3 = DFFE( sddatard2 $ GND, _EQ035, VCC, VCC, VCC);
_EQ035 = sdtakt & starttr1 & stoptr;
-- Node name is 'sddatard4' from file "zcont.tdf" line 19, column 25
-- Equation name is 'sddatard4', location is LC071, type is buried.
sddatard4 = DFFE( sddatard3 $ GND, _EQ036, VCC, VCC, VCC);
_EQ036 = sdtakt & starttr1 & stoptr;
-- Node name is 'sddatard5' from file "zcont.tdf" line 19, column 25
-- Equation name is 'sddatard5', location is LC042, type is buried.
sddatard5 = DFFE( sddatard4 $ GND, _EQ037, VCC, VCC, VCC);
_EQ037 = sdtakt & starttr1 & stoptr;
-- Node name is 'sddatard6' from file "zcont.tdf" line 19, column 25
-- Equation name is 'sddatard6', location is LC040, type is buried.
sddatard6 = DFFE( sddatard5 $ GND, _EQ038, VCC, VCC, VCC);
_EQ038 = sdtakt & starttr1 & stoptr;
-- Node name is 'sddatard7' from file "zcont.tdf" line 19, column 25
-- Equation name is 'sddatard7', location is LC098, type is buried.
sddatard7 = DFFE( sddatard6 $ GND, _EQ039, VCC, VCC, VCC);
_EQ039 = sdtakt & starttr1 & stoptr;
-- Node name is 'sddatawr0' from file "zcont.tdf" line 19, column 9
-- Equation name is 'sddatawr0', location is LC060, type is buried.
sddatawr0 = DFFE( _EQ040 $ GND, _EQ041, VCC, VCC, VCC);
_EQ040 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus0 & dos & !iorq &
!stoptr & !wr
# adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus0 & dos & !iorq &
!starttr1 & !wr;
_EQ041 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq &
synchrotrig0 & !wr & _X052;
_X052 = EXP( starttr1 & stoptr);
-- Node name is 'sddatawr1' from file "zcont.tdf" line 19, column 9
-- Equation name is 'sddatawr1', location is LC063, type is buried.
sddatawr1 = DFFE( _EQ042 $ GND, _EQ043, VCC, VCC, VCC);
_EQ042 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus1 & dos & !iorq &
!stoptr & !wr
# adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus1 & dos & !iorq &
!starttr1 & !wr
# sddatawr0 & starttr1 & stoptr;
_EQ043 = !_LC044 & _X038 & _X039 & _X040 & _X041 & _X042 & _X043 &
_X044 & _X045 & _X046 & _X047 & _X048 & _X049 & _X050 &
_X051;
_X038 = EXP( sdtakt & starttr1 & stoptr);
_X039 = EXP(!stoptr & !synchrotrig0);
_X040 = EXP(!adr6 & !starttr1);
_X041 = EXP( adr5 & !stoptr);
_X042 = EXP(!adr1 & !stoptr);
_X043 = EXP(!adr6 & !stoptr);
_X044 = EXP(!dos & !stoptr);
_X045 = EXP(!adr0 & !stoptr);
_X046 = EXP(!starttr1 & !synchrotrig0);
_X047 = EXP(!adr1 & !starttr1);
_X048 = EXP(!stoptr & wr);
_X049 = EXP(!dos & !starttr1);
_X050 = EXP(!adr0 & !starttr1);
_X051 = EXP( iorq & !stoptr);
-- Node name is 'sddatawr2' from file "zcont.tdf" line 19, column 9
-- Equation name is 'sddatawr2', location is LC052, type is buried.
sddatawr2 = DFFE( _EQ044 $ GND, _EQ045, VCC, VCC, VCC);
_EQ044 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus2 & dos & !iorq &
!stoptr & !wr
# adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus2 & dos & !iorq &
!starttr1 & !wr
# sddatawr1 & starttr1 & stoptr;
_EQ045 = !_LC044 & _X038 & _X039 & _X040 & _X041 & _X042 & _X043 &
_X044 & _X045 & _X046 & _X047 & _X048 & _X049 & _X050 &
_X051;
_X038 = EXP( sdtakt & starttr1 & stoptr);
_X039 = EXP(!stoptr & !synchrotrig0);
_X040 = EXP(!adr6 & !starttr1);
_X041 = EXP( adr5 & !stoptr);
_X042 = EXP(!adr1 & !stoptr);
_X043 = EXP(!adr6 & !stoptr);
_X044 = EXP(!dos & !stoptr);
_X045 = EXP(!adr0 & !stoptr);
_X046 = EXP(!starttr1 & !synchrotrig0);
_X047 = EXP(!adr1 & !starttr1);
_X048 = EXP(!stoptr & wr);
_X049 = EXP(!dos & !starttr1);
_X050 = EXP(!adr0 & !starttr1);
_X051 = EXP( iorq & !stoptr);
-- Node name is 'sddatawr3' from file "zcont.tdf" line 19, column 9
-- Equation name is 'sddatawr3', location is LC054, type is buried.
sddatawr3 = DFFE( _EQ046 $ GND, _EQ047, VCC, VCC, VCC);
_EQ046 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus3 & dos & !iorq &
!stoptr & !wr
# adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus3 & dos & !iorq &
!starttr1 & !wr
# sddatawr2 & starttr1 & stoptr;
_EQ047 = !_LC044 & _X038 & _X039 & _X040 & _X041 & _X042 & _X043 &
_X044 & _X045 & _X046 & _X047 & _X048 & _X049 & _X050 &
_X051;
_X038 = EXP( sdtakt & starttr1 & stoptr);
_X039 = EXP(!stoptr & !synchrotrig0);
_X040 = EXP(!adr6 & !starttr1);
_X041 = EXP( adr5 & !stoptr);
_X042 = EXP(!adr1 & !stoptr);
_X043 = EXP(!adr6 & !stoptr);
_X044 = EXP(!dos & !stoptr);
_X045 = EXP(!adr0 & !stoptr);
_X046 = EXP(!starttr1 & !synchrotrig0);
_X047 = EXP(!adr1 & !starttr1);
_X048 = EXP(!stoptr & wr);
_X049 = EXP(!dos & !starttr1);
_X050 = EXP(!adr0 & !starttr1);
_X051 = EXP( iorq & !stoptr);
-- Node name is 'sddatawr4' from file "zcont.tdf" line 19, column 9
-- Equation name is 'sddatawr4', location is LC058, type is buried.
sddatawr4 = DFFE( _EQ048 $ GND, _EQ049, VCC, VCC, VCC);
_EQ048 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus4 & dos & !iorq &
!stoptr & !wr
# adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus4 & dos & !iorq &
!starttr1 & !wr
# sddatawr3 & starttr1 & stoptr;
_EQ049 = !_LC044 & _X038 & _X039 & _X040 & _X041 & _X042 & _X043 &
_X044 & _X045 & _X046 & _X047 & _X048 & _X049 & _X050 &
_X051;
_X038 = EXP( sdtakt & starttr1 & stoptr);
_X039 = EXP(!stoptr & !synchrotrig0);
_X040 = EXP(!adr6 & !starttr1);
_X041 = EXP( adr5 & !stoptr);
_X042 = EXP(!adr1 & !stoptr);
_X043 = EXP(!adr6 & !stoptr);
_X044 = EXP(!dos & !stoptr);
_X045 = EXP(!adr0 & !stoptr);
_X046 = EXP(!starttr1 & !synchrotrig0);
_X047 = EXP(!adr1 & !starttr1);
_X048 = EXP(!stoptr & wr);
_X049 = EXP(!dos & !starttr1);
_X050 = EXP(!adr0 & !starttr1);
_X051 = EXP( iorq & !stoptr);
-- Node name is 'sddatawr5' from file "zcont.tdf" line 19, column 9
-- Equation name is 'sddatawr5', location is LC059, type is buried.
sddatawr5 = DFFE( _EQ050 $ GND, _EQ051, VCC, VCC, VCC);
_EQ050 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus5 & dos & !iorq &
!stoptr & !wr
# adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus5 & dos & !iorq &
!starttr1 & !wr
# sddatawr4 & starttr1 & stoptr;
_EQ051 = !_LC044 & _X038 & _X039 & _X040 & _X041 & _X042 & _X043 &
_X044 & _X045 & _X046 & _X047 & _X048 & _X049 & _X050 &
_X051;
_X038 = EXP( sdtakt & starttr1 & stoptr);
_X039 = EXP(!stoptr & !synchrotrig0);
_X040 = EXP(!adr6 & !starttr1);
_X041 = EXP( adr5 & !stoptr);
_X042 = EXP(!adr1 & !stoptr);
_X043 = EXP(!adr6 & !stoptr);
_X044 = EXP(!dos & !stoptr);
_X045 = EXP(!adr0 & !stoptr);
_X046 = EXP(!starttr1 & !synchrotrig0);
_X047 = EXP(!adr1 & !starttr1);
_X048 = EXP(!stoptr & wr);
_X049 = EXP(!dos & !starttr1);
_X050 = EXP(!adr0 & !starttr1);
_X051 = EXP( iorq & !stoptr);
-- Node name is 'sddatawr6' from file "zcont.tdf" line 19, column 9
-- Equation name is 'sddatawr6', location is LC061, type is buried.
sddatawr6 = DFFE( _EQ052 $ GND, _EQ053, VCC, VCC, VCC);
_EQ052 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus6 & dos & !iorq &
!stoptr & !wr
# adr0 & adr1 & !adr5 & adr6 & !adr7 & dbus6 & dos & !iorq &
!starttr1 & !wr
# sddatawr5 & starttr1 & stoptr;
_EQ053 = !_LC044 & _X038 & _X039 & _X040 & _X041 & _X042 & _X043 &
_X044 & _X045 & _X046 & _X047 & _X048 & _X049 & _X050 &
_X051;
_X038 = EXP( sdtakt & starttr1 & stoptr);
_X039 = EXP(!stoptr & !synchrotrig0);
_X040 = EXP(!adr6 & !starttr1);
_X041 = EXP( adr5 & !stoptr);
_X042 = EXP(!adr1 & !stoptr);
_X043 = EXP(!adr6 & !stoptr);
_X044 = EXP(!dos & !stoptr);
_X045 = EXP(!adr0 & !stoptr);
_X046 = EXP(!starttr1 & !synchrotrig0);
_X047 = EXP(!adr1 & !starttr1);
_X048 = EXP(!stoptr & wr);
_X049 = EXP(!dos & !starttr1);
_X050 = EXP(!adr0 & !starttr1);
_X051 = EXP( iorq & !stoptr);
-- Node name is 'sdpower' = 'sdcontrwr0' from file "zcont.tdf" line 20, column 10
-- Equation name is 'sdpower', location is LC051, type is output.
sdpower = sdcontrwr0~NOT;
sdcontrwr0~NOT = DFFE( dbus0 $ VCC, _EQ054, VCC, reso, VCC);
_EQ054 = adr0 & adr1 & adr5 & adr6 & !adr7 & dos & !iorq & !wr;
-- Node name is 'sdtakto'
-- Equation name is 'sdtakto', location is LC099, type is output.
sdtakto = LCELL( _EQ055 $ GND);
_EQ055 = sdtakt & starttr1 & stoptr;
-- Node name is 'starttr' from file "zcont.tdf" line 21, column 16
-- Equation name is 'starttr', location is LC090, type is buried.
starttr = DFFE( GND $ VCC, _EQ056, stoptr, VCC, VCC);
_EQ056 = _X053 & _X054;
_X053 = EXP( adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq & !wr);
_X054 = EXP( adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq & !rd);
-- Node name is 'starttr1' from file "zcont.tdf" line 21, column 25
-- Equation name is 'starttr1', location is LC041, type is buried.
starttr1 = DFFE( starttr $ GND, sdtakt, stoptr, VCC, VCC);
-- Node name is 'stoptr' from file "zcont.tdf" line 21, column 35
-- Equation name is 'stoptr', location is LC034, type is buried.
stoptr = DFFE( GND $ GND, !sdcounter3, VCC, !_EQ057, VCC);
_EQ057 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq & _X055;
_X055 = EXP( rd & wr);
-- Node name is 'synchrotrig0' from file "zcont.tdf" line 21, column 54
-- Equation name is 'synchrotrig0', location is LC055, type is buried.
synchrotrig0 = DFFE( _EQ058 $ GND, stoptr, !synchrotrig1, VCC, VCC);
_EQ058 = adr0 & adr1 & !adr5 & adr6 & !adr7 & dos & !iorq & !wr;
-- Node name is 'synchrotrig1' from file "zcont.tdf" line 21, column 54
-- Equation name is 'synchrotrig1', location is LC050, type is buried.
synchrotrig1 = DFFE( synchrotrig0 $ GND, !sdtakt, VCC, VCC, VCC);
-- Node name is 'wrh'
-- Equation name is 'wrh', location is LC083, type is output.
wrh = LCELL( _EQ059 $ VCC);
_EQ059 = adr0 & !adr1 & !adr2 & dos & !iorq & m1 & rd & !wr;
-- Node name is '~243~1' from file "zcont.tdf" line 70, column 164
-- Equation name is '~243~1', location is LC084, type is buried.
-- synthesized logic cell
_LC084 = LCELL( _EQ060 $ _EQ061);
_EQ060 = !a8 & !keyd00 & _X056 & _X057 & _X058
# !a9 & !keyd01 & _X056 & _X057 & _X058
# !a10 & !keyd02 & _X056 & _X057 & _X058
# !a11 & !keyd03 & _X056 & _X057 & _X058;
_X056 = EXP(!a13 & !keyd05);
_X057 = EXP(!a12 & !keyd04);
_X058 = EXP(!a14 & !keyd06);
_EQ061 = _X056 & _X057 & _X058;
_X056 = EXP(!a13 & !keyd05);
_X057 = EXP(!a12 & !keyd04);
_X058 = EXP(!a14 & !keyd06);
-- Node name is '~244~1' from file "zcont.tdf" line 70, column 205
-- Equation name is '~244~1', location is LC123, type is buried.
-- synthesized logic cell
_LC123 = LCELL( _EQ062 $ VCC);
_EQ062 = !a15 & !keyd07;
-- Node name is '~258~1' from file "zcont.tdf" line 71, column 164
-- Equation name is '~258~1', location is LC077, type is buried.
-- synthesized logic cell
_LC077 = LCELL( _EQ063 $ _EQ064);
_EQ063 = !a8 & !keyd10 & _X059 & _X060 & _X061
# !a9 & !keyd11 & _X059 & _X060 & _X061
# !a10 & !keyd12 & _X059 & _X060 & _X061
# !a11 & !keyd13 & _X059 & _X060 & _X061;
_X059 = EXP(!a13 & !keyd15);
_X060 = EXP(!a12 & !keyd14);
_X061 = EXP(!a14 & !keyd16);
_EQ064 = _X059 & _X060 & _X061;
_X059 = EXP(!a13 & !keyd15);
_X060 = EXP(!a12 & !keyd14);
_X061 = EXP(!a14 & !keyd16);
-- Node name is '~259~1' from file "zcont.tdf" line 71, column 205
-- Equation name is '~259~1', location is LC121, type is buried.
-- synthesized logic cell
_LC121 = LCELL( _EQ065 $ VCC);
_EQ065 = !a15 & !keyd17;
-- Node name is '~273~1' from file "zcont.tdf" line 72, column 164
-- Equation name is '~273~1', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ066 $ _EQ067);
_EQ066 = !a8 & !keyd20 & _X062 & _X063 & _X064
# !a9 & !keyd21 & _X062 & _X063 & _X064
# !a10 & !keyd22 & _X062 & _X063 & _X064
# !a11 & !keyd23 & _X062 & _X063 & _X064;
_X062 = EXP(!a13 & !keyd25);
_X063 = EXP(!a12 & !keyd24);
_X064 = EXP(!a14 & !keyd26);
_EQ067 = _X062 & _X063 & _X064;
_X062 = EXP(!a13 & !keyd25);
_X063 = EXP(!a12 & !keyd24);
_X064 = EXP(!a14 & !keyd26);
-- Node name is '~288~1' from file "zcont.tdf" line 73, column 164
-- Equation name is '~288~1', location is LC020, type is buried.
-- synthesized logic cell
_LC020 = LCELL( _EQ068 $ _EQ069);
_EQ068 = !a8 & !keyd30 & _X065 & _X066 & _X067
# !a9 & !keyd31 & _X065 & _X066 & _X067
# !a10 & !keyd32 & _X065 & _X066 & _X067
# !a11 & !keyd33 & _X065 & _X066 & _X067;
_X065 = EXP(!a13 & !keyd35);
_X066 = EXP(!a12 & !keyd34);
_X067 = EXP(!a14 & !keyd36);
_EQ069 = _X065 & _X066 & _X067;
_X065 = EXP(!a13 & !keyd35);
_X066 = EXP(!a12 & !keyd34);
_X067 = EXP(!a14 & !keyd36);
-- Node name is '~289~1' from file "zcont.tdf" line 73, column 205
-- Equation name is '~289~1', location is LC016, type is buried.
-- synthesized logic cell
_LC016 = LCELL( _EQ070 $ VCC);
_EQ070 = !a15 & !keyd37;
-- Node name is '~303~1' from file "zcont.tdf" line 74, column 164
-- Equation name is '~303~1', location is LC018, type is buried.
-- synthesized logic cell
_LC018 = LCELL( _EQ071 $ _EQ072);
_EQ071 = !a8 & !keyd40 & _X068 & _X069 & _X070
# !a9 & !keyd41 & _X068 & _X069 & _X070
# !a10 & !keyd42 & _X068 & _X069 & _X070
# !a11 & !keyd43 & _X068 & _X069 & _X070;
_X068 = EXP(!a13 & !keyd45);
_X069 = EXP(!a12 & !keyd44);
_X070 = EXP(!a14 & !keyd46);
_EQ072 = _X068 & _X069 & _X070;
_X068 = EXP(!a13 & !keyd45);
_X069 = EXP(!a12 & !keyd44);
_X070 = EXP(!a14 & !keyd46);
-- Node name is '~304~1' from file "zcont.tdf" line 74, column 205
-- Equation name is '~304~1', location is LC014, type is buried.
-- synthesized logic cell
_LC014 = LCELL( _EQ073 $ VCC);
_EQ073 = !a15 & !keyd47;
-- Node name is '~531~1' from file "zcont.tdf" line 182, column 22
-- Equation name is '~531~1', location is LC044, type is buried.
-- synthesized logic cell
_LC044 = LCELL( _EQ074 $ GND);
_EQ074 = adr7 & !starttr1
# adr5 & !starttr1
# !starttr1 & wr
# iorq & !starttr1
# adr7 & !stoptr;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X002 occurs in LABs G, H
-- _X023 occurs in LABs C, H
-- _X038 occurs in LABs D, G
Project Information c:\111\cpld_zc\zcont.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = on
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:32
Timing SNF Extractor 00:00:00
Assembler 00:00:03
-------------------------- --------
Total Time 00:00:36
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,770K