Rev 674 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 674 | Rev 684 | ||
|---|---|---|---|
| Line 228... | Line 228... | ||
| 228 | reg [1:0] memwr_reg_fclk; |
228 | reg [1:0] memwr_reg_fclk; |
| 229 | 229 | ||
| 230 | 230 | ||
| 231 | wire [7:0] loa; |
231 | wire [7:0] loa; |
| 232 | 232 | ||
| 233 | wire portfe_wr; |
- | |
| 234 | 233 | ||
| 235 | 234 | ||
| 236 | 235 | ||
| 237 | wire ideout_hi_wr; |
236 | wire ideout_hi_wr; |
| 238 | wire idein_lo_rd; |
237 | wire idein_lo_rd; |
| Line 276... | Line 275... | ||
| 276 | 275 | ||
| 277 | reg [7:0] savport [3:0]; |
276 | reg [7:0] savport [3:0]; |
| 278 | reg [5:0] vgFF; |
277 | reg [5:0] vgFF; |
| 279 | 278 | ||
| 280 | 279 | ||
| - | 280 | reg [7:0] up_lastwritten; |
|
| 281 | 281 | ||
| 282 | 282 | ||
| 283 | assign shadow = dos || shadow_en_reg; |
283 | assign shadow = dos || shadow_en_reg; |
| 284 | 284 | ||
| 285 | 285 | ||
| Line 290... | Line 290... | ||
| 290 | assign loa=a[7:0]; |
290 | assign loa=a[7:0]; |
| 291 | 291 | ||
| 292 | always @* |
292 | always @* |
| 293 | begin |
293 | begin |
| 294 | if( (loa==PORTFE) || (loa==PORTF6) || |
294 | if( (loa==PORTFE) || (loa==PORTF6) || |
| 295 | (loa==PORTFD) || |
295 | (loa==PORTFD) || (loa==8'hFC) || |
| 296 | 296 | ||
| 297 | `IS_PORT_NIDE(loa) || |
297 | `IS_PORT_NIDE(loa) || |
| 298 | // (loa==NIDE10) || (loa==NIDE11) || (loa==NIDE30) || (loa==NIDE50) || (loa==NIDE70) || |
298 | // (loa==NIDE10) || (loa==NIDE11) || (loa==NIDE30) || (loa==NIDE50) || (loa==NIDE70) || |
| 299 | // (loa==NIDE90) || (loa==NIDEB0) || (loa==NIDED0) || (loa==NIDEF0) || (loa==NIDEC8) || |
299 | // (loa==NIDE90) || (loa==NIDEB0) || (loa==NIDED0) || (loa==NIDEF0) || (loa==NIDEC8) || |
| 300 | 300 | ||
| Line 450... | Line 450... | ||
| 450 | endcase |
450 | endcase |
| 451 | end |
451 | end |
| 452 | 452 | ||
| 453 | 453 | ||
| 454 | 454 | ||
| 455 | assign portfe_wr = (((loa==PORTFE) || (loa==PORTF6)) && port_wr); |
455 | assign portfd_wr = ( (loa==PORTFD || loa==8'hFC) && port_wr); |
| 456 | assign portfd_wr = ( (loa==PORTFD) && port_wr); |
- | |
| 457 | 456 | ||
| 458 | // F7 ports (like EFF7) are accessible in shadow mode but at addresses like EEF7, DEF7, BEF7 so that |
457 | // F7 ports (like EFF7) are accessible in shadow mode but at addresses like EEF7, DEF7, BEF7 so that |
| 459 | // there are no conflicts in shadow mode with ATM xFF7 and x7F7 ports |
458 | // there are no conflicts in shadow mode with ATM xFF7 and x7F7 ports |
| 460 | assign portf7_wr = ( (loa==PORTF7) && (a[8]==1'b1) && port_wr && (!shadow) ) || |
459 | assign portf7_wr = ( (loa==PORTF7) && (a[8]==1'b1) && port_wr && (!shadow) ) || |
| 461 | ( (loa==PORTF7) && (a[8]==1'b0) && port_wr && shadow ) ; |
460 | ( (loa==PORTF7) && (a[8]==1'b0) && port_wr && shadow ) ; |
| Line 492... | Line 491... | ||
| 492 | 491 | ||
| 493 | 492 | ||
| 494 | //border port FE |
493 | //border port FE |
| 495 | wire portwe_wr_fclk; |
494 | wire portwe_wr_fclk; |
| 496 | 495 | ||
| 497 | assign portfe_wr_fclk = (((loa==PORTFE) || (loa==PORTF6)) && port_wr_fclk); |
496 | assign portfe_wr_fclk = (((loa==PORTFE) || (loa==PORTF6) || (loa==8'hFC)) && port_wr_fclk); |
| 498 | 497 | ||
| 499 | always @(posedge fclk) |
498 | always @(posedge fclk) |
| 500 | if( portfe_wr_fclk ) |
499 | if( portfe_wr_fclk ) |
| 501 | border <= { ~a[3], din[2:0] }; |
500 | border <= { ~a[3], din[2:0] }; |
| 502 | 501 | ||
| Line 947... | Line 946... | ||
| 947 | 946 | ||
| 948 | 947 | ||
| 949 | 948 | ||
| 950 | 949 | ||
| 951 | // ULAPLUS ports |
950 | // ULAPLUS ports |
| 952 | reg [7:0] up_lastwritten; |
- | |
| 953 | reg up_select; // 0 -- ena/dis, 1 -- palette write |
951 | reg up_select; // 0 -- ena/dis, 1 -- palette write |
| 954 | // |
952 | // |
| 955 | wire up_wr = port_wr_fclk && (loa==ULAPLUS); |
953 | wire up_wr = port_wr_fclk && (loa==ULAPLUS); |
| 956 | // |
954 | // |
| 957 | always @(posedge fclk) |
955 | always @(posedge fclk) |