Rev 668 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 668 | Rev 826 | ||
|---|---|---|---|
| Line 1... | Line 1... | ||
| 1 | // ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014 |
1 | // ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014,2019 |
| 2 | // |
2 | // |
| 3 | // fpga SPI slave device -- AVR controlled. |
3 | // fpga SPI slave device -- AVR controlled. |
| 4 | 4 | ||
| 5 | /* |
5 | /* |
| 6 | This file is part of ZX-Evo Base Configuration firmware. |
6 | This file is part of ZX-Evo Base Configuration firmware. |
| Line 54... | Line 54... | ||
| 54 | input wire wait_rnw, |
54 | input wire wait_rnw, |
| 55 | 55 | ||
| 56 | output wire wait_end, |
56 | output wire wait_end, |
| 57 | 57 | ||
| 58 | output wire [ 7:0] config0, // config bits for overall system |
58 | output wire [ 7:0] config0, // config bits for overall system |
| - | 59 | output wire [ 7:0] config1, // |
|
| 59 | 60 | ||
| 60 | output wire genrst, // positive pulse, causes Z80 reset |
61 | output wire genrst, // positive pulse, causes Z80 reset |
| 61 | 62 | ||
| 62 | output wire sd_lock_out, // SDcard control iface |
63 | output wire sd_lock_out, // SDcard control iface |
| 63 | input wire sd_lock_in, // |
64 | input wire sd_lock_in, // |
| Line 107... | Line 108... | ||
| 107 | 108 | ||
| 108 | 109 | ||
| 109 | 110 | ||
| 110 | // register selectors |
111 | // register selectors |
| 111 | wire sel_kbdreg, sel_kbdstb, sel_musxcr, sel_musycr, sel_musbtn, sel_kj, |
112 | wire sel_kbdreg, sel_kbdstb, sel_musxcr, sel_musycr, sel_musbtn, sel_kj, |
| 112 | sel_rstreg, sel_waitreg, sel_gluadr, sel_comadr, sel_cfg0, |
113 | sel_rstreg, sel_waitreg, sel_gluadr, sel_comadr, sel_cfg0, sel_cfg1, |
| 113 | sel_sddata, sel_sdctrl; |
114 | sel_sddata, sel_sdctrl; |
| 114 | 115 | ||
| 115 | // keyboard register |
116 | // keyboard register |
| 116 | reg [39:0] kbd_reg; |
117 | reg [39:0] kbd_reg; |
| 117 | 118 | ||
| Line 122... | Line 123... | ||
| 122 | 123 | ||
| 123 | // wait data out register |
124 | // wait data out register |
| 124 | reg [7:0] wait_reg; |
125 | reg [7:0] wait_reg; |
| 125 | 126 | ||
| 126 | // |
127 | // |
| 127 | reg [7:0] cfg0_reg_out; // one for shifting, second for storing values |
128 | reg [7:0] cfg0_reg_out; |
| - | 129 | reg [7:0] cfg1_reg_out; |
|
| 128 | 130 | ||
| 129 | 131 | ||
| 130 | // SDcard access registers |
132 | // SDcard access registers |
| 131 | reg [7:0] sddata; // output to SDcard |
133 | reg [7:0] sddata; // output to SDcard |
| 132 | reg [1:0] sdctrl; // SDcard control (CS_n and lock) |
134 | reg [1:0] sdctrl; // SDcard control (CS_n and lock) |
| Line 196... | Line 198... | ||
| 196 | // |
198 | // |
| 197 | assign sel_waitreg = ( (regnum[7:4]==4'h4) && (regnum[1:0]==2'b00) ); // $40 |
199 | assign sel_waitreg = ( (regnum[7:4]==4'h4) && (regnum[1:0]==2'b00) ); // $40 |
| 198 | assign sel_gluadr = ( (regnum[7:4]==4'h4) && (regnum[1:0]==2'b01) ); // $41 |
200 | assign sel_gluadr = ( (regnum[7:4]==4'h4) && (regnum[1:0]==2'b01) ); // $41 |
| 199 | assign sel_comadr = ( (regnum[7:4]==4'h4) && (regnum[1:0]==2'b10) ); // $42 |
201 | assign sel_comadr = ( (regnum[7:4]==4'h4) && (regnum[1:0]==2'b10) ); // $42 |
| 200 | // |
202 | // |
| 201 | assign sel_cfg0 = (regnum[7:4]==4'h5); // $50 |
203 | assign sel_cfg0 = (regnum[7:4]==4'h5 && regnum[0]==1'b0); // $50 |
| - | 204 | assign sel_cfg1 = (regnum[7:4]==4'h5 && regnum[0]==1'b1); // $51 |
|
| 202 | // |
205 | // |
| 203 | assign sel_sddata = ( (regnum[7:4]==4'h6) && !regnum[0] ); // $60 |
206 | assign sel_sddata = ( (regnum[7:4]==4'h6) && !regnum[0] ); // $60 |
| 204 | assign sel_sdctrl = ( (regnum[7:4]==4'h6) && regnum[0] ); // $61 |
207 | assign sel_sdctrl = ( (regnum[7:4]==4'h6) && regnum[0] ); // $61 |
| 205 | 208 | ||
| 206 | 209 | ||
| Line 219... | Line 222... | ||
| 219 | // wait read data shift-in |
222 | // wait read data shift-in |
| 220 | if( !scs_n && sel_waitreg && sck_01 ) |
223 | if( !scs_n && sel_waitreg && sck_01 ) |
| 221 | wait_reg[7:0] <= { sdo, wait_reg[7:1] }; |
224 | wait_reg[7:0] <= { sdo, wait_reg[7:1] }; |
| 222 | 225 | ||
| 223 | // config shift-in |
226 | // config shift-in |
| 224 | if( !scs_n && sel_cfg0 && sck_01 ) |
227 | if( !scs_n && (sel_cfg0 || sel_cfg1) && sck_01 ) |
| 225 | common_reg[7:0] <= { sdo, common_reg[7:1] }; |
228 | common_reg[7:0] <= { sdo, common_reg[7:1] }; |
| 226 | 229 | ||
| 227 | // config output |
230 | // config output |
| 228 | if( scs_n_01 && sel_cfg0 ) |
231 | if( scs_n_01 && sel_cfg0 ) |
| 229 | cfg0_reg_out <= common_reg; |
232 | cfg0_reg_out <= common_reg; |
| - | 233 | if( scs_n_01 && sel_cfg1 ) |
|
| - | 234 | cfg1_reg_out <= common_reg; |
|
| 230 | 235 | ||
| 231 | // SD data shift-in |
236 | // SD data shift-in |
| 232 | if( !scs_n && sel_sddata && sck_01 ) |
237 | if( !scs_n && sel_sddata && sck_01 ) |
| 233 | common_reg[7:0] <= { sdo, common_reg[7:1] }; |
238 | common_reg[7:0] <= { sdo, common_reg[7:1] }; |
| 234 | 239 | ||
| Line 262... | Line 267... | ||
| 262 | 267 | ||
| 263 | assign wait_read = wait_reg; |
268 | assign wait_read = wait_reg; |
| 264 | assign wait_end = sel_waitreg && scs_n_01; |
269 | assign wait_end = sel_waitreg && scs_n_01; |
| 265 | 270 | ||
| 266 | assign config0 = cfg0_reg_out; |
271 | assign config0 = cfg0_reg_out; |
| - | 272 | assign config1 = cfg1_reg_out; |
|
| 267 | 273 | ||
| 268 | 274 | ||
| 269 | 275 | ||
| 270 | // SD control output |
276 | // SD control output |
| 271 | assign sd_lock_out = sdctrl[1]; |
277 | assign sd_lock_out = sdctrl[1]; |