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1126 savelij 1 
		ifndef	__regf1680inc
2 
__regf1680inc	equ	1
3 
                save
4 
		listing off		; no listing over this file
5 
 
6 
;****************************************************************************
7 
;*                                                                          *
8 
;*   AS 1.42 - File F1680.INC                                               *
9 
;*                                                                          *
10 
;*   Contains Bit & Register Definitions for Z8encore F1680                 *
11 
;*   Source: Z8 Encore! XP F1680 Series Product Specification, PS025016-1013*
12 
;*                                                                          *
13 
;****************************************************************************
14 
 
15 
		include	"ez8com.inc"
16 
 
17 
;----------------------------------------------------------------------------
18 
; System Control
19 
 
20 
PWRCTL0		sfr	0f80h		; Power Control 0
21 
TRAM		__z8bit	PWRCTL0,7	;  Low-Power Operational Amplifier Disable
22 
LVD_VBO		__z8bit	PWRCTL0,4	;  Low-Voltage Detection/Voltage Brown-Out Detector Disable
23 
TEMP		__z8bit	PWRCTL0,3	;  Temperature Sensor Disable
24 
COMP0		__z8bit	PWRCTL0,1	;  Comparator 0 Disable
25 
COMP1		__z8bit	PWRCTL0,0	;  Comparator 1 Disable
26 
 
27 
OSCCTL0		sfr	0f86h		; Oscillator Control 0
28 
INTEN		__z8bit	OSCCTL0,7	;  Internal Precision Oscillator Enable
29 
XTLEN		__z8bit	OSCCTL0,6	;  Crystal Oscillator Enable
30 
WDTEN		__z8bit	OSCCTL0,5	;  Watchdog Timer Oscillator Enable
31 
POFEN		__z8bit	OSCCTL0,4	;  Primary Oscillator Failure Detection Enable
32 
WDFEN		__z8bit	OSCCTL0,3	;  Watchdog Timer Oscillator Failure Detection Enable
33 
SCKSEL		__z8bfield OSCCTL0,0,3	;  System Clock Oscillator Select
34 
OSCCTL1		sfr	0f87h		; Oscillator Control 1
35 
SECEN		__z8bit	OSCCTL1,7	;  Secondary Oscillator Enable
36 
SECRDY		__z8bit	OSCCTL1,6	;  Secondary Oscillator Ready Flag
37 
INTSEL		__z8bfield OSCCTL1,0,3	;  Internal Precision Oscillator Frequency Select
38 
 
39 
TRMADR		sfr	0ff6h		; Trim Bit Address
40 
TRMDR		sfr	0ff7h		; Trim Data
41 
 
42 
;----------------------------------------------------------------------------
43 
; Flash Options
44 
 
45 
OPTIONS0	label	0000h
46 
WDT_RES		__z8cbit OPTIONS0,7	;  Watchdog Timer Reset
47 
WDT_AO		__z8cbit OPTIONS0,6	;  Watchdog Timer Always On
48 
OSC_SEL		__z8cbfield OPTIONS0,4,2 ;  Oscillator Mode Selection
49 
VBO_AO		__z8cbit OPTIONS0,3	;  Voltage Brown-Out Protection Always On
50 
FRP		__z8cbit OPTIONS0,2	;  (Flash) Read Protect
51 
PRAM_M		__z8cbit OPTIONS0,1	;  On-Chip Program RAM Mode Select
52 
FWP		__z8cbit OPTIONS0,0	;  Flash Write Protect
53 
OPTIONS1	label	0001h
54 
EXTLTMG		__z8cbfield OPTIONS1,6,2 ;  External Crystal Reset Timing
55 
FLASH_WR_PRO_EN	__z8cbit OPTIONS1,5	;  Flash Write Operation Protect
56 
EXTL_AO		__z8cbit OPTIONS1,4	;  External Crystal Always ON
57 
X2_Mode		__z8cbit OPTIONS1,1	;  Secondary Crystal Mode Select
58 
X2TL_AO		__z8cbit OPTIONS1,0	;  Secondary Crystal Always On
59 
 
60 
;----------------------------------------------------------------------------
61 
; Interrupts Vectors
62 
 
63 
RESET_vect	label	0002h		; Reset (not an interrupt)
64 
WDT_vect	label	0004h		; Watchdog Timer
65 
ILL_INST_vect	label	0006h		; Illegal Instruction Trap (not an interrupt)
66 
TIMER2_vect	label	0008h		; Timer 2
67 
TIMER1_vect	label	000ah		; Timer 1
68 
TIMER0_vect	label	000ch		; Timer 0
69 
UART0_RX_vect	label	000eh		; UART 0 Receiver
70 
UART0_TX_vect	label	0010h		; UART 0 Transmitter
71 
I2C_vect	label	0012h		; I2C
72 
SPI_vect	label	0014h		; SPI
73 
ADC_vect	label	0016h		; ADC
74 
A7_vect		label	0018h		; Port A7, selectable rising or falling input edge, or LVD
75 
A6_vect		label	001ah		; Port A6, selectable rising or falling input edge or Comparator 0 Output
76 
A5_vect		label	001ch		; Port A5, selectable rising or falling input edge or Comparator 1 Output
77 
A4_vect		label	001eh		; Port A4 or Port D4, selectable rising or falling input edge
78 
A3_vect		label	0020h		; Port A3 or Port D3, selectable rising or falling input edge
79 
A2_vect		label	0022h		; Port A2 or Port D2, selectable rising or falling input edge
80 
A1_vect		label	0024h		; Port A1 or Port D1, selectable rising or falling input edge
81 
A0_vect		label	0026h		; Port A0, selectable rising or falling input edge
82 
MCT_vect	label	002ah		; Multi-Channel Timer
83 
UART1_RX_vect	label	002ch		; UART 1 Receiver
84 
UART1_TX_vect	label	002eh		; UART 1 Transmitter
85 
C3_vect		label	0030h		; Port C3, both input edges
86 
C2_vect		label	0032h		; Port C2, both input edges
87 
C1_vect		label	0034h		; Port C1, both input edges
88 
C0_vect		label	0036h		; Port C0, both input edges
89 
 
90 
;----------------------------------------------------------------------------
91 
; Interrupts
92 
 
93 
__defirq	macro	NUM,Base
94 
IRQ{NUM}	sfr	Base+0		; Interrupt Request n
95 
IRQ{NUM}ENH	sfr	Base+1		; IRQn Enable High Bit
96 
IRQ{NUM}ENL	sfr	Base+2		; IRQn Enable Low Bit
97 
		endm
98 
 
99 
		__defirq "0",0fc0h
100 
		__defirq "1",0fc3h
101 
		__defirq "2",0fc6h
102 
 
103 
T2I		__z8bit	IRQ0,7		;  Timer 2 Interrupt Request
104 
T1I		__z8bit IRQ0,6		;  Timer 1 Interrupt Request
105 
T0I		__z8bit IRQ0,5		;  Timer 0 Interrupt Request
106 
U0RXI		__z8bit	IRQ0,4		;  UART 0 Receiver Interrupt Request
107 
U0TXI		__z8bit	IRQ0,3		;  UART 0 Transmitter Interrupt Request
108 
I2CI		__z8bit	IRQ0,2		;  I2C Interrupt Request
109 
SPII		__z8bit	IRQ0,1		;  SPI Interrupt Request
110 
ADCI		__z8bit IRQ0,0		;  ADC Interrupt Request
111 
 
112 
T2ENH		__z8bit	IRQ0ENH,7	;  Timer 2 Interrupt Enable & Priority
113 
T2ENL		__z8bit	IRQ0ENL,7
114 
T1ENH		__z8bit	IRQ0ENH,6	;  Timer 1 Interrupt Enable & Priority
115 
T1ENL		__z8bit	IRQ0ENL,6
116 
T0ENH		__z8bit	IRQ0ENH,5	;  Timer 0 Interrupt Enable & Priority
117 
T0ENL		__z8bit	IRQ0ENL,5
118 
U0RENH		__z8bit	IRQ0ENH,4	;  UART 0 Receive Interrupt Enable & Priority
119 
U0RENL		__z8bit	IRQ0ENL,4
120 
U0TENH		__z8bit	IRQ0ENH,3	;  UART 0 Transmit Interrupt Enable & Priority
121 
U0TENL		__z8bit	IRQ0ENL,3
122 
I2CENH		__z8bit	IRQ0ENH,2	;  I2C Interrupt Enable & Priority
123 
I2CENL		__z8bit	IRQ0ENL,2
124 
SPIENH		__z8bit	IRQ0ENH,1	;  SPI Interrupt Enable & Priority
125 
SPIENL		__z8bit	IRQ0ENL,1
126 
ADCENH		__z8bit	IRQ0ENH,0	;  ADC Interrupt Enable & Priority
127 
ADCENL		__z8bit	IRQ0ENL,0
128 
 
129 
PA7VI		__z8bit	IRQ1,7		;  Port A7 or LVD Interrupt Request
130 
PA6CI		__z8bit	IRQ1,6		;  Port A6 or Comparator 0 Interrupt Request
131 
PA5CI		__z8bit	IRQ1,5		;  Port A5 or Comparator 1 Interrupt Request
132 
PAD4I		__z8bit	IRQ1,4		;  Port A4 or Port D4 Interrupt Request
133 
PAD3I		__z8bit	IRQ1,3		;  Port A3 or Port D3 Interrupt Request
134 
PAD2I		__z8bit	IRQ1,2		;  Port A2 or Port D2 Interrupt Request
135 
PAD1I		__z8bit	IRQ1,1		;  Port A1 or Port D1 Interrupt Request
136 
PA0I		__z8bit	IRQ1,0		;  Port A0 Interrupt Request
137 
 
138 
PA7VENH		__z8bit	IRQ1ENH,7	;  Port A7 or LVD Interrupt Enable & Priority
139 
PA7VENL		__z8bit	IRQ1ENL,7
140 
PA6ENH		__z8bit	IRQ1ENH,6	;  Port A6 or Comparator 0 Interrupt Enable & Priority
141 
PA6ENL		__z8bit	IRQ1ENL,6
142 
PA5ENH		__z8bit	IRQ1ENH,5	;  Port A5 or Comparator 1 Interrupt Enable & Priority
143 
PA5ENL		__z8bit	IRQ1ENL,5
144 
PA4ENH		__z8bit	IRQ1ENH,4	;  Port A4 or Port D4 Interrupt Enable & Priority
145 
PA4ENL		__z8bit	IRQ1ENL,4
146 
PA3ENH		__z8bit	IRQ1ENH,3	;  Port A3 or Port D3 Interrupt Enable & Priority
147 
PA3ENL		__z8bit	IRQ1ENL,3
148 
PA2ENH		__z8bit	IRQ1ENH,2	;  Port A2 or Port D2 Interrupt Enable & Priority
149 
PA2ENL		__z8bit	IRQ1ENL,2
150 
PA1ENH		__z8bit	IRQ1ENH,1	;  Port A1 or Port D1 Interrupt Enable & Priority
151 
PA1ENL		__z8bit	IRQ1ENL,1
152 
PA0ENH		__z8bit	IRQ1ENH,0	;  Port A0 Interrupt Enable & Priority
153 
PA0ENL		__z8bit	IRQ1ENL,0
154 
 
155 
MCTI		__z8bit	IRQ2,6		;  Multi-Channel Timer Interrupt Request
156 
U1RXI		__z8bit	IRQ2,5		;  UART 1 Receiver Interrupt Request
157 
U1TXI		__z8bit	IRQ2,4		;  UART 1 Transmitter Interrupt Request
158 
PC3I		__z8bit	IRQ2,3		;  Port C3 Interrupt Request
159 
PC2I		__z8bit	IRQ2,2		;  Port C2 Interrupt Request
160 
PC1I		__z8bit	IRQ2,1		;  Port C1 Interrupt Request
161 
PC0I		__z8bit	IRQ2,0		;  Port C0 Interrupt Request
162 
 
163 
MCTENH		__z8bit	IRQ2ENH,6	;  Multi-Channel Timer Interrupt Enable & Priority
164 
MCTENL		__z8bit	IRQ2ENL,6
165 
U1RENH		__z8bit	IRQ2ENH,5	;  UART 1 Receive Interrupt Enable & Priority
166 
U1RENL		__z8bit	IRQ2ENL,5
167 
U1TENH		__z8bit	IRQ2ENH,4	;  UART 1 Transmit Interrupt Enable & Priority
168 
U1TENL		__z8bit	IRQ2ENL,4
169 
C3ENH		__z8bit	IRQ2ENH,3	;  Port C3 Interrupt Enable & Priority
170 
C3ENL		__z8bit	IRQ2ENL,3
171 
C2ENH		__z8bit	IRQ2ENH,2	;  Port C2 Interrupt Enable & Priority
172 
C2ENL		__z8bit	IRQ2ENL,2
173 
C1ENH		__z8bit	IRQ2ENH,1	;  Port C1 Interrupt Enable & Priority
174 
C1ENL		__z8bit	IRQ2ENL,1
175 
C0ENH		__z8bit	IRQ2ENH,0	;  Port C0 Interrupt Enable & Priority
176 
C0ENL		__z8bit	IRQ2ENL,0
177 
 
178 
IRQES		sfr	0fcdh		; Interrupt Edge Select
179 
IRQSS		sfr	0fceh		; Shared Interrupt Select Register
180 
PA7VS		__z8bit	IRQSS,7		;  PA7/LVD Selection
181 
PA6CS		__z8bit	IRQSS,6		;  PA6/Comparator 0 Selection
182 
PA5CS		__z8bit	IRQSS,5		;  PA5/Comparator 1 Selection
183 
PAD4S		__z8bit	IRQSS,4		;  PA4/PD4 Selection
184 
PAD3S		__z8bit	IRQSS,3		;  PA3/PD3 Selection
185 
PAD2S		__z8bit	IRQSS,2		;  PA2/PD2 Selection
186 
PAD1S		__z8bit	IRQSS,1		;  PA1/PD1 Selection
187 
IRQCTL		sfr	0fcfh		; Interrupt Control
188 
IRQE		__z8bit	IRQCTL,7	;  Interrupt Request Enable
189 
 
190 
;----------------------------------------------------------------------------
191 
; Flash Memory Control
192 
 
193 
FCTL		sfr	0ff8h		; Flash Control
194 
FCMD		__z8bfield FCTL,0,8	;  Flash Command
195 
FSTAT		sfr	0ff8h		; Flash Status
196 
FPS		sfr	0ff9h		; Flash Page Select
197 
INFO_EN		__z8bit	FPS,7		;  Information Area Enable
198 
PAGE		__z8bfield FPS,0,7	;  Page Select
199 
FPROT		sfr	0ff9h		; Flash Sector Protect
200 
FFREQH		sfr	0ffah		; Flash Programming Frequency High Byte
201 
FFREQL		sfr	0ffbh		; Flash Programming Frequency Low Byte
202 
FFREQ		sfr	FFREQH
203 
 
204 
;----------------------------------------------------------------------------
205 
; GPIO
206 
 
207 
		__defgpio "A",0fd0h
208 
		__defgpio "B",0fd4h
209 
		__defgpio "C",0fd8h
210 
		__defgpio "D",0fdch
211 
		__defgpio "E",0fe0h
212 
 
213 
;----------------------------------------------------------------------------
214 
; LED Controller
215 
 
216 
LEDEN		sfr	0f82h		; LED Drive Enable
217 
LEDLVLH		sfr	0f83h		; LED Drive Level High
218 
LEDLVLL		sfr	0f84h		; LED Drive Level Low
219 
 
220 
;----------------------------------------------------------------------------
221 
; Timer
222 
 
223 
__defmytimer	macro	NUM,Base,Base2,Base3
224 
		__deftimer NUM,Base,1,1
225 
T{NUM}MODE3	equ	T{NUM}MODEHI
226 
T{NUM}PWM1H	sfr	Base2+0		; Timer PWM1 High Byte
227 
T{NUM}PWM1L	sfr	Base2+1		; Timer PWM1 Low Byte
228 
T{NUM}PWM1	sfr	T{NUM}PWM1H
229 
T{NUM}CTL2	sfr	Base2+2		; Timer Control 2
230 
T{NUM}PWM0UE	__z8bit	T{NUM}CTL2,5	;  PWM0 Update Enable
231 
T{NUM}TPOLHI	__z8bit	T{NUM}CTL2,4	;  Timer Input/Output Polarity High Bit
232 
T{NUM}TCLKS	__z8bit	T{NUM}CTL2,0	;  Timer Clock Source
233 
T{NUM}STAT	sfr	Base2+3		; Timer Status
234 
T{NUM}NEF	__z8bit	T{NUM}STAT,7	;  Noise Event Flag
235 
T{NUM}PWM1EO	__z8bit	T{NUM}STAT,5	;  PWM 1 Event Overrun
236 
T{NUM}PWM0EO	__z8bit	T{NUM}STAT,4	;  PWM 0 Event Overrun
237 
T{NUM}RTOEF	__z8bit	T{NUM}STAT,3	;  Reload Time-Out Event Flag
238 
T{NUM}PWM1EF	__z8bit	T{NUM}STAT,1	;  PWM 1 Event Flag
239 
T{NUM}PWM0EF	__z8bit	T{NUM}STAT,0	;  PWM 0 Event Flag
240 
T{NUM}NFC	sfr	Base3+0		; Timer Noise Filter Control
241 
T{NUM}NFEN	__z8bit	T{NUM}NFC,7	;  Noise Filter Enable
242 
T{NUM}NFCTL	__z8bfield T{NUM}NFC,4,3 ;  Noise Filter Control
243 
		endm
244 
 
245 
		__defmytimer "0",0f00h,0f20h,0f2ch
246 
		__defmytimer "1",0f08h,0f24h,0f2dh
247 
		__defmytimer "2",0f10h,0f28h,0f2eh
248 
 
249 
;----------------------------------------------------------------------------
250 
; Multi-Channel Timer
251 
 
252 
		__defmct
253 
 
254 
;----------------------------------------------------------------------------
255 
; LIN UART
256 
 
257 
__deflinuart	macro	NUM,Base
258 
U{NUM}TXD	sfr	Base+0		; LIN UART Transmit Data
259 
U{NUM}RXD	sfr	Base+0		; LIN UART Receive Data
260 
U{NUM}STAT0	sfr	Base+1		; LIN UART Status 0
261 
U{NUM}RDA	__z8bit	U{NUM}STAT0,7	;  Receive Data Available (LIN+UART)
262 
U{NUM}PE	__z8bit	U{NUM}STAT0,6	;  Parity Error (UART)
263 
U{NUM}PLE	__z8bit	U{NUM}STAT0,6	;  Physical Layer Error (LIN)
264 
U{NUM}OE	__z8bit	U{NUM}STAT0,5	;  Overrun Error (LIN+UART)
265 
U{NUM}FE	__z8bit	U{NUM}STAT0,4	;  Framing Error (LIN+UART)
266 
U{NUM}BRKD	__z8bit	U{NUM}STAT0,3	;  Break Detect (LIN+UART)
267 
U{NUM}TDRE	__z8bit	U{NUM}STAT0,2	;  Transmitter Data Register Empty (LIN+UART)
268 
U{NUM}TXE	__z8bit	U{NUM}STAT0,1	;  Transmitter Empty (LIN+UART)
269 
U{NUM}CTS	__z8bit	U{NUM}STAT0,0	;  Clear to Send Signal (UART)
270 
U{NUM}ATB	__z8bit	U{NUM}STAT0,0	;  LIN Slave Autobaud Complete (LIN)
271 
U{NUM}CTL0	sfr	Base+2		; LIN UART Control 0
272 
U{NUM}TEN	__z8bit	U{NUM}CTL0,7	;  Transmit Enable
273 
U{NUM}REN	__z8bit	U{NUM}CTL0,6	;  Receive Enable
274 
U{NUM}CTSE	__z8bit	U{NUM}CTL0,5	;  Clear To Send Enable
275 
U{NUM}PEN	__z8bit	U{NUM}CTL0,4	;  Parity Enable
276 
U{NUM}PSEL	__z8bit	U{NUM}CTL0,3	;  Parity Select
277 
U{NUM}SBRK	__z8bit	U{NUM}CTL0,2	;  Send Break
278 
U{NUM}STOP	__z8bit	U{NUM}CTL0,1	;  Stop Bit Select
279 
U{NUM}LBEN	__z8bit	U{NUM}CTL0,0	;  Loop Back Enable
280 
U{NUM}CTL1	sfr	Base+3		; LIN UART Control 1
281 
U{NUM}MPMD1	__z8bit	U{NUM}CTL1,7	;  Multiprocessor Mode (MSEL=000)
282 
U{NUM}MPEN	__z8bit	U{NUM}CTL1,6	;  Multiprocessor Enable (MSEL=000)
283 
U{NUM}MPMD0	__z8bit	U{NUM}CTL1,5	;  Multiprocessor Mode (MSEL=000)
284 
U{NUM}MPBT	__z8bit	U{NUM}CTL1,4	;  Multiprocessor Bit Transmit (MSEL=000)
285 
U{NUM}DEPOL	__z8bit	U{NUM}CTL1,3	;  Driver Enable Polarity (MSEL=000)
286 
U{NUM}BRGCTL	__z8bit	U{NUM}CTL1,2	;  Baud Rate Generator Control (MSEL=000)
287 
U{NUM}RDAIRQ	__z8bit	U{NUM}CTL1,1	;  Receive Data Interrupt (MSEL=000)
288 
U{NUM}IREN	__z8bit	U{NUM}CTL1,0	;  Loop Back Enable (MSEL=000)
289 
U{NUM}NFEN	__z8bit	U{NUM}CTL1,7	;  Noise Filter Enable (MSEL=001)
290 
U{NUM}NFCTL	__z8bfield U{NUM}CTL1,4,3 ;  Noise Filter Control (MSEL=001)
291 
U{NUM}LMST	__z8bit	U{NUM}CTL1,7	;  LIN MASTER Mode (MSEL=010)
292 
U{NUM}LSLV	__z8bit	U{NUM}CTL1,6	;  LIN SLAVE Mode (MSEL=010)
293 
U{NUM}ABEN	__z8bit	U{NUM}CTL1,5	;  Autobaud Enable (MSEL=010)
294 
U{NUM}ABIEN	__z8bit	U{NUM}CTL1,4	;  Autobaud Interrupt Enable (MSEL=010)
295 
U{NUM}LinState	__z8bfield U{NUM}CTL1,2,2 ;  LIN State Machine (MSEL=010)
296 
U{NUM}TxBreakLength __z8bfield U{NUM}CTL1,0,2 ;  TxBreakLength (MSEL=010)
297 
U{NUM}MDSTAT	sfr	Base+4		; LIN UART Mode Select and Status
298 
U{NUM}MSEL	__z8bfield U{NUM}MDSTAT,5,3 ;  Mode Select
299 
U{NUM}MODESTATUS __z8bfield U{NUM}MDSTAT,0,5 ;  Mode Status
300 
U{NUM}ADDR	sfr	Base+5		; UART Address Compare
301 
U{NUM}BRH	sfr	Base+6		; UART Baud Rate High Byte
302 
U{NUM}BRL	sfr	Base+7		; UART Baud Rate Low Byte
303 
U{NUM}BR	sfr	U{NUM}BRH
304 
		endm
305 
 
306 
		__deflinuart "0",0f40h
307 
		__deflinuart "1",0f48h
308 
 
309 
;----------------------------------------------------------------------------
310 
; I2C
311 
 
312 
I2CDATA		sfr	0f50h		; I2C Data
313 
I2CSTAT		sfr	0f51h		; I2C Status
314 
I2C_TDRE	__z8bit	I2CSTAT,7	;  Transmit Data Register Empty
315 
RDRF		__z8bit	I2CSTAT,6	;  Receive Data Register Full
316 
SAM		__z8bit	I2CSTAT,5	;  Slave Address Match
317 
GCA		__z8bit	I2CSTAT,4	;  General Call Address
318 
RD		__z8bit	I2CSTAT,3	;  Read
319 
ARBLST		__z8bit	I2CSTAT,2	;  Arbitration Lost
320 
SPRS		__z8bit	I2CSTAT,1	;  Stop/Restart Condition Interrupt
321 
NCKI		__z8bit	I2CSTAT,0	;  NACK Interrupt
322 
I2CCTL		sfr	0f52h		; I2C Control
323 
IEN		__z8bit	I2CCTL,7	;  I2C Enable
324 
SSTART		__z8bit	I2CCTL,6	;  Send Start Condition
325 
SSTOP		__z8bit	I2CCTL,5	;  Send Stop Condition
326 
I2C_BIRQ	__z8bit	I2CCTL,4	;  Baud Rate Generator Interrupt Request
327 
TXI		__z8bit	I2CCTL,3	;  Enable TDRE interrupts
328 
NAK		__z8bit	I2CCTL,2	;  Send NAK
329 
FLUSH		__z8bit	I2CCTL,1	;  Flush Data
330 
FILTEN		__z8bit	I2CCTL,0	;  I2C Signal Filter Enable
331 
I2CBRH		sfr	0f53h		; I2C Baud Rate High Byte
332 
I2CBRL		sfr	0f54h		; I2C Baud Rate Low Byte
333 
I2CBR		sfr	I2CBRH
334 
I2CSTATE	sfr	0f55h		; I2C State
335 
I2CSTATE_H	__z8bfield I2CSTATE,4,4	;  I2C State (DIAG=1)
336 
I2CSTATE_L	__z8bfield I2CSTATE,0,4	;  Least Significant Nibble of the I2C State Machine (DIAG=1)
337 
ACKV		__z8bit	I2CSTATE,7	;  ACK Valid (DIAG=0)
338 
ACK		__z8bit	I2CSTATE,6	;  Acknowledge (DIAG=0)
339 
AS		__z8bit	I2CSTATE,5	;  Address State (DIAG=0)
340 
DS		__z8bit	I2CSTATE,4	;  Data State (DIAG=0)
341 
I10B		__z8bit	I2CSTATE,3	;  10B (DIAG=0)
342 
RSTR		__z8bit	I2CSTATE,2	;  RESTART (DIAG=0)
343 
SCLOUT		__z8bit	I2CSTATE,1	;  Serial Clock Output (DIAG=0)
344 
BUSY		__z8bit	I2CSTATE,0	;  I2C Bus Busy (DIAG=0)
345 
I2CMODE		sfr	0f56h		; I2C Mode
346 
MODE		__z8bfield I2CMODE,5,2	;  Selects the I2C Controller Operational Mode
347 
IRM		__z8bit	I2CMODE,4	;  Interactive Receive Mode
348 
GCE		__z8bit	I2CMODE,3	;  General Call Address Enable
349 
SLA		__z8bfield I2CMODE,1,2	;  Slave Address Bits 9 and 8
350 
DIAG		__z8bit	I2CMODE,0	;  Diagnostic Mode
351 
I2CSLVAD	sfr	0f57h		; I2C Slave Address Register
352 
 
353 
;----------------------------------------------------------------------------
354 
; ESPI
355 
 
356 
ESPIDATA	sfr	0f60h		; ESPI Data
357 
ESPITDCR	sfr	0f61h		; ESPI Transmit Data Command
358 
CRDR		__z8bit	ESPITDCR,7	;  Clear Receive Data Register
359 
RDFLAG		__z8bfield ESPITDCR,5,2	;  Receive Data Buffer Flag
360 
TEOF		__z8bit	ESPITDCR,1	;  Transmit End of Frame
361 
SSV		__z8bit	ESPITDCR,0	;  Slave Select Value
362 
ESPICTL		sfr	0f62h		; ESPI Control
363 
DIRQE		__z8bit	ESPICTL,7	;  Data Interrupt Request Enable
364 
ESPIEN1		__z8bit	ESPICTL,6	;  ESPI Enable and Direction Control
365 
BRGCTL		__z8bit	ESPICTL,5	;  Baud Rate Generator Control
366 
PHASE		__z8bit	ESPICTL,4	;  Phase Select
367 
CLKPOL		__z8bit	ESPICTL,3	;  Clock Polarity
368 
WOR		__z8bit	ESPICTL,2	;  Wire-OR (Open-Drain) Mode Enabled
369 
MMEN		__z8bit	ESPICTL,1	;  ESPI MASTER Mode Enable
370 
ESPIEN0		__z8bit	ESPICTL,0	;  ESPI Enable and Direction Control
371 
ESPIMODE	sfr	0f63h		; ESPI Mode
372 
SSMD		__z8bfield ESPIMODE,5,3	;  Slave Select Mode
373 
NUMBITS		__z8bfield ESPIMODE,2,3	;  Number of Data Bits Per Character to Transfer
374 
SSIO		__z8bit	ESPIMODE,1	;  Slave Select I/O
375 
SSPO		__z8bit	ESPIMODE,0	;  Slave Select Polarity
376 
ESPISTAT	sfr	0f64h		; ESPI Status
377 
TDRE		__z8bit	ESPISTAT,7	;  Transmit Data Register Empty
378 
TUND		__z8bit	ESPISTAT,6	;  Transmit Underrun
379 
COL		__z8bit	ESPISTAT,5	;  Collision
380 
ABT		__z8bit	ESPISTAT,4	;  SLAVE Mode Transaction Abort
381 
ROVR		__z8bit	ESPISTAT,3	;  Receive Overrun
382 
RDRNE		__z8bit	ESPISTAT,2	;  Receive Data Register Not Empty
383 
TFST		__z8bit	ESPISTAT,1	;  Transfer Status
384 
SLAS		__z8bit	ESPISTAT,0	;  Slave Select
385 
ESPISTATE	sfr	0f65h		; ESPI State
386 
SCKI		__z8bit	ESPISTATE,7	;  Serial Clock Input
387 
SDI		__z8bit	ESPISTATE,6	;  Serial Data Input
388 
ESPIBRH		sfr	0f66h		; ESPI Baud Rate High Byte
389 
ESPIBRL		sfr	0f67h		; ESPI Baud Rate Low Byte
390 
ESPIBR		sfr	ESPIBRH		;
391 
 
392 
;----------------------------------------------------------------------------
393 
; Analog Comparator
394 
 
395 
CMP0		sfr	0f90h		; Comparator 0 Control
396 
INPSEL0		__z8bit	CMP0,7		;  Signal Select for Positive Input
397 
INNSEL0		__z8bit	CMP0,6		;  Signal Select for Negative Input
398 
REFLVL0		__z8bfield CMP0,2,4	;  Internal Reference Voltage Level
399 
TIMTRG0		__z8bfield CMP0,0,2	;  Timer Trigger
400 
CMP1		sfr	0f91h		; Comparator 1 Control
401 
INPSEL1		__z8bit	CMP1,7		;  Signal Select for Positive Input
402 
INNSEL1		__z8bit	CMP1,6		;  Signal Select for Negative Input
403 
REFLVL1		__z8bfield CMP1,2,4	;  Internal Reference Voltage Level
404 
TIMTRG1		__z8bfield CMP1,0,2	;  Timer Trigger
405 
 
406 
;----------------------------------------------------------------------------
407 
; Analog/Digital Converter
408 
 
409 
ADCCTL0		sfr	0f70h		; ADC Control 0
410 
START		__z8bit	ADCCTL0,7	;  ADC Start/Busy
411 
INTREF_SEL	__z8bit	ADCCTL0,6	;  Internal Reference Select
412 
REFEN		__z8bit	ADCCTL0,5	;  Reference Select
413 
ADCEN		__z8bit	ADCCTL0,4	;  ADC Eneable
414 
ANAIN		__z8bfield ADCCTL0,0,4	;  Analog Input Select
415 
ADCRD_H		sfr	0f71h		; ADC Raw Data High Byte
416 
ADCD_H		sfr	0f72h		; ADC Data High Byte
417 
ADCD_L		sfr	0f73h		; ADC Data Low Bits
418 
OVF		__z8bit	ADCD_L,0	;  Overflow Status
419 
ADCD		sfr	ADCD_H
420 
ADCSST		sfr	0f74h		; ADC Sample Settling Time
421 
SST		__z8bfield ADCSST,0,4	;  Sample Settling Time
422 
ADCST		sfr	0f75h		; ADC Sample Time
423 
ST		__z8bfield ADCST,0,6	;  Sample Time
424 
ADCCP		sfr	0f76h		; ADC Clock Prescale Register
425 
DIV16		__z8bit	ADCCP,3		;  Divide by 16
426 
DIV8		__z8bit	ADCCP,2		;  Divide by 8
427 
DIV4		__z8bit	ADCCP,1		;  Divide by 4
428 
DIV2		__z8bit	ADCCP,0		;  Divide by 2
429 
 
430 
;----------------------------------------------------------------------------
431 
; Watchdog Timer
432 
 
433 
RSTSTAT		sfr	0ff0h		; Reset Status
434 
POR_VBO		__z8bit	RSTSTAT,7	;  Power-On Initiated VBO Reset or General VBO Reset Indicator
435 
STOP		__z8bit	RSTSTAT,6	;  Stop Mode Recovery Indicator
436 
WDT		__z8bit	RSTSTAT,5	;  Watchdog Timer Time-Out Indicator
437 
EXT		__z8bit	RSTSTAT,4	;  External Reset Indicator
438 
LVD		__z8bit	RSTSTAT,0	;  Low-Voltage Detection Indicator
439 
WDTH		sfr	0ff2h		; Watchdog Timer Reload High Byte
440 
WDTL		sfr	0ff3h		; Watchdog Timer Reload Low Byte
441 
 
442 
;----------------------------------------------------------------------------
443 
 
444 
		restore
445 
 
446 
		endif			; __regf1680inc