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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1126 | savelij | 1 | ifndef __regf082ainc |
| 2 | __regf082ainc equ 1 |
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| 3 | save |
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| 4 | listing off ; no listing over this file |
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| 5 | |||
| 6 | ;**************************************************************************** |
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| 7 | ;* * |
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| 8 | ;* AS 1.42 - File F082a.INC * |
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| 9 | ;* * |
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| 10 | ;* Contains Bit & Register Definitions for Z8encore F082a * |
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| 11 | ;* Source: Z8 Encore! XP F082A Series Product Specification, PS022829-0814* |
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| 12 | ;* * |
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| 13 | ;**************************************************************************** |
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| 14 | |||
| 15 | include "ez8com.inc" |
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| 16 | |||
| 17 | ;---------------------------------------------------------------------------- |
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| 18 | ; System Control |
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| 19 | |||
| 20 | PWRCTL0 sfr 0f80h ; Power Control 0 |
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| 21 | LPO __z8bit PWRCTL0,7 ; Low-Power Operational Amplifier Disable |
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| 22 | VBO __z8bit PWRCTL0,4 ; Voltage Brown-Out Detector Disable |
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| 23 | TEMP __z8bit PWRCTL0,3 ; Temperature Sensor Disable |
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| 24 | if __hasadc |
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| 25 | ADC __z8bit PWRCTL0,2 ; Analog-to-Digital Converter Disable |
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| 26 | endif |
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| 27 | COMP __z8bit PWRCTL0,1 ; Comparator Disable |
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| 28 | |||
| 29 | OSCCTL sfr 0f86h ; Oscillator Control |
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| 30 | INTEN __z8bit OSCCTL,7 ; Internal Precision Oscillator Enable |
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| 31 | XTLEN __z8bit OSCCTL,6 ; Crystal Oscillator Enable |
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| 32 | WDTEN __z8bit OSCCTL,5 ; Watchdog Timer Oscillator Enable |
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| 33 | SOFEN __z8bit OSCCTL,4 ; System Oscillator Failure Detection Enable |
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| 34 | WDFEN __z8bit OSCCTL,3 ; Watchdog Timer Oscillator Failure Detection Enable |
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| 35 | SCKSEL __z8bfield OSCCTL,0,3 ; System Clock Oscillator Select |
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| 36 | |||
| 37 | TRMADR sfr 0ff6h ; Trim Bit Address |
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| 38 | TRMDR sfr 0ff7h ; Trim Data |
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| 39 | |||
| 40 | ;---------------------------------------------------------------------------- |
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| 41 | ; Flash Options |
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| 42 | |||
| 43 | OPTIONS0 label 0000h |
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| 44 | WDT_RES __z8cbit OPTIONS0,7 ; Watchdog Timer Reset |
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| 45 | WDT_AO __z8cbit OPTIONS0,6 ; Watchdog Timer Always On |
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| 46 | OSC_SEL __z8cbfield OPTIONS0,4,2 ; Oscillator Mode Selection |
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| 47 | VBO_AO __z8cbit OPTIONS0,3 ; Voltage Brown-Out Protection Always On |
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| 48 | |||
| 49 | FRP __z8cbit OPTIONS0,2 ; Flash Read Protect |
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| 50 | FWP __z8cbit OPTIONS0,0 ; Flash Write Protect |
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| 51 | OPTIONS1 label 0001h |
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| 52 | XTLDIS __z8cbit OPTIONS1,4 ; State of the Crystal Oscillator at Reset |
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| 53 | |||
| 54 | ;---------------------------------------------------------------------------- |
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| 55 | ; Interrupts Vectors |
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| 56 | |||
| 57 | RESET_vect label 0002h ; Reset (not an interrupt) |
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| 58 | WDT_vect label 0004h ; Watchdog Timer |
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| 59 | ILL_INST_vect label 0006h ; Illegal Instruction Trap (not an interrupt) |
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| 60 | TIMER1_vect label 000ah ; Timer 1 |
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| 61 | TIMER0_vect label 000ch ; Timer 0 |
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| 62 | UART_RX_vect label 000eh ; UART Receiver |
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| 63 | UART_TX_vect label 0010h ; UART Transmitter |
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| 64 | if __hasadc |
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| 65 | ADC_vect label 0016h ; ADC |
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| 66 | endif |
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| 67 | A7_vect label 0018h ; Port A7, selectable rising or falling input edge or LVD |
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| 68 | A6_vect label 001ah ; Port A6, selectable rising or falling input edge or Comparator Output |
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| 69 | A5_vect label 001ch ; Port A5, selectable rising or falling input edge |
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| 70 | A4_vect label 001eh ; Port A4, selectable rising or falling input edge |
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| 71 | A3_vect label 0020h ; Port A3, selectable rising or falling input edge |
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| 72 | A2_vect label 0022h ; Port A2, selectable rising or falling input edge |
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| 73 | A1_vect label 0024h ; Port A1, selectable rising or falling input edge |
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| 74 | A0_vect label 0026h ; Port A0, selectable rising or falling input edge |
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| 75 | C3_vect label 0030h ; Port C3, both input edges |
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| 76 | C2_vect label 0032h ; Port C2, both input edges |
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| 77 | C1_vect label 0034h ; Port C1, both input edges |
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| 78 | C0_vect label 0036h ; Port C0, both input edges |
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| 79 | PRIOSC_vect label 003ah ; Primary Oscillator Fail Trap (not an interrupt) |
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| 80 | WDGOSC_vect label 003ch ; Watchdog Oscillator Fail Trap (not an interrupt) |
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| 81 | |||
| 82 | ;---------------------------------------------------------------------------- |
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| 83 | ; Interrupts |
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| 84 | |||
| 85 | __defirq macro NUM,Base |
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| 86 | IRQ{NUM} sfr Base+0 ; Interrupt Request n |
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| 87 | IRQ{NUM}ENH sfr Base+1 ; IRQn Enable High Bit |
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| 88 | IRQ{NUM}ENL sfr Base+2 ; IRQn Enable Low Bit |
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| 89 | endm |
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| 90 | |||
| 91 | __defirq "0",0fc0h |
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| 92 | __defirq "1",0fc3h |
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| 93 | __defirq "2",0fc6h |
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| 94 | |||
| 95 | T1I __z8bit IRQ0,6 ; Timer 1 Interrupt Request |
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| 96 | T0I __z8bit IRQ0,5 ; Timer 0 Interrupt Request |
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| 97 | U0RXI __z8bit IRQ0,4 ; UART 0 Receiver Interrupt Request |
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| 98 | U0TXI __z8bit IRQ0,3 ; UART 0 Transmitter Interrupt Request |
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| 99 | if __hasadc |
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| 100 | ADCI __z8bit IRQ0,0 ; ADC Interrupt Request |
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| 101 | endif |
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| 102 | |||
| 103 | T1ENH __z8bit IRQ0ENH,6 ; Timer 1 Interrupt Enable & Priority |
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| 104 | T1ENL __z8bit IRQ0ENL,6 |
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| 105 | T0ENH __z8bit IRQ0ENH,5 ; Timer 0 Interrupt Enable & Priority |
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| 106 | T0ENL __z8bit IRQ0ENL,5 |
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| 107 | U0RENH __z8bit IRQ0ENH,4 ; UART 0 Receive Interrupt Enable & Priority |
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| 108 | U0RENL __z8bit IRQ0ENL,4 |
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| 109 | U0TENH __z8bit IRQ0ENH,3 ; UART 0 Transmit Interrupt Enable & Priority |
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| 110 | U0TENL __z8bit IRQ0ENL,3 |
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| 111 | if __hasadc |
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| 112 | ADCENH __z8bit IRQ0ENH,0 ; ADC Interrupt Enable & Priority |
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| 113 | ADCENL __z8bit IRQ0ENL,0 |
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| 114 | endif |
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| 115 | |||
| 116 | PA7VI __z8bit IRQ1,7 ; Port A7 Interrupt Request |
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| 117 | PA6CI __z8bit IRQ1,6 ; Port A6 or Comparator Interrupt Request |
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| 118 | PA5I __z8bit IRQ1,5 ; Port A5 Interrupt Request |
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| 119 | PA4I __z8bit IRQ1,4 ; Port A4 Interrupt Request |
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| 120 | PA3I __z8bit IRQ1,3 ; Port A3 Interrupt Request |
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| 121 | PA2I __z8bit IRQ1,2 ; Port A2 Interrupt Request |
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| 122 | PA1I __z8bit IRQ1,1 ; Port A1 Interrupt Request |
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| 123 | PA0I __z8bit IRQ1,0 ; Port A0 Interrupt Request |
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| 124 | |||
| 125 | PA7VENH __z8bit IRQ1ENH,7 ; Port A7 Interrupt Enable & Priority |
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| 126 | PA7VENL __z8bit IRQ1ENL,7 |
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| 127 | PA6CENH __z8bit IRQ1ENH,6 ; Port A6 Interrupt Enable & Priority |
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| 128 | PA6CENL __z8bit IRQ1ENL,6 |
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| 129 | PA5ENH __z8bit IRQ1ENH,5 ; Port A5 Interrupt Enable & Priority |
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| 130 | PA5ENL __z8bit IRQ1ENL,5 |
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| 131 | PA4ENH __z8bit IRQ1ENH,4 ; Port A4 Interrupt Enable & Priority |
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| 132 | PA4ENL __z8bit IRQ1ENL,4 |
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| 133 | PA3ENH __z8bit IRQ1ENH,3 ; Port A3 Interrupt Enable & Priority |
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| 134 | PA3ENL __z8bit IRQ1ENL,3 |
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| 135 | PA2ENH __z8bit IRQ1ENH,2 ; Port A2 Interrupt Enable & Priority |
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| 136 | PA2ENL __z8bit IRQ1ENL,2 |
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| 137 | PA1ENH __z8bit IRQ1ENH,1 ; Port A1 Interrupt Enable & Priority |
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| 138 | PA1ENL __z8bit IRQ1ENL,1 |
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| 139 | PA0ENH __z8bit IRQ1ENH,0 ; Port A0 Interrupt Enable & Priority |
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| 140 | PA0ENL __z8bit IRQ1ENL,0 |
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| 141 | |||
| 142 | PC3I __z8bit IRQ2,3 ; Port C3 Interrupt Request |
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| 143 | PC2I __z8bit IRQ2,2 ; Port C2 Interrupt Request |
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| 144 | PC1I __z8bit IRQ2,1 ; Port C1 Interrupt Request |
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| 145 | PC0I __z8bit IRQ2,0 ; Port C0 Interrupt Request |
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| 146 | |||
| 147 | C3ENH __z8bit IRQ2ENH,3 ; Port C3 Interrupt Enable & Priority |
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| 148 | C3ENL __z8bit IRQ2ENL,3 |
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| 149 | C2ENH __z8bit IRQ2ENH,2 ; Port C2 Interrupt Enable & Priority |
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| 150 | C2ENL __z8bit IRQ2ENL,2 |
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| 151 | C1ENH __z8bit IRQ2ENH,1 ; Port C1 Interrupt Enable & Priority |
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| 152 | C1ENL __z8bit IRQ2ENL,1 |
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| 153 | C0ENH __z8bit IRQ2ENH,0 ; Port C0 Interrupt Enable & Priority |
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| 154 | C0ENL __z8bit IRQ2ENL,0 |
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| 155 | |||
| 156 | IRQES sfr 0fcdh ; Interrupt Edge Select |
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| 157 | IRQSS sfr 0fceh ; Shared Interrupt Select |
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| 158 | PA7VS __z8bit IRQSS,7 ; PA7/LVD Selection |
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| 159 | PA6CS __z8bit IRQSS,6 ; PA6/Comparator Selection |
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| 160 | IRQCTL sfr 0fcfh ; Interrupt Control |
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| 161 | IRQE __z8bit IRQCTL,7 ; Interrupt Request Enable |
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| 162 | |||
| 163 | ;---------------------------------------------------------------------------- |
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| 164 | ; Flash Memory Control |
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| 165 | |||
| 166 | FCTL sfr 0ff8h ; Flash Control |
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| 167 | FCMD __z8bfield FCTL,0,8 ; Flash Command |
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| 168 | FSTAT sfr 0ff8h ; Flash Status |
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| 169 | FPS sfr 0ff9h ; Flash Page Select |
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| 170 | INFO_EN __z8bit FPS,7 ; Information Area Enable |
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| 171 | PAGE __z8bfield FPS,0,7 ; Page Select |
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| 172 | FPROT sfr 0ff9h ; Flash Sector Protect |
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| 173 | FFREQH sfr 0ffah ; Flash Programming Frequency High Byte |
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| 174 | FFREQL sfr 0ffbh ; Flash Programming Frequency Low Byte |
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| 175 | FFREQ sfr FFREQH |
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| 176 | |||
| 177 | ;---------------------------------------------------------------------------- |
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| 178 | ; GPIO |
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| 179 | |||
| 180 | __defgpio "A",0fd0h |
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| 181 | __defgpio "B",0fd4h |
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| 182 | __defgpio "C",0fd8h |
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| 183 | __defgpio "D",0fdch ; TODO: PDIN does not exist |
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| 184 | |||
| 185 | ;---------------------------------------------------------------------------- |
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| 186 | ; LED Controller |
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| 187 | |||
| 188 | LEDEN sfr 0f82h ; LED Drive Enable |
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| 189 | LEDLVLH sfr 0f83h ; LED Drive Level High |
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| 190 | LEDLVLL sfr 0f84h ; LED Drive Level Low |
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| 191 | |||
| 192 | ;---------------------------------------------------------------------------- |
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| 193 | ; Timer |
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| 194 | |||
| 195 | __deftimer "0",0f00h,1,0 |
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| 196 | __deftimer "1",0f08h,1,0 |
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| 197 | |||
| 198 | ;---------------------------------------------------------------------------- |
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| 199 | ; UART |
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| 200 | |||
| 201 | __defuart "0",0f40h |
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| 202 | |||
| 203 | ;---------------------------------------------------------------------------- |
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| 204 | ; Analog Comparator |
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| 205 | |||
| 206 | CMP0 sfr 0f90h ; Comparator 0 Control |
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| 207 | INPSEL __z8bit CMP0,7 ; Signal Select for Positive Input |
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| 208 | INNSEL __z8bit CMP0,6 ; Signal Select for Negative Input |
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| 209 | REFLVL __z8bfield CMP0,0,6 ; Internal Reference Voltage Level (b0/1 only on 8 pin devices) |
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| 210 | |||
| 211 | ;---------------------------------------------------------------------------- |
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| 212 | ; Analog/Digital Converter |
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| 213 | |||
| 214 | if __hasadc |
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| 215 | ADCCTL0 sfr 0f70h ; ADC Control 0 |
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| 216 | CEN __z8bit ADCCTL0,7 ; Conversion Enable |
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| 217 | REFSELL __z8bit ADCCTL0,6 ; Voltage Reference Level Select Low Bit |
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| 218 | REFOUT __z8bit ADCCTL0,5 ; Internal Reference Output Enable |
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| 219 | CONT __z8bit ADCCTL0,4 ; Continuous Conversion |
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| 220 | ANAIN __z8bfield ADCCTL0,0,3 ; Analog Input Select |
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| 221 | ADCCTL1 sfr 0f71h ; ADC Control 1 |
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| 222 | REFSELH __z8bit ADCCTL1,7 ; Voltage Reference Level Select High Bit |
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| 223 | BUFMODE __z8bfield ADCCTL1,0,2 ; Input Buffer Mode Select |
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| 224 | ADCD_H sfr 0f72h ; ADC Data High Byte |
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| 225 | ADCD_L sfr 0f73h ; ADC Data Low Bits |
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| 226 | OVF __z8bit ADCD_L,0 ; Overflow Status |
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| 227 | ADCD sfr ADCD_H |
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| 228 | ADCSST sfr 0f74h ; ADC Sample Settling Time |
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| 229 | SST __z8bfield ADCSST,0,3 ; Sample Settling Time |
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| 230 | ADCST sfr 0f75h ; ADC sample time |
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| 231 | ST __z8bfield ADCST,0,6 ; Sample Time |
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| 232 | endif ; __hasadc |
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| 233 | |||
| 234 | ;---------------------------------------------------------------------------- |
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| 235 | ; Watchdog Timer |
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| 236 | |||
| 237 | RSTSTAT sfr 0ff0h ; Reset Status |
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| 238 | POR __z8bit RSTSTAT,7 ; Power-On Reset Indicator |
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| 239 | STOP __z8bit RSTSTAT,6 ; Stop Mode Recovery Indicator |
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| 240 | WDT __z8bit RSTSTAT,5 ; Watchdog Timer Time-Out Indicator |
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| 241 | EXT __z8bit RSTSTAT,4 ; External Reset Indicator |
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| 242 | LVCD __z8bit RSTSTAT,,0 ; Low Voltage Detection Indicator |
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| 243 | WDTCTL sfr 0ff0h ; Watchdog Timer Control |
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| 244 | WDTU sfr 0ff1h ; Watchdog Timer Reload Upper Byte |
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| 245 | WDTH sfr 0ff2h ; Watchdog Timer Reload High Byte |
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| 246 | WDTL sfr 0ff3h ; Watchdog Timer Reload Low Byte |
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| 247 | |||
| 248 | ;---------------------------------------------------------------------------- |
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| 249 | |||
| 250 | restore |
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| 251 | |||
| 252 | endif ; __regf082ainc |