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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1186 | savelij | 1 | ifndef __stm8lrtcinc ; avoid multiple inclusion |
| 2 | __stm8lrtcinc equ 1 |
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| 3 | |||
| 4 | save |
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| 5 | listing off ; no listing over this file |
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| 6 | |||
| 7 | ;**************************************************************************** |
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| 8 | ;* * |
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| 9 | ;* AS 1.42 - File RTC.INC * |
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| 10 | ;* * |
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| 11 | ;* contains SFR and Bit Definitions for STM8L RTC * |
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| 12 | ;* * |
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| 13 | ;**************************************************************************** |
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| 14 | |||
| 15 | __defrtc macro Base |
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| 16 | RTC_TR1 label Base+$00 ; RTC Time register 1 |
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| 17 | RTC_ST bfield RTC_TR1,4,3 ; Second tens in BCD format |
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| 18 | RTC_SU bfield RTC_TR1,0,4 ; Second units in BCD format |
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| 19 | RTC_TR2 label Base+$01 ; RTC Time register 2 |
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| 20 | RTC_MNT bfield RTC_TR2,4,3 ; Minute tens in BCD format |
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| 21 | RTC_MNU bfield RTC_TR2,0,4 ; Minute units in BCD format |
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| 22 | RTC_TR3 label Base+$02 ; RTC Time register 3 |
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| 23 | RTC_PM bit RTC_TR3,7 ; AM/PM notation |
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| 24 | RTC_HT bfield RTC_TR3,4,2 ; Hour tens in BCD format |
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| 25 | RTC_HU bfield RTC_TR3,0,4 ; Hour units in BCD format |
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| 26 | RTC_DR1 label Base+$04 ; RTC Date register 1 |
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| 27 | RTC_DT bfield RTC_DR1,4,2 ; Date tens in BCD format |
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| 28 | RTC_DU bfield RTC_DR1,0,4 ; Date units in BCD format |
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| 29 | RTC_DR2 label Base+$05 ; RTC Date register 2 |
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| 30 | RTC_WDU bfield RTC_DR2,5,3 ; Week day units |
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| 31 | RTC_MT bit RTC_DR2,4 ; Month tens in BCD format |
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| 32 | RTC_MU bfield RTC_DR2,0,4 ; Month units in BCD format |
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| 33 | RTC_DR3 label Base+$06 ; RTC Date register 3 |
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| 34 | RTC_YT bfield RTC_DR3,4,4 ; Year tens in BCD format |
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| 35 | RTC_YU bfield RTC_DR3,0,4 ; Year units in BCD format |
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| 36 | RTC_CR1 label Base+$08 ; RTC Control register 1 |
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| 37 | RTC_FMT bit RTC_CR1,6 ; Hour format |
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| 38 | RTC_RATIO bit RTC_CR1,5 ; System clock (SYSCLK) versus RTCCLK ratio |
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| 39 | RTC_BYPSHAD bit RTC_CR1,4 ; Bypass the shadow registers |
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| 40 | RTC_WUCKSEL bfield RTC_CR1,0,3 ; Wakeup clock selection |
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| 41 | RTC_CR2 label Base+$09 ; RTC Control register 2 |
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| 42 | RTC_WUTIE bit RTC_CR2,6 ; Wakeup timer interrupt enable |
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| 43 | RTC_ALRAIE bit RTC_CR2,4 ; Alarm A interrupt enable |
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| 44 | RTC_WUTE bit RTC_CR2,2 ; Wakeup timer enable |
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| 45 | RTC_ALRAE bit RTC_CR2,0 ; Alarm A enable |
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| 46 | RTC_CR3 label Base+$0a ; RTC Control register 3 |
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| 47 | RTC_COE bit RTC_CR3,7 ; Calibration output enable |
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| 48 | RTC_OSEL bfield RTC_CR3,5 ; Output selection |
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| 49 | RTC_POL bit RTC_CR3,4 ; Output polarity |
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| 50 | RTC_COSEL bit RTC_CR3,3 ; Calibration output selection |
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| 51 | RTC_BCK bit RTC_CR3,2 ; Backup |
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| 52 | RTC_SUB1H bit RTC_CR3,1 ; Subtract 1 hour (winter time change) |
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| 53 | RTC_ADD1H bit RTC_CR3,0 ; Add 1 hour (summer time change) |
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| 54 | RTC_ISR1 label Base+$0c ; RTC Initialization and status register 1 |
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| 55 | RTC_INIT bit RTC_ISR1,7 ; Initialization mode |
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| 56 | RTC_INITF bit RTC_ISR1,6 ; Initialization flag |
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| 57 | RTC_RSF bit RTC_ISR1,5 ; Registers synchronization flag |
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| 58 | RTC_INITS bit RTC_ISR1,4 ; Initialization status flag |
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| 59 | RTC_SHPF bit RTC_ISR1,3 ; Shift operation pending |
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| 60 | RTC_WUTWF bit RTC_ISR1,2 ; Wakeup timer write flag |
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| 61 | RTC_RECALPF bit RTC_ISR1,1 ; Recalibration pending Flag |
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| 62 | RTC_ALRAWF bit RTC_ISR1,0 ; Alarm A write flag |
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| 63 | RTC_ISR2 label Base+$0d ; RTC Initialization and Status register 2 |
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| 64 | RTC_TAMP3F bit RTC_ISR2,7 ; TAMPER3 detection flag |
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| 65 | RTC_TAMP2F bit RTC_ISR2,6 ; TAMPER2 detection flag |
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| 66 | RTC_TAMP1F bit RTC_ISR2,5 ; TAMPER1 detection flag |
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| 67 | RTC_WUTF bit RTC_ISR2,2 ; Periodic wakeup flag |
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| 68 | RTC_ALRAF bit RTC_ISR2,0 ; Alarm A Flag |
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| 69 | RTC_SPRERH label Base+$10 ; RTC Synchronous prescaler register high |
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| 70 | RTC_SPRERL label Base+$11 ; RTC Synchronous prescaler register low |
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| 71 | RTC_APRER label Base+$12 ; RTC Asynchronous prescaler register |
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| 72 | RTC_WUTRH label Base+$14 ; RTC Wakeup timer register high |
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| 73 | RTC_WUTRL label Base+$15 ; RTC Wakeup timer register low |
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| 74 | RTC_SSRL label Base+$17 ; RTC Subsecond register low |
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| 75 | RTC_SSRH label Base+$18 ; RTC Subsecond register high |
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| 76 | RTC_WPR label Base+$19 ; RTC Write protection register |
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| 77 | RTC_SHIFTRH label Base+$1a ; RTC Shift register high |
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| 78 | RTC_ADD1S bit RTC_SHIFTRH,7 ; Add one second |
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| 79 | RTC_SHIFTRL label Base+$1b ; RTC Shift register low |
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| 80 | RTC_ALRMAR1 label Base+$1c ; RTC Alarm A register 1 |
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| 81 | RTC_MSK1 bit RTC_ALRMAR1,7 ; Alarm A Seconds mask |
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| 82 | RTC_AL_ST bfield RTC_ALRMAR1,4,3 ; Second tens in BCD format |
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| 83 | RTC_AL_SU bfield RTC_ALRMAR1,0,4 ; Second units in BCD format |
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| 84 | RTC_ALRMAR2 label Base+$1d ; RTC Alarm A register 2 |
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| 85 | RTC_MSK2 bit RTC_ALRMAR2,7 ; Alarm A minutes mask |
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| 86 | RTC_AL_MNT bfield RTC_ALRMAR2,4,3 ; Minute tens in BCD format |
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| 87 | RTC_AL_MNU bfield RTC_ALRMAR2,0,4 ; Minute units in BCD format |
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| 88 | RTC_ALRMAR3 label Base+$1e ; RTC Alarm A register 3 |
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| 89 | RTC_MSK3 bit RTC_ALRMAR3,7 ; Alarm A hours mask |
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| 90 | RTC_AL_PM bit RTC_ALRMAR3,6 ; AM/PM notation |
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| 91 | RTC_AL_HT bfield RTC_ALRMAR3,4,2 ; Hour tens in BCD format |
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| 92 | RTC_AL_HU bfield RTC_ALRMAR3,0,4 ; Hour units in BCD format |
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| 93 | RTC_ALRMAR4 label Base+$1f ; RTC Alarm A register 4 |
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| 94 | RTC_MSK4 bit RTC_ALRMAR4,7 ; Alarm A Date mask |
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| 95 | RTC_WDSEL bit RTC_ALRMAR4,6 ; Week day selection |
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| 96 | RTC_AL1_DT bfield RTC_ALRMAR4,4,2 ; Date tens in BCD format |
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| 97 | RTC_AL1_DU bfield RTC_ALRMAR4,0,4 ; Date units or Day in BCD format |
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| 98 | RTC_ALRMASSRH label Base+$24 ; RTC Alarm A subsecond register high |
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| 99 | RTC_ALRMASSRL label Base+$25 ; RTC Alarm A subsecond register low |
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| 100 | RTC_ALRMASSMSKR label Base+$26 ; RTC Alarm A masking register |
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| 101 | RTC_CALRH label Base+$2a ; RTC Calibration register high |
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| 102 | RTC_CALP bit RTC_CALRH,7 ; Increase of RTC frequency by 488.5 ppm |
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| 103 | RTC_CALW8 bit RTC_CALRH,6 ; Use an 8-second calibration cycle period |
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| 104 | RTC_CALW16 bit RTC_CALRH,5 ; Use a16-second calibration cycle period |
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| 105 | RTC_CALRL label Base+$2b ; RTC Calibration register low |
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| 106 | RTC_TCR1 label Base+$2c ; RTC Tamper control register 1 |
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| 107 | RTC_TAMP3TRG bit RTC_TCR1,6 ; Active level for tamper input 3 |
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| 108 | RTC_TAMP3E bit RTC_TCR1,5 ; Tamper detection enable for tamper input 3 |
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| 109 | RTC_TAMP2TRG bit RTC_TCR1,4 ; Active level for tamper input 2 |
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| 110 | RTC_TAMP2E bit RTC_TCR1,3 ; Tamper detection enable for tamper input 2 |
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| 111 | RTC_TAMP1TRG bit RTC_TCR1,2 ; Active level for tamper 1 |
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| 112 | RTC_TAMP1E bit RTC_TCR1,1 ; Tamper detection enable for tamper input 1 |
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| 113 | RTC_TAMPIE bit RTC_TCR1,0 ; Tamper interrupt enable |
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| 114 | RTC_TCR2 label Base+$2d ; RTC Tamper control register 2 |
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| 115 | RTC_TTAMPPUDIS bit RTC_TCR2,7 ; TAMPER pull-up disable |
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| 116 | RTC_TTAMPPRCH bfield RTC_TCR2,5,2 ; Tamper precharge duration |
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| 117 | RTC_TTAMPFLT bfield RTC_TCR2,3,2 ; Tamper filter count |
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| 118 | RTC_TTAMPFREQ bfield RTC_TCR2,0,2 ; Tamper sampling frequency |
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| 119 | CSSLSE_CSR label Base+$50 ; CSS on LSE control and status register |
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| 120 | SWITCHF bit CSSLSE_CSR,4 ; RTC clock switch flag |
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| 121 | CSSF bit CSSLSE_CSR,3 ; CSS on LSE flag |
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| 122 | CSSIE bit CSSLSE_CSR,2 ; Clock security system on LSE interrupt enable |
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| 123 | SWITCHEN bit CSSLSE_CSR,1 ; RTC clock switch to LSI in case of LSE failure enable |
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| 124 | LSE_CSSEN bit CSSLSE_CSR,0 ; Clock security system on LSE enable |
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| 125 | endm |
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| 126 | |||
| 127 | restore |
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| 128 | endif ; __stm8lrtcinc |