Details | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
1126 | savelij | 1 | ifndef stddef37inc ; avoid multiple inclusion |
2 | stddef37inc equ 1 |
||
3 | |||
4 | save |
||
5 | listing off ; no listing over this file |
||
6 | |||
7 | ;**************************************************************************** |
||
8 | ;* * |
||
9 | ;* AS 1.42 - File STDDEF37.INC * |
||
10 | ;* * |
||
11 | ;* Contains SFR and Bit Definitions for TMS370 Processors * |
||
12 | ;* * |
||
13 | ;**************************************************************************** |
||
14 | |||
15 | if (MOMCPU<>57720848)&&(MOMCPU<>57720864)&&(MOMCPU<>57720880)&&(MOMCPU<>57720896)&&(MOMCPU<>57720912) |
||
16 | fatal "wrong target selected: only 370C010, 370C020, 370C030, 370C040 oder 370C050 supported" |
||
17 | endif |
||
18 | |||
19 | |||
20 | if MOMPASS=1 |
||
21 | message "TMS370 Register Definitions (C) 1994 Alfred Arnold" |
||
22 | message "including \{MOMCPU} Registers" |
||
23 | endif |
||
24 | |||
25 | ;---------------------------------------------------------------------------- |
||
26 | ; System Control |
||
27 | |||
28 | sccr0 equ p010 |
||
29 | cold_start dbit 7,sccr0 ; Cold Start |
||
30 | osc_power dbit 6,sccr0 ; Reduce Oscillator Power Consumption |
||
31 | pf_auto_wait dbit 5,sccr0 ; External Peripherals Wait States |
||
32 | osc_flt_flag dbit 4,sccr0 ; Oscillator Fault |
||
33 | mc_pin_wpo dbit 3,sccr0 ; Voltage on MC high enough |
||
34 | mc_pin_data dbit 2,sccr0 ; MC Pin State |
||
35 | up_uc_mode dbit 0,sccr0 ; Micro Processor or Micro Controller Mode |
||
36 | |||
37 | sccr1 equ p011 |
||
38 | auto_wait_disable dbit 4,sccr1 ; External Memory Wait States |
||
39 | memory_disable dbit 2,sccr1 ; Disable Internal ROM |
||
40 | |||
41 | sccr2 equ p012 |
||
42 | halt_standby dbit 7,sccr2 ; Halt or /Standby Mode |
||
43 | pwrdwn_idle dbit 6,sccr2 ; /Idle or Halt/Standby Mode |
||
44 | bus_stest dbit 4,sccr2 ; Bus Self Test |
||
45 | cpu_stest dbit 3,sccr2 ; Processor Self Test |
||
46 | int1_nmi dbit 1,sccr2 ; Interrupt 1 Maskable or not |
||
47 | privilege_disable dbit 0,sccr2 ; Leave Privileged Mode |
||
48 | |||
49 | ;---------------------------------------------------------------------------- |
||
50 | ; Digital IO |
||
51 | |||
52 | aport1 equ p020 |
||
53 | aport2 equ p021 |
||
54 | adata equ p022 ; Port A Data Register |
||
55 | adir equ p023 ; Port A Data Direction Register |
||
56 | |||
57 | if (MOMCPU=370C020h)||(MOMCPU>370C030h) |
||
58 | bport1 equ p024 |
||
59 | bport2 equ p025 |
||
60 | bdata equ p026 ; Port B Data Register |
||
61 | bdir equ p027 ; Port B Data Direction Register |
||
62 | endif |
||
63 | |||
64 | if (MOMCPU=370C020h)||(MOMCPU=370C050h) |
||
65 | cport1 equ p028 |
||
66 | cport2 equ p029 |
||
67 | cdata equ p02a ; Port C Data Register |
||
68 | cdir equ p02b ; Port C Data Direction Register |
||
69 | endif |
||
70 | |||
71 | dport1 equ p02c |
||
72 | dport2 equ p02d |
||
73 | ddata equ p02e ; Port D Data Register |
||
74 | ddir equ p02f ; Port D Data Direction Register |
||
75 | |||
76 | ;---------------------------------------------------------------------------- |
||
77 | ; Interrupts |
||
78 | |||
79 | int1 equ p017 |
||
80 | int1_enable dbit 0,int1 ; External Interrupt 1 Enable |
||
81 | int1_priority dbit 1,int1 ; External Interrupt 1 Priority |
||
82 | int1_polarity dbit 2,int1 ; External Interrupt 1 Polarity |
||
83 | int1_pin_data dbit 6,int1 ; External Interrupt 1 Pin State |
||
84 | int1_flag dbit 7,int1 ; External Interrupt 1 Flag |
||
85 | |||
86 | int2 equ p018 |
||
87 | int2_enable dbit 0,int2 ; External Interrupt 2 Enable |
||
88 | int2_priority dbit 1,int2 ; External Interrupt 2 Priority |
||
89 | int2_polarity dbit 2,int2 ; External Interrupt 2 Polarity |
||
90 | int2_data_out dbit 3,int2 ; External Interrupt 2 Pin Output Value |
||
91 | int2_data_dir dbit 4,int2 ; External Interrupt 2 Pin Data Direction |
||
92 | int2_pin_data dbit 6,int2 ; External Interrupt 2 Pin State |
||
93 | int2_flag dbit 7,int2 ; External Interrupt 2 Flag |
||
94 | |||
95 | int3 equ p019 |
||
96 | int3_enable dbit 0,int3 ; External Interrupt 3 Enable |
||
97 | int3_priority dbit 1,int3 ; External Interrupt 3 Priority |
||
98 | int3_polarity dbit 2,int3 ; External Interrupt 3 Polarity |
||
99 | int3_data_out dbit 3,int3 ; External Interrupt 3 Pin Output Value |
||
100 | int3_data_dir dbit 4,int3 ; External Interrupt 3 Pin Data Direction |
||
101 | int3_pin_data dbit 6,int3 ; External Interrupt 3 Pin State |
||
102 | int3_flag dbit 7,int3 ; External Interrupt 3 Flag |
||
103 | |||
104 | ;---------------------------------------------------------------------------- |
||
105 | ; (E)EPROM |
||
106 | |||
107 | deectl equ p01a |
||
108 | ee_busy dbit 7,deectl ; EEPROM Busy |
||
109 | ap dbit 2,deectl ; Enable Block Programming |
||
110 | w1w0 dbit 1,deectl ; Program Ones or Zeros? |
||
111 | ee_exe dbit 0,deectl ; Execute Transaction |
||
112 | |||
113 | epctl0 equ p01c |
||
114 | ep0_busy dbit 7,epctl0 ; EPROM Part 1 Busy |
||
115 | ep0_vpps dbit 6,epctl0 ; Enable Programming Voltage |
||
116 | ep0_w0 dbit 1,epctl0 ; Enable Writing Zeros |
||
117 | ep0_exe dbit 0,epctl0 ; Execute Write Transaction |
||
118 | |||
119 | epctl1 equ p01e |
||
120 | ep1_busy dbit 7,epctl1 ; EPROM Part 2 Busy |
||
121 | ep1_vpps dbit 6,epctl1 ; Enable Programming Voltage |
||
122 | ep1_w0 dbit 1,epctl1 ; Enable Writing Zeros |
||
123 | ep1_exe dbit 0,epctl1 ; Execute Write Transaction |
||
124 | |||
125 | ;---------------------------------------------------------------------------- |
||
126 | ; Timer 1 |
||
127 | |||
128 | t1ctl1 equ p049 ; Controls also the Watchdog |
||
129 | t1ctl2 equ p04a |
||
130 | |||
131 | if MOMCPU<>370C030h |
||
132 | t1cntrh equ p040 ; Count Register |
||
133 | t1cntrl equ p041 |
||
134 | |||
135 | t1ch equ p042 ; Compare Register |
||
136 | t1cl equ p043 |
||
137 | |||
138 | t1cch equ p044 ; Compare/Capture Register |
||
139 | t1ccl equ p045 |
||
140 | |||
141 | t1_input_select0 dbit 0,t1ctl1 ; Clock Source |
||
142 | t1_input_select1 dbit 1,t1ctl1 |
||
143 | t1_input_select2 dbit 2,t1ctl1 |
||
144 | |||
145 | t1_sw_reset dbit 0,t1ctl2 ; Reset Counter |
||
146 | t1_ovrfl_int_flag dbit 3,t1ctl2 ; Overflow Flag |
||
147 | t1_ovrfl_int_ena dbit 4,t1ctl2 ; Enable Overflow Interrupt |
||
148 | |||
149 | t1ctl3 equ p04b |
||
150 | t1c1_int_ena dbit 0,t1ctl3 ; Compare Register Interrupt Enable |
||
151 | t1c2_int_ena dbit 1,t1ctl3 ; Capture/Compare Register Interrupt Enable |
||
152 | t1edge_int_ena dbit 2,t1ctl3 ; Edge on T1IC/CR Interrupt Enable |
||
153 | t1c1_int_flag dbit 5,t1ctl3 ; Compare Register Interrupt Flag |
||
154 | t1c2_int_flag dbit 6,t1ctl3 ; Capture/Compare Register Interrupt Flag |
||
155 | t1edge_int_flag dbit 7,t1ctl3 ; Edge on T1IC/CR Interrupt Flag |
||
156 | |||
157 | t1ctl4 equ p04c |
||
158 | t1edge_det_ena dbit 0,t1ctl4 ; T1IC/CR Edge Detector Enable |
||
159 | t1cr_rst_ena dbit 1,t1ctl4 ; External Reset Enable |
||
160 | t1edge_polarity dbit 2,t1ctl4 ; T1IC/CR Edge Selection |
||
161 | t1cr_out_ena dbit 3,t1ctl4 ; T1IC/CR PWM Toggle Enable |
||
162 | t1c1_rst_ena dbit 4,t1ctl4 ; Comparator Reset Enable |
||
163 | t1c2_out_ena dbit 5,t1ctl4 ; Capture/Compare Register PWM Toggle Enable |
||
164 | t1c1_out_ena dbit 6,t1ctl4 ; Compare Register PWM Toggle Enable |
||
165 | t1_mode dbit 7,t1ctl4 ; Timer 1 Mode |
||
166 | |||
167 | t1pc1 equ p04d |
||
168 | t1evt_data_dir dbit 0,t1pc1 ; Timer 1 Event Pin Data Direction |
||
169 | t1evt_function dbit 1,t1pc1 ; Timer 1 Event Pin Function Selection |
||
170 | t1evt_data_out dbit 2,t1pc1 ; Timer 1 Event Pin Data Output |
||
171 | t1evt_data_in dbit 3,t1pc1 ; Timer 1 Event Pin Data Input |
||
172 | |||
173 | t1pc2 equ p04e |
||
174 | t1iccr_data_dir dbit 0,t1pc2 ; T1IC/CR Pin Data Direction |
||
175 | t1iccr_function dbit 1,t1pc2 ; T1IC/CR Pin Function Selection |
||
176 | t1iccr_data_out dbit 2,t1pc2 ; T1IC/CR Pin Data Output |
||
177 | t1iccr_data_in dbit 3,t1pc2 ; T1IC/CR Pin Data Input |
||
178 | t1pwm_data_dir dbit 4,t1pc2 ; T1PWM Pin Data Direction |
||
179 | t1pwm_function dbit 5,t1pc2 ; T1PWM Pin Function Selection |
||
180 | t1pwm_data_out dbit 2,t1pc2 ; T1PWM Pin Data Output |
||
181 | t1pwm_data_in dbit 7,t1pc2 ; T1PWM Pin Data Input |
||
182 | |||
183 | t1pri equ p04f |
||
184 | t1_priority dbit 6,t1pri ; Timer 1 Interrupt Priority |
||
185 | t1_stest dbit 7,t1pri ; Timer 1 Self Test |
||
186 | endif |
||
187 | |||
188 | ;---------------------------------------------------------------------------- |
||
189 | ; Timer 2 |
||
190 | |||
191 | if MOMCPU>370C030H |
||
192 | t2cntrh equ p060 ; Count Register |
||
193 | t2cntrl equ p061 |
||
194 | |||
195 | t2ch equ p062 ; Compare Register |
||
196 | t2cl equ p063 |
||
197 | |||
198 | t2cch equ p064 ; Capture/Compare Register |
||
199 | t2ccl equ p065 |
||
200 | |||
201 | t2ich equ p066 ; Capture Register |
||
202 | t2icl equ p067 |
||
203 | |||
204 | t2ctl1 equ p06a |
||
205 | t2_sw_reset dbit 0,t2ctl1 ; Reset Counter |
||
206 | t2_input_select0 dbit 1,t2ctl1 ; Clock Source |
||
207 | t2_input_select1 dbit 2,t2ctl1 |
||
208 | t2_ovrfl_int_flag dbit 3,t2ctl1 ; Overflow Interrupt Flag |
||
209 | t2_ovrfl_int_ena dbit 4,t2ctl1 ; Overflow Interrupt Enable |
||
210 | |||
211 | t2ctl2 equ p06b |
||
212 | t2c1_int_ena dbit 0,t2ctl2 ; Compare Register Interrupt Enable |
||
213 | t2c2_int_ena dbit 1,t2ctl2 ; Capture/Compare Register Interrupt Enable |
||
214 | t2edge1_int_ena dbit 2,t2ctl2 ; Edge on T2IC1/CR Interrupt Enable |
||
215 | t2c1_int_flag dbit 5,t2ctl2 ; Compare Register Interrupt Flag |
||
216 | t2c2_int_flag dbit 6,t2ctl2 ; Capture/Compare Register Interrupt Flag |
||
217 | t2edge1_int_flag dbit 7,t2ctl2 ; Edge on T2IC1/CR Interrupt Flag |
||
218 | |||
219 | t2ctl3 equ p06c |
||
220 | t2edge1_det_ena dbit 0,t2ctl3 ; T2IC1/CR Edge Detector Enable |
||
221 | t2edge1_rst_ena dbit 1,t2ctl3 ; External Reset Enable |
||
222 | t2edge2_det_ena dbit 1,t2ctl3 ; T2IC2/CR Edge Detector Enable |
||
223 | t2edge1_polarity dbit 2,t2ctl3 ; T2IC1/CR Edge Selection |
||
224 | t2edge1_out_ena dbit 3,t2ctl3 ; T2IC1/CR PWM Toggle Enable |
||
225 | t2edge2_polarity dbit 3,t2ctl3 ; T2IC2/CR Edge Selection |
||
226 | t2c1_rst_ena dbit 4,t2ctl3 ; Comparator Reset Enable |
||
227 | t2c2_out_ena dbit 5,t2ctl3 ; Capture/Compare Register PWM Toggle Enable |
||
228 | t2c1_out_ena dbit 6,t2ctl3 ; Capture Register PWM Toggle Enable |
||
229 | t2_mode dbit 7,t2ctl3 ; Timer 2 Mode |
||
230 | |||
231 | t2pc1 equ p06d |
||
232 | t2evt_data_dir dbit 0,t2pc1 ; Timer 2 Event Pin Data Direction |
||
233 | t2evt_function dbit 1,t2pc1 ; Timer 2 Event Pin Function Selection |
||
234 | t2evt_data_out dbit 2,t2pc1 ; Timer 2 Event Pin Data Output |
||
235 | t2evt_data_in dbit 3,t2pc1 ; Timer 2 Event Pin Data Input |
||
236 | |||
237 | t2pc2 equ p06e |
||
238 | t2ic1cr_data_dir dbit 0,t1pc2 ; T2IC1/CR Pin Data Direction |
||
239 | t2ic1cr_function dbit 1,t1pc2 ; T2IC1/CR Pin Function Selection |
||
240 | t2ic1cr_data_out dbit 2,t1pc2 ; T2IC1/CR Pin Data Output |
||
241 | t2ic1cr_data_in dbit 3,t1pc2 ; T2IC1/CR Pin Data Input |
||
242 | t2ic2cr_data_dir dbit 4,t1pc2 ; T2IC2/CR Pin Data Direction |
||
243 | t2ic2cr_function dbit 5,t1pc2 ; T2IC2/CR Pin Function Selection |
||
244 | t2ic2cr_data_out dbit 6,t1pc2 ; T2IC2/CR Pin Data Output |
||
245 | t2ic2cr_data_in dbit 7,t1pc2 ; T2IC2/CR Pin Data Input |
||
246 | t2pwm_data_dir dbit 4,t1pc2 ; T2PWM Pin Data Direction |
||
247 | t2pwm_function dbit 5,t1pc2 ; T2PWM Pin Function Selection |
||
248 | t2pwm_data_out dbit 6,t1pc2 ; T2PWM Pin Data Output |
||
249 | t2pwm_data_in dbit 7,t1pc2 ; T2PWM Pin Data Input |
||
250 | |||
251 | t2pri equ p06f |
||
252 | t2_priority dbit 6,t2pri ; Timer 2 Interrupt Priority |
||
253 | t2_stest dbit 7,t2pri ; Timer 2 Self Test |
||
254 | endif |
||
255 | |||
256 | ;---------------------------------------------------------------------------- |
||
257 | ; Watchdog |
||
258 | |||
259 | if MOMCPU<>370C030h |
||
260 | wdcntrh equ p046 ; Count Register |
||
261 | wdcntrl equ p047 |
||
262 | |||
263 | wdrst equ p048 ; Reset Key Register |
||
264 | |||
265 | wd_input_select0 dbit 4,t1ctl1 ; Clock Source |
||
266 | wd_input_select1 dbit 5,t1ctl1 |
||
267 | wd_input_select2 dbit 6,t1ctl1 |
||
268 | wd_ovrfl_tap_sel dbit 7,t1ctl1 ; Count Tith 15 or 16 Bits |
||
269 | wd_ovrfl_int_flag dbit 5,t1ctl2 ; Watchdog Reset Flag |
||
270 | wd_ovrfl_int_ena dbit 6,t1ctl2 ; Watchdog Interrupt Enable |
||
271 | wd_ovrfl_rst_ena dbit 7,t1ctl2 ; Watchdog Reset Enable |
||
272 | endif |
||
273 | |||
274 | ;---------------------------------------------------------------------------- |
||
275 | ; SCI |
||
276 | |||
277 | if (MOMCPU=370C020h)||(MOMCPU>370C030h) |
||
278 | sciccr equ p050 |
||
279 | sci_char0 dbit 0,sciccr ; Character Length |
||
280 | sci_char1 dbit 1,sciccr |
||
281 | sci_char2 dbit 2,sciccr |
||
282 | address_idle_wup dbit 3,sciccr ; Multi Processor Mode |
||
283 | async_iosync dbit 4,sciccr ; Synchronous/Asynchronous Mode |
||
284 | parity_enable dbit 5,sciccr ; Parity Enable |
||
285 | even_odd_parity dbit 6,sciccr ; Even or Odd Parity |
||
286 | stop_bits dbit 7,sciccr ; Number of Stopbits |
||
287 | |||
288 | scictl equ p051 |
||
289 | rxena dbit 0,scictl ; Receiver Enable |
||
290 | txena dbit 1,scictl ; Transmitter Enable |
||
291 | sleep dbit 2,scictl ; SCI Sleep Mode |
||
292 | txwake dbit 3,scictl ; Transmitter Wake |
||
293 | clock dbit 4,scictl ; SCI Internal or External Clock |
||
294 | sci_sw_reset dbit 5,scictl ; Software Reset |
||
295 | |||
296 | baud_msb equ p052 ; Baud Rate Generator |
||
297 | baud_lsb equ p053 |
||
298 | |||
299 | txctl equ p054 |
||
300 | sci_tx_int_ena dbit 0,txctl ; Transmitter Interrupt Enable |
||
301 | tx_empty dbit 6,txctl ; Transmitter Entirely Empty |
||
302 | txrdy dbit 7,txctl ; Transmitter Redy to Accept Character |
||
303 | |||
304 | rxctl equ p055 |
||
305 | sci_rx_int_ena dbit 0,rxctl ; Receiver Interrupt Enable |
||
306 | rxwake dbit 1,rxctl ; Receiver Woken Up |
||
307 | sci_pe dbit 2,rxctl ; Parity Error |
||
308 | sci_oe dbit 3,rxctl ; Overflow Error |
||
309 | sci_fe dbit 4,rxctl ; Framing Error |
||
310 | brkdt dbit 5,rxctl ; Break Detected |
||
311 | rxrdy dbit 6,rxctl ; Character Detected |
||
312 | rx_error dbit 7,rxctl ; Receive Error |
||
313 | |||
314 | rxbuf equ p057 ; Data Register |
||
315 | txbuf equ p059 |
||
316 | |||
317 | scipc1 equ p05d |
||
318 | sciclk_data_dir dbit 0,scipc1 ; SCICLK Pin Data Direction |
||
319 | sciclk_function dbit 1,scipc1 ; SCICLK Pin Function Select |
||
320 | sciclk_data_out dbit 2,scipc1 ; SCICLK Pin Data Output |
||
321 | sciclk_data_in dbit 3,scipc1 ; SCICLK Pin Data Input |
||
322 | |||
323 | scipc2 equ p05e |
||
324 | scirxd_data_dir dbit 0,scipc2 ; SCIRXD-Pin Data Direction |
||
325 | scirxd_function dbit 1,scipc2 ; SCIRXD-Pin Function Select |
||
326 | scirxd_data_out dbit 2,scipc2 ; SCIRXD-Pin Data Output |
||
327 | scirxd_data_in dbit 3,scipc2 ; SCIRXD-Pin Data Input |
||
328 | scitxd_data_dir dbit 4,scipc2 ; SCITXD-Pin Data Direction |
||
329 | scitxd_function dbit 5,scipc2 ; SCITXD-Pin Function Select |
||
330 | scitxd_data_out dbit 6,scipc2 ; SCITXD-Pin Data Output |
||
331 | scitxd_data_in dbit 7,scipc2 ; SCITXD-Pin Data Input |
||
332 | |||
333 | scipri equ p05f |
||
334 | sci_espen dbit 4,scipri ; SCI Emulator Suspend |
||
335 | scirx_priority dbit 5,scipri ; SCI Receiver Interrupt Priority |
||
336 | scitx_priority dbit 6,scipri ; SCI Transmitter Interrupt Priority |
||
337 | sci_test dbit 7,scipri ; SCI Self Test |
||
338 | endif |
||
339 | |||
340 | ;---------------------------------------------------------------------------- |
||
341 | ; SPI |
||
342 | |||
343 | if (MOMCPU<370C030h)||(MOMCPU=370C050h) |
||
344 | spiccr equ p030 |
||
345 | spi_char0 dbit 0,spiccr ; Character Length |
||
346 | spi_char1 dbit 1,spiccr |
||
347 | spi_char2 dbit 2,spiccr |
||
348 | spi_bit_rate0 dbit 3,spiccr ; Bit Rate |
||
349 | spi_bit_rate1 dbit 4,spiccr |
||
350 | spi_bit_rate2 dbit 5,spiccr |
||
351 | clock_polarity dbit 6,spiccr ; Clock Polarity |
||
352 | spi_sw_reset dbit 7,spiccr ; Software Reset |
||
353 | |||
354 | spictl equ p031 |
||
355 | spi_int_ena dbit 0,spictl ; Interrupt Freigabe |
||
356 | talk dbit 1,spictl ; Slave/Master Transmitter Enable |
||
357 | master_slave dbit 2,spictl ; Slave/Master Select |
||
358 | spi_int_flag dbit 6,spictl ; Interrupt Flag |
||
359 | receiver_overrun dbit 7,spictl ; Receiver Overflow |
||
360 | |||
361 | spibuf equ p037 ; Receive Buffer |
||
362 | spidat equ p039 ; Transmit Register |
||
363 | |||
364 | spipc1 equ p03d |
||
365 | spiclk_data_dir dbit 0,spipc1 ; SPICLK Pin Data Direction |
||
366 | spiclk_function dbit 1,spipc1 ; SPICLK Pin Function Select |
||
367 | spiclk_data_out dbit 2,spipc1 ; SPICLK Pin Data Output |
||
368 | spiclk_data_in dbit 3,spipc1 ; SPICLK Pin Data Input |
||
369 | |||
370 | spipc2 equ p03e |
||
371 | spisomi_data_dir dbit 0,spipc2 ; SPISOMI Pin Data Direction |
||
372 | spisomi_function dbit 1,spipc2 ; SPISOMI Pin Function Select |
||
373 | spisomi_data_out dbit 2,spipc2 ; SPISOMI Pin Data Output |
||
374 | spisomi_data_in dbit 3,spipc2 ; SPISOMI Pin Data Input |
||
375 | spimosi_data_dir dbit 4,spipc2 ; SPIMOSI Pin Data Direction |
||
376 | spimosi_function dbit 5,spipc2 ; SPIMOSI Pin Function Select |
||
377 | spimosi_data_out dbit 6,spipc2 ; SPIMOSI Pin Data Output |
||
378 | spimosi_data_in dbit 7,spipc2 ; SPIMOSI Pin Data Input |
||
379 | |||
380 | spipri equ p03f |
||
381 | spi_espen dbit 5,spipri ; Suppress Emulator |
||
382 | spi_priority dbit 6,spipri ; Interrupt Priority |
||
383 | spi_stest dbit 7,spipri ; Self Test |
||
384 | endif |
||
385 | |||
386 | ;---------------------------------------------------------------------------- |
||
387 | ; A/D Converter |
||
388 | |||
389 | if MOMCPU>370C030h |
||
390 | adctl equ p070 |
||
391 | ad_input_select0 dbit 0,adctl ; Channel Selection |
||
392 | ad_input_select1 dbit 1,adctl |
||
393 | ad_input_select2 dbit 2,adctl |
||
394 | ref_volt_select0 dbit 3,adctl ; Reference Voltage Selection |
||
395 | ref_volt_select1 dbit 4,adctl |
||
396 | ref_volt_select2 dbit 5,adctl |
||
397 | sample_start dbit 6,adctl ; Start Sample Phase (auto-clear) |
||
398 | convert_start dbit 7,adctl ; Start Conversion Phase |
||
399 | |||
400 | adstat equ p071 |
||
401 | ad_int_ena dbit 0,adstat ; Interrupt Enable |
||
402 | ad_int_flag dbit 1,adstat ; Interrupt Flag |
||
403 | ad_ready dbit 2,adstat ; AD Converter Ready? |
||
404 | |||
405 | addata equ p072 ; Conversion Result |
||
406 | adin equ p07d ; Digital Input Data if Unused as Analog Inputs |
||
407 | adena equ p07e ; Enable Analog Inputs |
||
408 | |||
409 | adpri equ p07f |
||
410 | ad_espen dbit 5,adpri ; Suppress Emulator |
||
411 | ad_priority dbit 6,adpri ; Interrupt Priority |
||
412 | ad_stest dbit 7,adpri ; Self Test |
||
413 | endif |
||
414 | |||
415 | ;---------------------------------------------------------------------------- |
||
416 | ; PACT |
||
417 | |||
418 | if MOMCPU=370C030h |
||
419 | pact_scr equ p040 |
||
420 | pact_prescale_select0 dbit 0,pact_scr ; Prescaler Selection |
||
421 | pact_prescale_select1 dbit 1,pact_scr |
||
422 | pact_prescale_select2 dbit 2,pact_scr |
||
423 | pact_prescale_select3 dbit 3,pact_scr |
||
424 | fast_mode_select dbit 4,pact_scr ; Disable Prescaler-by-8 |
||
425 | cmd_def_area_ena dbit 5,pact_scr ; Enable Dual-Port-RAM Access |
||
426 | deftim_ovrfl_int_flag dbit 6,pact_scr ; Timer Overflow Interrupt Flag |
||
427 | deftim_ovrfl_int_ena dbit 7,pact_scr ; Timer Overflow Interrupt Enable |
||
428 | |||
429 | cdstart equ p041 |
||
430 | cmd_def_area2 dbit 2,cdstart ; Command/Definition Area Start Address |
||
431 | cmd_def_area3 dbit 3,cdstart |
||
432 | cmd_def_area4 dbit 4,cdstart |
||
433 | cmd_def_area5 dbit 5,cdstart |
||
434 | cmd_def_area_int_ena dbit 7,cdstart ; Enable Interrupts |
||
435 | |||
436 | cdend equ p042 |
||
437 | cmd_def_area_end2 dbit 2,cdend ; Command/Definition Area End Address |
||
438 | cmd_def_area_end3 dbit 3,cdend |
||
439 | cmd_def_area_end4 dbit 4,cdend |
||
440 | cmd_def_area_end5 dbit 5,cdend |
||
441 | cmd_def_area_end6 dbit 6,cdend |
||
442 | |||
443 | bufptr equ p043 |
||
444 | buffer_pointer1 dbit 1,bufptr ; Buffer Pointer Address |
||
445 | buffer_pointer2 dbit 2,bufptr |
||
446 | buffer_pointer3 dbit 3,bufptr |
||
447 | buffer_pointer4 dbit 4,bufptr |
||
448 | buffer_pointer5 dbit 5,bufptr |
||
449 | |||
450 | scictlp equ p045 |
||
451 | sci_sw_reset dbit 0,scictlp ; Software Reset |
||
452 | sci_tx_int_ena dbit 2,scictlp ; Transmit Interrupt Enable |
||
453 | sci_rx_int_ena dbit 3,scictlp ; Receive Interrupt Enable |
||
454 | pact_fe dbit 4,scictlp ; Framing Error |
||
455 | pact_parity dbit 5,scictlp ; Parity Error |
||
456 | pact_txrdy dbit 6,scictlp ; Transmitter Empty |
||
457 | pact_rxrdy dbit 7,scictlp ; Receive Buffer Full |
||
458 | |||
459 | rxbufp equ p046 ; Mini-SCI Receive Buffer |
||
460 | txbufp equ p047 ; Mini-SCI Transmit Buffer |
||
461 | |||
462 | opstate equ p048 ; Output Pin State |
||
463 | cdflags equ p049 ; Command 0..7 Interrupt Flags |
||
464 | |||
465 | cpctl1 equ p04a |
||
466 | cp1_capt_falling_edge dbit 0,cpctl1 ; CP1 Falling Edge Capture |
||
467 | cp1_capt_rising_edge dbit 1,cpctl1 ; CP1 Rising Edge Capture |
||
468 | cp1_int_flag dbit 2,cpctl1 ; CP1 Edge Occured |
||
469 | cp1_int_ena dbit 3,cpctl1 ; CP1 Interrupt Enable |
||
470 | cp2_capt_falling_edge dbit 4,cpctl1 ; CP2 Falling Edge Capture |
||
471 | cp2_capt_rising_edge dbit 5,cpctl1 ; CP2 Rising Edge Capture |
||
472 | cp2_int_flag dbit 6,cpctl1 ; CP2 Edge Occured |
||
473 | cp2_int_ena dbit 7,cpctl1 ; CP2 Interrupt Enable |
||
474 | |||
475 | cpctl2 equ p04b |
||
476 | cp3_capt_falling_edge dbit 0,cpctl2 ; CP3 Falling Edge Capture |
||
477 | cp3_capt_rising_edge dbit 1,cpctl2 ; CP3 Rising Edge Capture |
||
478 | cp3_int_flag dbit 2,cpctl2 ; CP3 Edge Occured |
||
479 | cp3_int_ena dbit 3,cpctl2 ; CP3 Interrupt Enable |
||
480 | cp4_capt_falling_edge dbit 4,cpctl2 ; CP4 Falling Edge Capture |
||
481 | cp4_capt_rising_edge dbit 5,cpctl2 ; CP4 Rising Edge Capture |
||
482 | cp4_int_flag dbit 6,cpctl2 ; CP4 Edge Occured |
||
483 | cp4_int_ena dbit 7,cpctl2 ; CP4 Interrupt Enable |
||
484 | |||
485 | cpctl3 equ p04c |
||
486 | cp5_capt_falling_edge dbit 0,cpctl3 ; CP5 Falling Edge Capture |
||
487 | cp5_capt_rising_edge dbit 1,cpctl3 ; CP5 Rising Edge Capture |
||
488 | cp5_int_flag dbit 2,cpctl3 ; CP5 Edge Occured |
||
489 | cp5_int_ena dbit 3,cpctl3 ; CP5 Interrupt Enable |
||
490 | cp6_capt_falling_edge dbit 4,cpctl3 ; CP6 Falling Edge Capture |
||
491 | cp6_capt_rising_edge dbit 5,cpctl3 ; CP6 Rising Edge Capture |
||
492 | cp6_int_flag dbit 6,cpctl3 ; CP6 Edge Occured |
||
493 | cp6_int_ena dbit 7,cpctl3 ; CP6 Interrupt Enable |
||
494 | |||
495 | cppre equ p04d |
||
496 | op_set_clr_select dbit 0,cppre ; Set/Reset Output Pins in Software |
||
497 | event_counter_sw_reset dbit 1,cppre ; Reset Event Counter |
||
498 | cp6_event_only dbit 2,cppre ; CP6 only for Event Counter |
||
499 | input_capt_prescale_select0 dbit 3,cppre; CP3..CP6 Prescaler |
||
500 | input_capt_prescale_select1 dbit 4,cppre |
||
501 | input_capt_prescale_select2 dbit 5,cppre |
||
502 | buffer_half_full_int_flag dbit 6,cppre ; Buffer Half/Full Interrupt Flag |
||
503 | buffer_half_full_int_ena dbit 7,cppre ; Buffer Half/Full Interrupt Enable |
||
504 | |||
505 | wdrst equ p04e |
||
506 | |||
507 | pactpri equ p04f |
||
508 | wd_prescale_select0 dbit 0,pactpri ; Watchdog Prescaler |
||
509 | wd_prescale_select1 dbit 1,pactpri |
||
510 | pact_mode_select dbit 2,pactpri ; PACT Mode A/B Select |
||
511 | pact_group_3_priority dbit 3,pactpri ; Interrupt Groups Priority |
||
512 | pact_group_2_priority dbit 4,pactpri |
||
513 | pact_group_1_priority dbit 5,pactpri |
||
514 | pact_stest dbit 7,pactpri ; Self Test |
||
515 | endif |
||
516 | |||
517 | ;---------------------------------------------------------------------------- |
||
518 | |||
519 | restore ; re-allow listing |
||
520 | |||
521 | endif ; stddef37inc |