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Rev | Author | Line No. | Line |
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1126 | savelij | 1 | ifndef __st7i2cinc ; avoid multiple inclusion |
2 | __st7i2cinc equ 1 |
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3 | |||
4 | save |
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5 | listing off ; no listing over this file |
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6 | |||
7 | ;**************************************************************************** |
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8 | ;* * |
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9 | ;* AS 1.42 - File I2C.INC * |
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10 | ;* * |
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11 | ;* contains SFR and Bit Definitions for ST7 I2C * |
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12 | ;* * |
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13 | ;**************************************************************************** |
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14 | |||
15 | __defi2c macro Base |
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16 | I2CCR label Base+$00 ; Control Register |
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17 | PE bit I2CCR,5 ; Peripheral enable |
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18 | ENGC bit I2CCR,4 ; Enable General Call |
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19 | START bit I2CCR,3 ; Generation of a Start condition |
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20 | ACK bit I2CCR,2 ; Acknowledge enable |
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21 | STOP bit I2CCR,1 ; Generation of a Stop condition |
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22 | ITE bit I2CCR,0 ; Interrupt enable |
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23 | I2CSR1 label Base+$01 ; Status Register 1 |
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24 | EVF bit I2CSR1,7 ; Event flag |
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25 | ADD10 bit I2CSR1,6 ; 10-bit addressing in Master mode |
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26 | TRA bit I2CSR1,5 ; Transmitter/Receiver |
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27 | BUSY bit I2CSR1,4 ; Bus busy |
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28 | BTF bit I2CSR1,3 ; Byte transfer finished |
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29 | ADSL bit I2CSR1,2 ; Address matched (Slave mode) |
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30 | M_SL bit I2CSR1,1 ; Master/Slave |
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31 | SB bit I2CSR1,0 ; Start bit (Master mode) |
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32 | I2CSR2 label Base+$02 ; Status Register 2 |
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33 | AF bit I2CSR2,4 ; Acknowledge failure |
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34 | STOPF bit I2CSR2,3 ; Stop detection (Slave mode) |
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35 | ARLO bit I2CSR2,2 ; Arbitration lost |
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36 | BERR bit I2CSR2,1 ; Bus error |
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37 | GCAL bit I2CSR2,0 ; General Call (Slave mode) |
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38 | I2CCCR label Base+$03 ; Clock Control Register |
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39 | FM_SM bit I2CCCR,7 ; Fast/Standard I2C mode |
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40 | I2COAR1 label Base+$04 ; Own Address Register 1 |
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41 | I2COAR2 label Base+$05 ; Own Address Register 2 |
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42 | FR bfield I2COAR2,6,2 ; Frequency bits |
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43 | I2CDR label Base+$06 ; Data Register |
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44 | endm |
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45 | |||
46 | restore |
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47 | endif ; __st7i2cinc |