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1126 savelij 1
		ifndef	__st7i2cinc	; avoid multiple inclusion
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__st7i2cinc	equ	1
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		save
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		listing	off		; no listing over this file
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;****************************************************************************
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;*                                                                          *
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;*   AS 1.42 - File I2C.INC                                                 *
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;*                                                                          *
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;*   contains SFR and Bit Definitions for ST7 I2C                           *
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;*                                                                          *
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;****************************************************************************
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__defi2c	macro	Base
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I2CCR		label	Base+$00	; Control Register
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PE		bit	I2CCR,5		;  Peripheral enable
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ENGC		bit	I2CCR,4		;  Enable General Call
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START		bit	I2CCR,3		;  Generation of a Start condition
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ACK		bit	I2CCR,2		;  Acknowledge enable
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STOP		bit	I2CCR,1		;  Generation of a Stop condition
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ITE		bit	I2CCR,0		;  Interrupt enable
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I2CSR1		label	Base+$01	; Status Register 1
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EVF		bit	I2CSR1,7	;  Event flag
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ADD10		bit	I2CSR1,6	;  10-bit addressing in Master mode
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TRA		bit	I2CSR1,5	;  Transmitter/Receiver
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BUSY		bit	I2CSR1,4	;  Bus busy
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BTF		bit	I2CSR1,3	;  Byte transfer finished
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ADSL		bit	I2CSR1,2	;  Address matched (Slave mode)
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M_SL		bit	I2CSR1,1	;  Master/Slave
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SB		bit	I2CSR1,0	;  Start bit (Master mode)
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I2CSR2		label	Base+$02	; Status Register 2
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AF		bit	I2CSR2,4	;  Acknowledge failure
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STOPF		bit	I2CSR2,3	;  Stop detection (Slave mode)
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ARLO		bit	I2CSR2,2	;  Arbitration lost
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BERR		bit	I2CSR2,1	;  Bus error
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GCAL		bit	I2CSR2,0	;  General Call (Slave mode)
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I2CCCR		label	Base+$03	; Clock Control Register
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FM_SM		bit	I2CCCR,7	;  Fast/Standard I2C mode
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I2COAR1		label	Base+$04	; Own Address Register 1
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I2COAR2		label	Base+$05	; Own Address Register 2
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FR		bfield	I2COAR2,6,2	;  Frequency bits
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I2CDR		label	Base+$06	; Data Register
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		endm
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		restore
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		endif			; __st7i2cinc