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1186 savelij 1
		ifndef	__s12z_spi_inc
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__s12z_spi_inc	equ	1
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		save
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		listing	off	; no listing over this file
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;****************************************************************************
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;*                                                                          *
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;*   AS 1.42 - File S12ZSPI.INC                                             *
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;*                                                                          *
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;*   Contains Bit & Register Definitions for S12Z Serial/Parallel Interface *
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;*                                                                          *
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;****************************************************************************
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		padding	off
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S12ZSPI		struct	dots
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CR1		ds.b	1		; ($00) SPI Control Register 1
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SPIE		s12zbit	CR1,7		;  SPI Interrupt Enable Bit
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SPE		s12zbit	CR1,6		;  SPI System Enable Bit
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SPTIE		s12zbit	CR1,5		;  SPI Transmit Interrupt Enable
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MSTR		s12zbit	CR1,4		;  SPI Master/Slave Mode Select Bit
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CPOL		s12zbit	CR1,3		;  SPI Clock Polarity Bit
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CPHA		s12zbit	CR1,2		;  SPI Clock Phase Bit
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SSOE		s12zbit	CR1,1		;  Slave Select Output Enable
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LSBFE		s12zbit	CR1,0		;  LSB-First Enable
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CR2		ds.b	1		; ($01) SPI Control Register 2
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XFRW		s12zbit	CR2,6		;  Transfer Width
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MODFEN		s12zbit	CR2,4		;  Mode Fault Enable Bit
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BIDIROE		s12zbit	CR2,3		;  Output Enable in the Bidirectional Mode of Operation
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SPISWAI		s12zbit	CR2,1		;  SPI Stop in Wait Mode Bit
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SPC0		s12zbit	CR2,0		;  Serial Pin Control Bit 0
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BR		ds.b	1		; ($02) SPI Baud Rate Register
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SPPR		s12zfld	BR,3:4		;  SPI Baud Rate Preselection Bits
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SPR		s12zfld	BR,3:0		;  SPI Baud Rate Selection Bits
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SR		ds.b	1		; ($03) SPI Status Register
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SPIF		s12zbit	SR,7		;  SPIF Interrupt Flag
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SPTEF		s12zbit	SR,5		;  SPI Transmit Empty Interrupt Flag
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MODF		s12zbit	SR,4		;  Mode Fault Flag
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DR		ds.w	0		; ($04) SPI Data Register (16 bits)
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DRH		ds.b	1		; ($04) SPI Data Register MSB
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DRL		ds.b	1		; ($05) SPI Data Register LBS
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		ends	S12ZSPI
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		restore			; re-enable listing
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		endif			; __s12z_spi_inc