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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1186 | savelij | 1 | ifndef regz380inc ; avoid multiple inclusion |
| 2 | reg380inc equ 1 |
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| 3 | |||
| 4 | save |
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| 5 | listing off ; no listing over this file |
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| 6 | ;**************************************************************************** |
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| 7 | ;* * |
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| 8 | ;* AS 1.42 - File REGZ380.INC * |
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| 9 | ;* * |
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| 10 | ;* Contains Register Definitions for the Z380 * |
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| 11 | ;* These Registers may only be accessed via the instructions IN0, OUT0, * |
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| 12 | ;* and TSTIO. * |
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| 13 | ;* * |
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| 14 | ;**************************************************************************** |
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| 15 | |||
| 16 | if (MOMCPU<>896) |
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| 17 | fatal "wrong target selected: only Z380 allowed" |
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| 18 | endif |
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| 19 | |||
| 20 | |||
| 21 | if MOMPASS=1 |
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| 22 | message "Z380 Register Definitions (C) 1994 Alfred Arnold, Leonhard Schneider" |
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| 23 | endif |
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| 24 | |||
| 25 | ;---------------------------------------------------------------------------- |
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| 26 | |||
| 27 | LMCS0 port 00h ; Lower Memory Chip Select Registers |
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| 28 | LMCS1 port 01h |
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| 29 | UMCS0 port 02h ; Upper Memory Chip Select Registers |
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| 30 | UMCS1 port 03h |
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| 31 | MMCS0 port 04h ; Midrange Memory Chip Select Registers |
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| 32 | MMCS1 port 05h |
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| 33 | MMCS2 port 06h |
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| 34 | MMCS3 port 07h |
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| 35 | LMWR port 08h ; Lower Memory Waits Register |
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| 36 | UMWR port 09h ; Upper Memory Waits Register |
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| 37 | MMWR0 port 0ah ; Midrange Memory Waits Registers |
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| 38 | MMWR1 port 0bh |
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| 39 | MMWR2 port 0ch |
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| 40 | MMWR3 port 0dh |
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| 41 | IOWR port 0eh ; I/O Waits Register |
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| 42 | RFWR port 0fh ; Refresh Waits Register |
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| 43 | MSMER port 10h ; Memory Select Master Enable Register |
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| 44 | IOCR0 port 11h ; I/O Bus Control Registers |
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| 45 | IOCR1 port 12h |
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| 46 | RFSHR0 port 13h ; Refresh Registers |
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| 47 | RFSHR1 port 14h |
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| 48 | RFSHR2 port 15h |
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| 49 | SMCR port 16h ; Standby Mode Control Register |
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| 50 | IER port 17h ; Interrupt Enable |
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| 51 | AVBR port 18h ; Interrupt Vectors Offset |
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| 52 | TRPBK port 19h ; indicates whether trap or break occured |
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| 53 | |||
| 54 | CHIPVERSION port 0ffh ; Chip Version (00=Z380MPU) |
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| 55 | |||
| 56 | ;---------------------------------------------------------------------------- |
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| 57 | |||
| 58 | restore ; re-allow listing |
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| 59 | |||
| 60 | endif ; reg380inc |
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| 61 | |||
| 62 |