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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1126 | savelij | 1 | ifndef __regs12zinc ; avoid multiple inclusion |
| 2 | __regs12zinc equ 1 |
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| 3 | |||
| 4 | save |
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| 5 | listing off ; no listing over this file |
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| 6 | |||
| 7 | ;**************************************************************************** |
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| 8 | ;* * |
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| 9 | ;* AS 1.42 - File REGS12Z.INC * |
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| 10 | ;* * |
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| 11 | ;* Contains SFR and Bit Definitions for AVR Processors * |
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| 12 | ;* * |
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| 13 | ;**************************************************************************** |
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| 14 | |||
| 15 | ;---------------------------------------------------------------------------- |
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| 16 | ; Bits with the name as given in the datasheets contain the plain bit |
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| 17 | ; position within the register; with the prefix _bit_..., they hold |
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| 18 | ; register and bit position |
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| 19 | |||
| 20 | s12zbit macro {intlabel},reg,pos |
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| 21 | __LABEL__ defbit.ATTRIBUTE reg,pos |
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| 22 | endm |
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| 23 | |||
| 24 | s12zfld macro {intlabel},reg,widthandstart |
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| 25 | __LABEL__ defbitfield.ATTRIBUTE reg,widthandstart |
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| 26 | endm |
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| 27 | |||
| 28 | ;---------------------------------------------------------------------------- |
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| 29 | ; include proper CPU-specific register definitions |
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| 30 | |||
| 31 | if MOMPASS=1 |
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| 32 | message "NXP S12Z SFR Definitions (C) 2018 Alfred Arnold" |
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| 33 | endif |
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| 34 | |||
| 35 | switch MOMCPUNAME |
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| 36 | |||
| 37 | case "S912ZVC19F0MKH" |
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| 38 | include "s12z/vc/19f0mkh.inc" |
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| 39 | case "S912ZVC19F0MLF" |
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| 40 | include "s12z/vc/19f0mlf.inc" |
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| 41 | case "S912ZVCA19F0MKH" |
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| 42 | include "s12z/vca/19f0mkh.inc" |
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| 43 | case "S912ZVCA19F0MLF" |
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| 44 | include "s12z/vca/19f0mlf.inc" |
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| 45 | case "S912ZVCA19F0WKH" |
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| 46 | include "s12z/vca/19f0wkh.inc" |
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| 47 | case "S912ZVH128F2CLQ" |
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| 48 | include "s12z/vh/128f2clq.inc" |
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| 49 | case "S912ZVH128F2CLL" |
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| 50 | include "s12z/vh/128f2cll.inc" |
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| 51 | case "S912ZVH64F2CLQ" |
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| 52 | include "s12z/vh/64f2clq.inc" |
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| 53 | case "S912ZVHY64F1CLQ" |
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| 54 | include "s12z/vhy/64f1clq.inc" |
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| 55 | case "S912ZVHY32F1CLQ" |
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| 56 | include "s12z/vhy/32f1clq.inc" |
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| 57 | case "S912ZVHY64F1CLL" |
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| 58 | include "s12z/vhy/64f1cll.inc" |
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| 59 | case "S912ZVHY32F1CLL" |
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| 60 | include "s12z/vhy/32f1cll.inc" |
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| 61 | case "S912ZVHL64F1CLQ" |
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| 62 | include "s12z/vhl/64f1clq.inc" |
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| 63 | case "S912ZVHL32F1CLQ" |
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| 64 | include "s12z/vhl/32f1clq.inc" |
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| 65 | case "S912ZVHL64F1CLL" |
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| 66 | include "s12z/vhl/64f1cll.inc" |
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| 67 | case "S912ZVHL32F1CLL" |
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| 68 | include "s12z/vhl/32f1cll.inc" |
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| 69 | case "S912ZVFP64F1CLQ" |
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| 70 | include "s12z/vfp/64f1clq.inc" |
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| 71 | case "S912ZVFP64F1CLL" |
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| 72 | include "s12z/vfp/64f1cll.inc" |
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| 73 | case "S912ZVH128F2VLQ" |
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| 74 | include "s12z/vh/128f2vlq.inc" |
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| 75 | case "S912ZVH128F2VLL" |
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| 76 | include "s12z/vh/128f2vll.inc" |
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| 77 | case "S912ZVH64F2VLQ" |
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| 78 | include "s12z/vh/64f2vlq.inc" |
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| 79 | case "S912ZVHY64F1VLQ" |
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| 80 | include "s12z/vhy/64f1vlq.inc" |
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| 81 | case "S912ZVHY32F1VLQ" |
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| 82 | include "s12z/vhy/32f1vlq.inc" |
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| 83 | case "S912ZVHY64F1VL" |
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| 84 | include "s12z/vhy/64f1vl.inc" |
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| 85 | case "S912ZVHY32F1VLL" |
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| 86 | include "s12z/vhy/32f1vll.inc" |
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| 87 | case "S912ZVHL64F1VLQ" |
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| 88 | include "s12z/vhl/64f1vlq.inc" |
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| 89 | |||
| 90 | elsecase |
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| 91 | error "wrong processor type set: only S912ZVH128F2CLQ, S912ZVH128F2CLL, S912ZVH64F2CLQ, S912ZVHY64F1CLQ, S912ZVHY32F1CLQ, S912ZVHY64F1CLL, S912ZVHY32F1CLL, S912ZVHL64F1CLQ, S912ZVHL32F1CLQ, S912ZVHL64F1CLL, S912ZVHL32F1CLL, S912ZVFP64F1CLQ," |
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| 92 | fatal "S912ZVFP64F1CLL, S912ZVH128F2VLQ, S912ZVH128F2VLL, S912ZVH64F2VLQ, S912ZVHY64F1VLQ, S912ZVHY32F1VLQ, S912ZVHY64F1VL, S912ZVHY32F1VLL, S912ZVHL64F1VLQ allowed!" |
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| 93 | endcase |
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| 94 | |||
| 95 | ;---------------------------------------------------------------------------- |
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| 96 | |||
| 97 | restore ; wieder erlauben |
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| 98 | |||
| 99 | endif ; __regs12zinc |