WebSVN – pentevo – Blame – /tools/asl/asl-current/include/regmsp.inc

Rev	Author	Line No.	Line
1126	savelij	1	ifndef regmspinc ; avoid multiple inclusion
		2	regmspinc equ 1
		3
		4	save
		5	listing off ; no listing over this file
		6	;****************************************************************************
		7	;* *
		8	;* AS 1.42 - File REGMSP.INC *
		9	;* *
		10	;* Contains Macro and Register Definitions for MSP430 *
		11	;* *
		12	;****************************************************************************
		13
		14	if (MOMCPUNAME<>"MSP430")&&(MOMCPUNAME<>"MSP430X")
		15	fatal "wrong target selected: only MSP430(X) supported"
		16	endif
		17
		18	if MOMPASS=1
		19	message "MSP430 Register Definitionen (C) 1996/2007 Alfred Arnold, Jose Da Silva"
		20	endif
		21
		22	;----------------------------------------------------------------------------
		23	; General Memory Layout
		24	; ----------------------
		25	;
		26	; 0000 - 000f : Special Function Registers
		27	; 0010 - 00ff : 8bit Peripheral Modules
		28	; 0100 - 01ff : 16bit Peripheral Modules
		29	; 0200 - .... : RAM Memory
		30	; .... - ffdf : Flash Memory
		31	; ffe0 - ffff : Interrupt Vector Table
		32	;
		33	;----------------------------------------------------------------------------
		34
		35	;----------------------------------------------------------------------------
		36	; Status Register
		37
		38	SCG1 equ 128 ; System Clock Generator 1. 1=Turn_Off_SMCLK
		39	SCG0 equ 64 ; System Clock Generator 0. 1=Turn_Off_DCO
		40	OSCOFF equ 32 ; Oscillator Off. 1=Turn_Off_LFXT1CLK
		41	CPUOFF equ 16 ; CPU Off. 1=Turn_Off_CPU (SR)
		42	GIE equ 8 ; General Interrupt Enable (SR)
		43
		44	;----------------------------------------------------------------------------
		45	; Special Function Register of MSP430x1xx Family, Byte Access
		46
		47	IE1 equ 000h ; Interrupt Enable
		48	ACCVIE equ 32 ; Flash Access Interrupt Enable (IE1.5)
		49	NMIIE equ 16 ; NMI Enable (IE1.4)
		50	OFIE equ 2 ; Osc Fault Interrupt Enable (IE1.1)
		51	WDTIE equ 1 ; Watchdog Interrupt Enable (IE1.0)
		52
		53	IFG1 equ 002h ; Interrupt Flag
		54	NMIIFG equ 16 ; Set Via !RST/NMI Pin (IFG1.4)
		55	RSTIFG equ 8 ; External Reset Interrupt Flag (IFG1.3)
		56	PORIFG equ 4 ; Power-on-Reset Interrupt Flag (IFG1.2)
		57	OFIFG equ 2 ; Flag on Oscillator Fault (IFG1.1)
		58	WDTIFG equ 1 ; Watchdog or Security Key Violation (IFG1.0)
		59
		60	ME1 equ 004h ; Module Enable
		61
		62	; MSP43012xx devices only, only for MSP43012xx devices.
		63
		64	IE2 equ 001h
		65	UTXIE0 equ 2 ; USART0 Transmit Int-Enable Bit (IE2.2)
		66	URXIE0 equ 1 ; USART0 Receive Int-Enable Bit (IE2.1)
		67
		68	IFG2 equ 003h
		69	UTXIFG0 equ 2 ; USART0 and SPI Transmit Flag (IFG2.1)
		70	URXIFG0 equ 1 ; USART0 and SPI Receive Flag (IFG2.0)
		71
		72	ME2 equ 005h
		73	UTXE0 equ 2 ; USART0 Transmit Enable Bit (ME2.1)
		74	URXE0 equ 1 ; USART0 Receive Enable Bit (ME2.0)
		75	USPIE0 equ 1 ; SPI Transmit+Receive Enable (ME2.0)
		76
		77	;----------------------------------------------------------------------------
		78	; Digital I/O, Byte Access
		79
		80	P0IN equ 010h ; Read Register (Pin State)
		81	P0OUT equ 011h ; Write Register (Latches)
		82	P0DIR equ 012h ; Direction Register
		83	P0IFG equ 013h ; Interrupt Flags
		84	P0IES equ 014h ; Interrupt Edge Selection
		85	P0IE equ 015h ; Interrupt Enables
		86
		87	P3IN equ 018h ; Input Register
		88	P3OUT equ 019h ; Output Register
		89	P3DIR equ 01Ah ; Direction Register
		90	P3SEL equ 01Bh ; Function Select
		91
		92	P4IN equ 01Ch ; Input Register
		93	P4OUT equ 01Dh ; Output Register
		94	P4DIR equ 01Eh ; Direction Register
		95	P4SEL equ 01Fh ; Function Select
		96
		97	P1IN equ 020h ; Input Register
		98	P1OUT equ 021h ; Output Register
		99	P1DIR equ 022h ; Direction Register
		100	P1IFG equ 023h ; Interrupt Flags
		101	P1IES equ 024h ; Interrupt Edge Select
		102	P1IE equ 025h ; Interrupt Enable
		103	P1SEL equ 026h ; Function Select
		104
		105	P2IN equ 028h ; Input Register
		106	P2OUT equ 029h ; Output Register
		107	P2DIR equ 02Ah ; Direction Register
		108	P2IFG equ 02Bh ; Interrupt Flags
		109	P2IES equ 02Ch ; Interrupt Edge Select
		110	P2IE equ 02Dh ; Interrupt Enable
		111	P2SEL equ 02Eh ; Function Select
		112
		113	P5IN equ 030h ; Input Register
		114	P5OUT equ 031h ; Output Register
		115	P5DIR equ 032h ; Direction Register
		116	P5SEL equ 033h ; Function Select
		117
		118	P6IN equ 034h ; Input Register
		119	P6OUT equ 035h ; Output Register
		120	P6DIR equ 036h ; Direction Register
		121	P6SEL equ 037h ; Function Select
		122
		123	;----------------------------------------------------------------------------
		124	; LCD-Interface
		125
		126	LCDCTL equ 030h ; Control
		127	LCD_Start equ 031h ; Start Address
		128	LCD_Stop equ 03fh ; End Address
		129	__TMP set 1 ; Individual Definitions
		130	rept 9
		131	LCD{"\{__TMP}"} equ 030h+__TMP
		132	__TMP set __TMP+1
		133	endm
		134	rept 6
		135	LCD1{"\{__TMP-10}"} equ 030h+__TMP
		136	__TMP set __TMP+1
		137	endm
		138
		139	;----------------------------------------------------------------------------
		140	; Timer
		141
		142	BTCTL equ 040h ; Timer 1 Basic Control Register
		143
		144	TCCTL equ 042h
		145	TCPLD equ 043h ; Preaload Value
		146	TCDAT equ 044h ; Count Value
		147
		148	BTCNT1 equ 046h ; Count Register
		149	BTCNT2 equ 047h
		150
		151	TPCTL equ 04Bh ; Timer/Port Control Register
		152	TPCNT1 equ 04Ch ; Count Register
		153	TPCNT2 equ 04Dh
		154	TPD equ 04Eh ; Data Register
		155	TPE equ 04Fh ; Enable Register
		156
		157	;----------------------------------------------------------------------------
		158	; Clock Generator
		159
		160	SCFI0 equ 050h ; Integrator
		161	SCFI1 equ 051h
		162	SCFQCTL equ 052h ; Crystal Frequency Multiplicator
		163	CBCTL equ 053h ; Buffer Control
		164
		165	;----------------------------------------------------------------------------
		166	; EPROM Control Registers, Byte Access
		167
		168	EPCTL equ 054h ; EPROM Control
		169
		170	;----------------------------------------------------------------------------
		171	; Basic Clock Registers, Byte Access
		172
		173	DCOCTL equ 056h
		174	DCO2 equ 128 ; DCO Freq Select, see RSELx (DCOCTL.7)
		175	DCO1 equ 64 ; (DCOCTL.6)
		176	DCO0 equ 32 ; (DCOCTL.5)
		177	MOD4 equ 16 ; Modulator Selection (DCOCTL.4)
		178	MOD3 equ 8 ; (DCOCTL.3)
		179	MOD2 equ 4 ; (DCOCTL.2)
		180	MOD1 equ 2 ; (DCOCTL.1)
		181	MOD0 equ 1 ; (DCOCTL.0)
		182
		183	BCSCTL1 equ 057h
		184	XT2OFF equ 128 ; XT2 Off. Turn Off XT2 Oscil (BCSCTL1.7)
		185	XTS equ 64 ; LFXT1 Mode. 0=LowFreq,1=HiFreq (BCSCTL1.6)
		186	DIVA1 equ 32 ; Divider for ACLK. (BCSCTL1.5)
		187	DIVA0 equ 16 ; 00=/1, 01=/2, 10=/4, 11=/8 (BCSCTL1.4)
		188	XT5V equ 8 ; Unused. Always Reset to Zero (BCSCTL1.3)
		189	RSEL2 equ 4 ; Resistor Select. Internal R (BCSCTL1.2)
		190	RSEL1 equ 2 ; Lowest R=0 (BCSCTL1.1)
		191	RSEL0 equ 1 ; (BCSCTL1.0)
		192	RSEL_7 equ 7 ; (BCSCTL1.0-2)
		193	RSEL_6 equ 6 ; (BCSCTL1.0-2)
		194	RSEL_5 equ 5 ; (BCSCTL1.0-2)
		195	RSEL_4 equ 4 ; (BCSCTL1.0-2)
		196	RSEL_3 equ 3 ; (BCSCTL1.0-2)
		197	RSEL_2 equ 2 ; (BCSCTL1.0-2)
		198	RSEL_1 equ 1 ; (BCSCTL1.0-2)
		199	RSEL_0 equ 0 ; (BCSCTL1.0-2)
		200
		201	BCSCTL2 equ 058h
		202	SELM_3 equ 128+64 ; Select MCLK. 11=LFXT1CLK (BCSCTL2.6.7)
		203	SELM_2 equ 128 ; MCLK 10=XT2CLK or LFXT1CLK (BCSCTL2.6.7)
		204	SELM_1 equ 64 ; Select MCLK. 01=DCOCLK (BCSCTL2.6.7)
		205	SELM_0 equ 0 ; Select MCLK. 00=DCOCLK (BCSCTL2.6.7)
		206	SELM1 equ 128 ; Select MCLK. 00=01=DCOCLK (BCSCTL2.7)
		207	SELM0 equ 64 ; 10=XT2CLK or LFXT1CLK=11 (BCSCTL2.6)
		208	DIVM1 equ 32 ; Divider for MCLK, (BCSCTL2.5)
		209	DIVM0 equ 16 ; 00=/1, 01=/2, 10=/4, 11=/8 (BCSCTL2.4)
		210	SELS equ 8 ; Select SMCLK 0=DCOCLK,1=XT2CLK (BCSCTL2.3)
		211	DIVS1 equ 4 ; Divider for SMCLK, (BCSCTL2.2)
		212	DIVS0 equ 2 ; 00=/1, 01=/2, 10=/4, 11=/8 (BCSCTL2.1)
		213	DCOR equ 1 ; DCO Resistor. 0=Intern,1=1xtn (BCSCTL2.0)
		214
		215	;----------------------------------------------------------------------------
		216	; Comparator_A Registers, Byte Access
		217
		218	CACTL1 equ 059h ; Comparator A Control Register 1
		219	CACTL2 equ 05Ah ; Comparator A Control Register 2
		220	CAPD equ 05Bh ; Comparator A Port Disable
		221
		222	;----------------------------------------------------------------------------
		223	; PWM
		224
		225	PWMCTL equ 058h ; Count Value
		226	PWMDTB equ 059h ; Pulse Width (Buffer)
		227	PWMDTR equ 05Ah ; Pulse Width
		228	PWMCNT equ 05Bh ; Control
		229
		230	;----------------------------------------------------------------------------
		231	; USART 0
		232
		233	U0CTL equ 070h
		234	U0TCTL equ 071h
		235	U0RCTL equ 072h
		236	U0MCTL equ 073h
		237	U0BR0 equ 074h
		238	U0BR1 equ 075h
		239	U0RXBUF equ 076h
		240	U0TXBUF equ 077h
		241
		242	;----------------------------------------------------------------------------
		243	; USART 1
		244
		245	U1CTL equ 078h
		246	U1TCTL equ 079h
		247	U1RCTL equ 07Ah
		248	U1MCTL equ 07Bh
		249	U1BR0 equ 07Ch
		250	U1BR1 equ 07Dh
		251	U1RXBUF equ 07Eh
		252	U1TXBUF equ 07Fh
		253
		254	;----------------------------------------------------------------------------
		255	; USART Register Bits
		256
		257	FE equ 128 ; Framing Error (low stop bit) (UxRCTL.7)
		258	PE equ 64 ; Parity Error (PE=0 if PENA=0) (UxRCTL.6)
		259	OE equ 32 ; Overrun Error (Buffer Overrun) (UxRCTL.5)
		260	BRK equ 16 ; Break Detect Flag (UxRCTL.4)
		261	URXEIE equ 8 ; Rec Err Chars Sets URXIFG) (UxRCTL.3)
		262	URXWIE equ 4 ; Rec Wakeup Int Enable (URXIFG) (UxRCTL.2)
		263	RXWAKE equ 2 ; Rec Wakeup Flag (UxRCTL.1)
		264	RXERR equ 1 ; Rec Error Flag (FE,PE,OE,BRK) (UxRCTL.0)
		265
		266	CKPL equ 64 ; Clock Polarity 0=UCLKI=UCLK (UxTCTL.6)
		267	SSEL1 equ 32 ; Source 00=UCLKI, 01=ACLK (UxTCTL.5)
		268	SSEL0 equ 16 ; Source 10=SMCLKI, 11=SMCLK (UxTCTL.4)
		269	URXSE equ 8 ; Receive Start-Edge, 1=Enabled (UxTCTL.3)
		270	TXWAKE equ 4 ; Transmitter Wake, 0=Data,1=Adr (UxTCTL.2)
		271	TXEPT equ 1 ; Transmitter Empty Flag (UxTCTL.0)
		272
		273	PENA equ 128 ; Parity Enable, 1=Enabled (UxCTL.7)
		274	PEV equ 64 ; Parity Select, 1=Even,0=Odd (UxCTL.6)
		275	SPB equ 32 ; Stop Bit, 0=1Stop,1=2Stop (UxCTL.5)
		276	CHAR equ 16 ; Char Length, 0=7Bit,1=8Bit (UxCTL.4)
		277	LISTEN equ 8 ; Listen Enable, 1=Loopback->RX (UxCTL.3)
		278	SYNC equ 4 ; Synch Mode, 0=USART,1=SPI (UxCTL.2)
		279	MM equ 2 ; Multiprocessor, 1=Use_Protocol (UxCTL.1)
		280	SWRST equ 1 ; Software Reset, 1=Held_Reset (UxCTL.0)
		281
		282	;----------------------------------------------------------------------------
		283	; ADC12 Low Bytes
		284
		285	ADC12MCTL0 equ 080h
		286	ADC12MCTL1 equ 081h
		287	ADC12MCTL2 equ 082h
		288	ADC12MCTL3 equ 083h
		289	ADC12MCTL4 equ 084h
		290	ADC12MCTL5 equ 085h
		291	ADC12MCTL6 equ 086h
		292	ADC12MCTL7 equ 087h
		293	ADC12MCTL8 equ 088h
		294	ADC12MCTL9 equ 089h
		295	ADC12MCTL10 equ 08Ah
		296	ADC12MCTL11 equ 08Bh
		297	ADC12MCTL12 equ 08Ch
		298	ADC12MCTL13 equ 08Dh
		299	ADC12MCTL14 equ 08Eh
		300	ADC12MCTL15 equ 08Fh
		301
		302	;----------------------------------------------------------------------------
		303	; LCD Registers
		304
		305	LCDC equ 090h
		306	__TMP set 1 ; Individual Definitions
		307	rept 19
		308	LCDmemory{"\{__TMP}"} equ LCDC+__TMP
		309	__TMP set __TMP+1
		310	endm
		311
		312	;----------------------------------------------------------------------------
		313	; A/D-Wandler, Word Access
		314
		315	AIN equ 0110h ; Input Register
		316	AEN equ 0112h ; Input Enables
		317	ACTL equ 0114h ; Control
		318	ADAT equ 0118h ; Data
		319
		320	;----------------------------------------------------------------------------
		321	; Timer_B Interrupt Vector, Word Access
		322
		323	TBIV equ 011Eh
		324
		325	;----------------------------------------------------------------------------
		326	; Watchdog/Timer, Word Access
		327
		328	WDTCTL equ 0120h
		329	WDTHOLD equ 128 ; Watchdog Timer Hold. 1=Stopped (WDTCTL.6)
		330	WDTNMIES equ 64 ; NMI Edge Select 0=Rise,1=Fall (WDTCTL.6)
		331	WDTNMI equ 32 ; NMI Pin Select, 0=!Reset,1=NMI (WDTCTL.5)
		332	WDTTMSEL equ 16 ; Mode Select 0=Watchdog,1=Timer (WDTCTL.4)
		333	WDTCNTCL equ 8 ; Counter Clear, 1=Clear_Counter (WDTCTL.3)
		334	WDTSSEL equ 4 ; Source Select, 0=SMCLK,1=ACLK (WDTCTL.2)
		335	WDTIS1 equ 2 ; Watchdog Timer Interval Select (WDTCTL.1)
		336	WDTIS0 equ 1 ; 00=32768,01=8192,10=512,11=64 (WDTCTL.0)
		337
		338	;----------------------------------------------------------------------------
		339	; Timer_A Interrupt Vector, Word Access
		340
		341	TAIV equ 012Eh
		342
		343	;----------------------------------------------------------------------------
		344	; Flash Control, Word Access
		345
		346	FCTL1 equ 0128h
		347	FCTL2 equ 012Ah
		348	FCTL3 equ 012Ch
		349
		350	;----------------------------------------------------------------------------
		351	; Hardware Multiplier, Word Access
		352
		353	MPY equ 0130h ; Multiply Unsigned
		354	MPYS equ 0132h ; Multiply Signed
		355	MAC equ 0134h ; MPY+ACC
		356	MACS equ 0136h ; MPYS+ACC
		357	OP2 equ 0138h ; Second Operand
		358	ResLo equ 013Ah ; Result Low Word
		359	ResHi equ 013Ch ; Result High Word
		360	SumExt equ 013Eh ; Sum Extend
		361
		362	;----------------------------------------------------------------------------
		363	; ADC12 High Bytes, Word Access
		364
		365	ADC12MEM0 equ 0140h
		366	ADC12MEM1 equ 0142h
		367	ADC12MEM2 equ 0144h
		368	ADC12MEM3 equ 0146h
		369	ADC12MEM4 equ 0148h
		370	ADC12MEM5 equ 014Ah
		371	ADC12MEM6 equ 014Ch
		372	ADC12MEM7 equ 014Eh
		373	ADC12MEM8 equ 0150h
		374	ADC12MEM9 equ 0152h
		375	ADC12MEM10 equ 0154h
		376	ADC12MEM11 equ 0156h
		377	ADC12MEM12 equ 0158h
		378	ADC12MEM13 equ 015Ah
		379	ADC12MEM14 equ 015Ch
		380	ADC12MEM15 equ 015Eh
		381
		382	;----------------------------------------------------------------------------
		383	; Timer_A Registers, Word Access
		384
		385	TACTL equ 0160h
		386	CCTL0 equ 0162h
		387	CCTL1 equ 0164h
		388	CCTL2 equ 0166h
		389	CCTL3 equ 0168h
		390	CCTL4 equ 016Ah
		391	TAR equ 0170h
		392	CCR0 equ 0172h
		393	CCR1 equ 0174h
		394	CCR2 equ 0176h
		395	CCR3 equ 0178h
		396	CCR4 equ 017Ah
		397
		398	;----------------------------------------------------------------------------
		399	; Timer_B Registers, Word Access
		400
		401	TBCTL equ 0180h
		402	TBCCTL0 equ 0182h
		403	TBCCTL1 equ 0184h
		404	TBCCTL2 equ 0186h
		405	TBCCTL3 equ 0188h
		406	TBCCTL4 equ 018Ah
		407	TBCCTL5 equ 018Ch
		408	TBCCTL6 equ 018Eh
		409	TBR equ 0190h
		410	TBCCR0 equ 0192h
		411	TBCCR1 equ 0194h
		412	TBCCR2 equ 0196h
		413	TBCCR3 equ 0198h
		414	TBCCR4 equ 019Ah
		415	TBCCR5 equ 019Ch
		416	TBCCR6 equ 019Eh
		417
		418	;----------------------------------------------------------------------------
		419	; ADC12 Registers, Byte and Word Access
		420
		421	ADC12CTL0 equ 01A0h
		422	ADC12CTL1 equ 01A2h
		423	ADC12FG equ 01A4h
		424	ADC12IE equ 01A6h
		425
		426	;----------------------------------------------------------------------------
		427
		428	restore ; wieder erlauben
		429
		430	endif ; regmspinc

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(root)/tools/asl/asl-current/include/regmsp.inc @ 1126 – Rev