WebSVN – pentevo – Blame – /tools/asl/asl-current/include/regavrold.inc

Rev	Author	Line No.	Line
1126	savelij	1	ifndef __regavrinc ; avoid multiple inclusion
		2	__regavrinc equ 1
		3
		4	save
		5	listing off ; no listing over this file
		6
		7	;****************************************************************************
		8	;* *
		9	;* AS 1.42 - Datei REGAVROLD.INC *
		10	;* *
		11	;* Contains SFR and Bit Definitions for AVR Processors *
		12	;* OUTDATED VERSION - PLEASE SWITCH TO NEW FILE IF POSSIBLE *
		13	;* *
		14	;****************************************************************************
		15
		16	; Set internal CPU code and memory addresses in one step
		17
		18	switch MOMCPUNAME
		19	case "AT90S1200"
		20	__cpucode equ 0x011200
		21	eeend equ 63 ; End Address EEPROM
		22	iramend equ 95,data ; End Address SRAM
		23	iromend label 1023 ; End Address EPROM
		24	case "AT90S2313"
		25	__cpucode equ 0x012313
		26	eeend equ 127
		27	iramend equ 0xdf,data
		28	iromend label 2047
		29	case "AT90S4414"
		30	__cpucode equ 0x014414
		31	eeend equ 255
		32	iramend equ 0x15f,data
		33	iromend label 4095
		34	case "AT90S8515"
		35	__cpucode equ 0x018515
		36	eeend equ 511
		37	iramend equ 0x25f,data
		38	iromend label 8191
		39	case "ATMEGA8"
		40	__cpucode equ 0x020008
		41	eeend equ 511
		42	iramend equ 0x45f,data
		43	iromend label 8191
		44	case "ATMEGA16"
		45	__cpucode equ 0x020010
		46	eeend equ 511
		47	iramend equ 0x45f,data
		48	iromend label 16383
		49	elsecase
		50	fatal "wrong target selected: only AT90S1200, AT90S2313, AT90S4414, AT90S8515, ATMEGA8, or ATMEGA16 supported"
		51	endcase
		52
		53	ismega function code,(code>>16)=2
		54
		55	if MOMPASS=1
		56	message "Atmel AVR SFR Definitions (C) 1996,2002 Alfred Arnold"
		57	endif
		58
		59	;----------------------------------------------------------------------------
		60	; Constant Memory Addresses
		61
		62	eestart equ 0 ; Start Address Internal EEPROM
		63	iram equ 96,data ; Start Address Internal SRAM
		64	; (behind mapped I/O)
		65	irom label 0 ; Start Address Internal EPROM
		66
		67	;----------------------------------------------------------------------------
		68	; Prozessorkern
		69
		70	sreg port 0x3f ; Status Register:
		71	c equ 0 ; Carry
		72	z equ 1 ; Zero Result
		73	n equ 2 ; Negative Result
		74	v equ 3 ; Twos Complement Overflow
		75	s equ 4 ; Sign
		76	h equ 5 ; Half Carry
		77	t equ 6 ; Bit Storage
		78	i equ 7 ; Globale Interrupt Enable
		79
		80	; Size of stack pointer depends on size of Internal data space
		81	; (if present at all)
		82
		83	if __cpucode>=0x012313
		84	spl equ 0x3d ; Stack Pointer (LSB)
		85	if iramend>=256
		86	sph equ 0x3e ; (MSB)
		87	endif
		88	endif
		89
		90	;----------------------------------------------------------------------------
		91	; Chip Configuration
		92
		93	mcucr port 0x35 ; CPU Control:
		94	isc00 equ 0 ; INT0 Edge Selection
		95	isc01 equ 1 ; INT0 Edge/Level Trigger
		96	if __cpucode>=0x012313
		97	isc10 equ 2 ; INT1 Edge Selection
		98	isc11 equ 3 ; INT1 Edge/Level Trigger
		99	endif
		100	if ismega(__cpucode)
		101	; Note: for the Mega16, bits 6 & 7 are interchanged, I guess that's an
		102	; error in the data sheet...
		103	se equ 7 ; Sleep Enable
		104	sm2 equ 6 ; Sleep Mode Select
		105	sm1 equ 5
		106	sm0 equ 4
		107	else ; !ismega
		108	sm equ 4 ; Select Idle/PowerDdown Mode
		109	se equ 5 ; Enable Sleep Mode
		110	if __cpucode>=0x014414
		111	srw equ 6 ; Wait State Selection External SRAM
		112	sre equ 7 ; External External SRAM
		113	endif
		114	endif
		115
		116	if ismega(__cpucode)
		117	osccal port 0x31 ; Oscillator Calibration
		118
		119	mcucsr port 0x34
		120	if __cpucode>=0x020010
		121	jtd equ 7 ; JTAG Reset Flag
		122	isc2 equ 6 ; Interrupt Sense Control 2
		123	endif
		124	wdrf equ 3 ; Watchdog Reset Occured
		125	borf equ 2 ; Brown Out Occured
		126	extrf equ 1 ; External Reset Occured
		127	porf equ 0 ; Power On Reset Occured
		128
		129	spmcr port 0x37 ; Store Program Memory Control Register
		130	spmie equ 7 ; Interrupt Enable
		131	rwwsb equ 6 ; Read-while-Write Section Busy
		132	rwwsre equ 4 ; Read-while-Write Section Read Enable
		133	blbset equ 3 ; Boot Lock Bit Set
		134	pgwrt equ 2 ; Page Write
		135	pgers equ 1 ; Page Erase
		136	spmen equ 0 ; Store Program Memory Enable
		137	endif
		138
		139	;----------------------------------------------------------------------------
		140	; Interrupt-Steuerung
		141
		142	if ismega(__cpucode)
		143	gicr port 0x3b
		144	ivce equ 0 ; Interrupt Vector Change Enable
		145	ivsel equ 1 ; Interrupt Vector Select
		146	int0 equ 6 ; Enable External Interrupt 0
		147	int1 equ 7 ; Enable External Interrupt 1
		148	if __cpucode>=0x020010
		149	int2 equ 5 ; Enable External Interrupt 2
		150	endif
		151	elseif
		152	gimsk port 0x3b ; Global Interrupt Mask:
		153	int0 equ 6 ; External Interrupt 0
		154	if __cpucode>=0x012313
		155	int1 equ 7 ; External Interrupt 1
		156	endif
		157	endif
		158
		159	if __cpucode>=0x012313
		160	gifr port 0x3a ; Global Interrupt Flags
		161	intf0 equ 6 ; External Interrupt 0
		162	intf1 equ 7 ; External Interrupt 1
		163	ifdef int2
		164	intf2 equ int2 ; External Interrupt 2
		165	endif
		166	endif
		167
		168	; who the heck decided to rearrange all bits for the Megas?
		169
		170	timsk port 0x39 ; Timer Interrupt Mask:
		171	if ismega(__cpucode)
		172	toie0 equ 0
		173	elseif
		174	toie0 equ 1 ; Timer 0 Overflow
		175	endif
		176	if __cpucode>=0x012313
		177	if __cpucode>=0x014414
		178	if ismega(__cpucode)
		179	ocie1b equ 3 ; Timer 1 Vergleich B
		180	elseif
		181	ocie1b equ 5 ; Timer 1 Vergleich B
		182	endif
		183	endif
		184	if ismega(__cpucode)
		185	toie1 equ 2
		186	ticie1 equ 5
		187	toie2 equ 6
		188	ocie2 equ 7
		189	ocie1a equ 4
		190	elseif
		191	toie1 equ 7 ; Timer 1 Overflow
		192	ticie1 equ 3 ; Timer 1 Capture
		193	ocie1a equ 6 ; Timer 1 Compare
		194	endif
		195	endif
		196
		197	tifr port 0x38 ; Timer Interrupt Flags
		198	tov0 equ toie0 ; Timer 0 Overflow
		199	if __cpucode>=0x012313
		200	ocf1a equ ocie1a ; Timer 1 Compare A
		201	tov1 equ toie1 ; Timer 1 Overflow
		202	icf1 equ ticie1 ; Timer 1 Capture
		203	endif
		204	if __cpucode>=0x014414
		205	ocf1b equ ocie1b ; Timer 1 Compare
		206	endif
		207	if ismega(__cpucode)
		208	tov2 equ toie2
		209	ocf2 equ ocie2
		210	endif
		211
		212
		213	;----------------------------------------------------------------------------
		214	; Parallel Ports
		215
		216	if ismega(__cpucode)
		217	sfior equ 0x30
		218	psr10 equ 0 ; T0/T1 Prescaler Reset
		219	psr2 equ 1 ; ditto T2
		220	pud equ 2 ; Pullup Disable
		221	acme equ 3 ; Analog Comparator Multiplexer Enable
		222	adhsm equ 4 ; ADC High Speed Mode
		223	if __cpucode>=0x020010
		224	adts0 equ 5
		225	adts1 equ 6
		226	adts2 equ 7
		227	endif
		228	endif
		229
		230	if (__cpucode=0x014414)\|\|(__cpucode=0x018515)\|\|(__cpucode=0x020010)
		231	porta port 0x1b ; Port A Data Register
		232	ddra port 0x1a ; Port A Data Direction Register
		233	pina port 0x19 ; Port A Read Register
		234	endif
		235
		236	portb port 0x18 ; Port B Data Register
		237	ddrb port 0x17 ; Port B Data Direction Register
		238	pinb port 0x16 ; Port B Read Register
		239
		240	if __cpucode>=0x014414
		241	portc port 0x15 ; Port C Data Register
		242	ddrc port 0x14 ; Port C Data Direction Register
		243	pinc port 0x13 ; Port C Read Register
		244	endif
		245
		246	portd port 0x12 ; Port D Data Register
		247	ddrd port 0x11 ; Port D Data Direction Register
		248	pind port 0x10 ; Port D Read Register
		249
		250	;----------------------------------------------------------------------------
		251	; Timer
		252
		253	tccr0 port 0x33 ; Timer 0 Control Register:
		254	cs00 equ 0 ; Prescaler Setting
		255	cs01 equ 1
		256	cs02 equ 2
		257	if __cpucode=0x020010
		258	wgm01 equ 3 ; Waveform Generation Mode
		259	wgm00 equ 6
		260	com00 equ 4 ; Compare/Match Output Mode
		261	com01 equ 5
		262	foc0 equ 7 ; Force Output Compare
		263	endif
		264
		265	tcnt0 port 0x32 ; Timer 0 Count Register
		266
		267	ocr0 port 0x3c
		268
		269	if __cpucode>=0x012313
		270	tccr1a port 0x2f ; Timer 1 Steuerregister A:
		271	pwm10 equ 0 ; PWM Mode
		272	wgm10 equ pwm10
		273	pwm11 equ 1
		274	wgm11 equ pwm11
		275	com1a0 equ 6 ; Compare Mode A
		276	com1a1 equ 7
		277	if __cpucode>=0x014414
		278	com1b0 equ 4 ; Compare Mode B
		279	com1b1 equ 5
		280	endif
		281	if ismega(__cpucode)
		282	foc1b equ 2
		283	foc1a equ 3
		284	endif
		285
		286	tccr1b port 0x2e ; Timer 1 Control Register B:
		287	cs10 equ 0 ; Prescale setting
		288	cs11 equ 1
		289	cs12 equ 2
		290	ctc1 equ 3 ; Reset after Equality ?
		291	wgm12 equ ctc1
		292	if ismega(__cpucode)
		293	wgm13 equ 4
		294	endif
		295	ices1 equ 6 ; Capture Edge Selection
		296	icnc1 equ 7 ; Capture Noise Filter
		297
		298	tcnt1l port 0x2c ; Timer 1 Count Register (LSB)
		299	tcnt1h port 0x2d ; (MSB)
		300
		301	if __cpucode>=0x014414
		302	ocr1al port 0x2a ; Timer 1 Compare Register A (LSB)
		303	ocr1ah port 0x2b ; (MSB)
		304	ocr1bl port 0x28 ; Timer 1 Compare Register B (LSB)
		305	ocr1bh port 0x29 ; (MSB)
		306	elseif
		307	ocr1l port 0x2a ; Timer 1 Compare Register (LSB)
		308	ocr1h port 0x2b ; (MSB)
		309	endif
		310
		311	if ismega(__cpucode)
		312	icr1l port 0x26
		313	icr1h port 0x27
		314	elseif
		315	icr1l port 0x24 ; Timer 1 Capture Value (LSB)
		316	icr1h port 0x25 ; (MSB)
		317	endif
		318	endif
		319
		320	if ismega(__cpucode)
		321	tccr2 port 0x26 ; Timer 2 Control Register
		322	cs20 equ 0 ; Prescaler
		323	cs21 equ 1
		324	cs22 equ 2
		325	wgm21 equ 3
		326	com20 equ 4
		327	com21 equ 5
		328	wgm20 equ 6
		329	foc2 equ 7
		330
		331	tcnt2 port 0x24 ; Timer Value
		332	ocr2 port 0x23 ; Output Compare Value
		333
		334	assr port 0x22 ; Asynchronous Status Register
		335	as2 equ 3 ; Asynchronous Timer 2
		336	tcn2ub equ 2 ; Timer/Counter 2 Update Busy
		337	ocr2ub equ 1 ; Output Compare Register 2 Update Busy
		338	tcr2ub equ 0 ; Timer/Counter Control Register 2 Update Busy
		339	endif
		340
		341	;----------------------------------------------------------------------------
		342	; Watchdog
		343
		344	wdtcr port 0x21 ; Watchdog-Control Register:
		345	wdp0 equ 0 ; Prescaler
		346	wdp1 equ 1
		347	wdp2 equ 2
		348	wde equ 3 ; Enable
		349	if __cpucode=0x010008
		350	wdce equ 4 ; Watchdog Change Enable
		351	elseif __cpucode>=0x012313
		352	wdttoe equ 4 ; Needed for Disable
		353	endif
		354
		355	;----------------------------------------------------------------------------
		356	; serielle Ports
		357
		358	if __cpucode>=0x012312
		359	udr port 0x0c ; Data Register UART
		360
		361	usr port 0x0b ; Status Register UART:
		362	ucsra port usr
		363	if ismega(__cpucode)
		364	mpcm equ 0 ; Multiprocessor Communication Mode
		365	u2x equ 1 ; Double Speed
		366	pe equ 2 ; Parity Error
		367	endif
		368	or equ 3 ; Receiver Overflow
		369	dor equ or
		370	fe equ 4 ; Framing Error
		371	udre equ 5 ; Data Register Empty
		372	txc equ 6 ; Transmission Complete
		373	rxc equ 7 ; Reception Complete
		374
		375	ucr port 0x0a ; UART Control Register:
		376	ucsrb port ucr
		377	txb8 equ 0 ; Transmit Bit 8
		378	rxb8 equ 1 ; Receive Bit 8
		379	chr9 equ 2 ; Enable 9 Bit Data Values
		380	ucsz2 equ chr9
		381	txen equ 3 ; Transmitter Enable
		382	rxen equ 4 ; Receiver Enable
		383	udrie equ 5 ; Enable Free Data Register Interrupt
		384	txcie equ 6 ; Enable Transmit Complete Interrupt
		385	rxcie equ 7 ; Enable Receive Complete Interrupt
		386
		387	if ismega(__cpucode)
		388	ucsrc port 0x20 ; Control Register C
		389	ursel equ 7 ; Register Select
		390	umsel equ 6 ; Sync/Async Mode
		391	upm1 equ 5 ; Parity Mode
		392	upm0 equ 4
		393	usbs equ 3 ; Stop Bit Select
		394	ucsz1 equ 2 ; Character Size
		395	ucsz0 equ 1
		396	ucpol equ 0 ; Clock Polarity
		397	endif
		398
		399	ubrr port 0x09 ; Baud Rate Generator
		400	if ismega(__cpucode)
		401	ubrrl port ubrr
		402	ubrrh port ucsrc
		403	endif
		404	endif
		405
		406	if __cpucode>=0x014414
		407	spcr port 0x0d ; SPI Control Register:
		408	spr0 equ 0 ; Clock Selection
		409	spr1 equ 1
		410	cpha equ 2 ; Clock Phase
		411	cpol equ 3 ; Clock Polarity
		412	mstr equ 4 ; Master/Slave Select
		413	dord equ 5 ; Bit Order
		414	spe equ 6 ; SPI Enable
		415	spie equ 7 ; SPI Interrupt Enable
		416
		417	spsr port 0x0e ; SPI Status Register:
		418	if ismega(__cpucode)
		419	spi2x equ 0 ; Double Speed Mode
		420	endif
		421	wcol equ 6 ; Write Collision ?
		422	spif equ 7 ; SPI Interrupt Flag
		423
		424	spdr port 0x0f ; SPI Data Register
		425	endif
		426
		427	if ismega(__cpucode)
		428	twbr port 0x00 ; Bit Rate Register
		429
		430	twcr port 0x36 ; Control Register
		431	twint equ 7 ; Interrupt Flag
		432	twea equ 6 ; Enable Acknowledge Bit
		433	twsta equ 5 ; Start Condition
		434	twsto equ 4 ; Stop Condition
		435	twwc equ 3 ; Write Collision Flag
		436	twen equ 2 ; Enable Bit
		437	twie equ 0 ; Interupt Enable
		438
		439	twsr port 0x01 ; Status Register
		440	tws7 equ 7 ; Status
		441	tws6 equ 6
		442	tws5 equ 5
		443	tws4 equ 4
		444	tws3 equ 3
		445	twps1 equ 1 ; Prescaler
		446	twps0 equ 0
		447
		448	twdr port 0x03 ; Data Register
		449
		450	twar port 0x02 ; (Slave) Address Register
		451	twgce equ 0 ; General Call recognition Bit
		452	endif
		453
		454	;----------------------------------------------------------------------------
		455	; Analog Comparator
		456
		457	acsr port 0x08 ; Comparator Control/Status Register:
		458	acis0 equ 0 ; Interrupt Mode
		459	acis1 equ 1
		460	if __cpucode>=0x012313
		461	acic equ 2 ; Use Comparator as Capture Signal for Timer 1
		462	endif
		463	acie equ 3 ; Interrupt Enable
		464	aci equ 4 ; Interrupt Flag
		465	aco equ 5 ; Comparator Output
		466	if ismega(__cpucode)
		467	acbg equ 6 ; Bandgap Select
		468	endif
		469	acd equ 7 ; Power Off
		470
		471	;----------------------------------------------------------------------------
		472	; A/D Converter
		473
		474	if ismega(__cpucode)
		475	admux port 0x07 ; Multiplexer Selection
		476	refs1 equ 7 ; reference Selection Bits
		477	refs0 equ 6
		478	adlar equ 5 ; Left Adjust Right
		479	mux3 equ 3 ; Multiplexer
		480	mux2 equ 2
		481	mux1 equ 1
		482	mux0 equ 0
		483
		484	if __cpucode >=0x020010
		485	adcsra port 0x06 ; Control/Status Register
		486	adate equ 5 ; Auto Trigger Enable
		487	elseif
		488	adcsr port 0x06 ; Control/Status Register
		489	adfr equ 5 ; free Running Select
		490	endif
		491	aden equ 7 ; Enable ADC
		492	adsc equ 6 ; Start Conversion
		493	adif equ 4 ; Interrupt Flag
		494	adie equ 3 ; Interrupt Enable
		495	adps2 equ 2 ; Prescaler Select
		496	adps1 equ 1
		497	adps0 equ 0
		498
		499	adch port 0x05 ; Data Register
		500	adcl port 0x04
		501	endif
		502
		503	;----------------------------------------------------------------------------
		504	; JTAG
		505
		506	if __cpucode >=0x020010
		507	ocdr port osccal ; Debug Register
		508	endif
		509
		510	;----------------------------------------------------------------------------
		511	; EEPROM
		512
		513	if eeend>=256
		514	eearl port 0x1e ; Address Register
		515	eearh port 0x1f
		516	elseif
		517	eear port 0x1e
		518	endif
		519
		520	eedr port 0x1d ; Data Register
		521
		522	eecr port 0x1c ; Control Register:
		523	eere equ 0 ; Read Enable
		524	eewe equ 1 ; Write Enable
		525	if __cpucode>=0x012313
		526	eemwe equ 2
		527	endif
		528	if __cpucode=0x020008
		529	eerie equ 3 ; Enable Ready Interrupt
		530	endif
		531
		532	;----------------------------------------------------------------------------
		533	; Vectors
		534	; Unfortunately, interrupt numbers change for biggger processors
		535	; Why only, Atmel, why ?
		536
		537	vec_reset label 0 ; Reset Entry
		538	switch __cpucode
		539	case 0x011200
		540	vec_int0 label 1 ; Entry External Interrupt 0
		541	vec_tm0ovf label 2 ; Entry Overflow Timer 0
		542	vec_anacomp label 3 ; Entry Analog Comparator
		543	case 0x012313
		544	vec_int0 label 1 ; Entry External Interrupt 0
		545	vec_int1 label 2 ; Entry External Interrupt 2
		546	vec_tm1capt label 3 ; Entry Capture Timer 1
		547	vec_tm1comp label 4 ; Entry Compare Timer 1
		548	vec_tm1ovf label 5 ; Entry Overflow Timer 1
		549	vec_tm0ovf label 6 ; Entry Overflow Timer 0
		550	vec_uartrx label 7 ; Entry UART Empfang komplett
		551	vec_uartudre label 8 ; Entry UART Data Register leer
		552	vec_uarttx label 9 ; Entry UART Sendung komplett
		553	vec_anacomp label 10 ; Entry Analog-Komparator
		554	case 0x014414,0x018515
		555	vec_int0 label 1 ; Entry External Interrupt 0
		556	vec_int1 label 2 ; Entry External Interrupt 2
		557	vec_tm1capt label 3 ; Entry Capture Timer 1
		558	vec_tm1compa label 4 ; Entry Compare A Timer 1
		559	vec_tm1compb label 5 ; Entry Compare A Timer 1
		560	vec_tm1ovf label 6 ; Entry Overflow Timer 1
		561	vec_tm0ovf label 7 ; Entry Overflow Timer 0
		562	vec_spi label 8 ; Entry SPI Interrupt
		563	vec_uartrx label 9 ; Entry UART Reception Complete
		564	vec_uartudre label 10 ; Entry UART Data Register Empty
		565	vec_uarttx label 11 ; Entry UART Sendung Complete
		566	vec_anacomp label 12 ; Entry Analog Comparator
		567	case 0x020008
		568	vec_int0 label 1 ; Entry External Interrupt 0
		569	vec_int1 label 2 ; External Interrupt 1
		570	vec_tm2comp label 3 ; Timer 2 Compare Match
		571	vec_tm2ovf label 4 ; Timer 2 Overflow
		572	vec_tm1capt label 5 ; Timer 1 Capture
		573	vec_tm1compa label 6 ; Timer 1 Compare Match A
		574	vec_tm1compb label 7 ; Timer 1 Compare Match B
		575	vec_tm1ovf label 8 ; Timer 1 Overflow
		576	vec_tm0ovf label 9 ; Timer 0 Overflow
		577	vec_spi label 10 ; SPI Transfer Complete
		578	vec_uartrx label 11 ; UART Rx Complete
		579	vec_uartudre label 12 ; UART Data Register Empty
		580	vec_uarttx label 13 ; UART Tx Complete
		581	vec_adc label 14 ; ADC Conversion Complete
		582	vec_eerdy label 15 ; EEPROM Ready
		583	vec_anacomp label 16 ; analog Comparator
		584	vec_twi label 17 ; Two-Wire Interface
		585	vec_spm_rdy label 18 ; Store Program Memory Ready
		586	case 0x020010
		587	vec_int0 label 2 ; External Interrupt 0
		588	vec_int1 label 4 ; External Interrupt 1
		589	vec_tm2comp label 6 ; Timer 2 Compare Match
		590	vec_tm2ovf label 8 ; Timer 2 Overflow
		591	vec_tm1capt label 10 ; Timer 1 Capture
		592	vec_tm1compa label 12 ; Timer 1 Compare Match A
		593	vec_tm1compb label 14 ; Timer 1 Compare Match B
		594	vec_tm1ovf label 16 ; Timer 1 Overflow
		595	vec_tm0ovf label 18 ; Timer 0 Overflow
		596	vec_spi label 20 ; SPI Transfer Complete
		597	vec_uartrx label 22 ; UART Rx Complete
		598	vec_uartudre label 24 ; UART Data Register Empty
		599	vec_uarttx label 26 ; UART Tx Complete
		600	vec_adc label 28 ; ADC Conversion Complete
		601	vec_eerdy label 30 ; EEPROM Ready
		602	vec_anacomp label 32 ; analog Comparator
		603	vec_twi label 34 ; Two-Wire Interface
		604	vec_int2 label 36 ; External Interrupt 2
		605	vec_tm0comp label 38 ; Timer 0 Compare Match
		606	vec_spm_rdy label 40 ; Store Program Memory Ready
		607	endcase
		608
		609	;----------------------------------------------------------------------------
		610
		611	restore ; re-allow listing
		612
		613	endif ; __regavrinc

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(root)/tools/asl/asl-current/include/regavrold.inc @ 1126 – Rev