WebSVN – pentevo – Blame – /tools/asl/asl-current/include/reg166.inc

Rev	Author	Line No.	Line
1186	savelij	1	ifndef reg166inc ; avoid multiple inclusion
		2	reg166inc equ 1
		3
		4	save
		5	listing off ; no listing over this file
		6
		7	;****************************************************************************
		8	;* *
		9	;* AS 1.42 - Datei REG166.INC *
		10	;* *
		11	;* Contains SFR, Macro and Adress Definitions for 80C166/167 *
		12	;* *
		13	;****************************************************************************
		14
		15	switch MOMCPUNAME
		16	case "80C166"
		17	_n equ 166
		18	case "80C167"
		19	_n equ 167
		20	case "80C167CS"
		21	_n equ 168
		22	elsecase
		23	fatal "wrong target: only 80C166, 80C167, or 80C167CS are supported!"
		24	endcase
		25
		26	if MOMPASS=1
		27	message "80C166/167 SFR Definitions (C) 1994 Alfred Arnold"
		28	message "Extensions for 80C167CS 2003 Marc Reibel"
		29	message "including SFPRs for \{MOMCPUNAME}"
		30	endif
		31
		32	; Make things a bit shorter:
		33
		34	DefIntBits macro BASE,adr,{NoExpand} ; Define Interrupt Register + its Bits
		35	tmpstr166 set "BASE"
		36	{tmpstr166}IC equ adr
		37	{tmpstr166}_GLVL bit {tmpstr166}IC.0 ; Group Priority
		38	{tmpstr166}_ILVL bit {tmpstr166}IC.2 ; Interrupt Priority
		39	{tmpstr166}IE bit {tmpstr166}IC.6 ; Interrupt Enable
		40	{tmpstr166}IR bit {tmpstr166}IC.7 ; Interrupt Flag
		41	endm
		42
		43	;----------------------------------------------------------------------------
		44	; Special Registers:
		45	; Bit Addresses only for bit-addressable registers!
		46	; Only start bit for bit fields!
		47
		48	if _n>=167
		49	SYSCON equ 0ff12h ; System Configuration
		50	XPERSHARE bit SYSCON.0 ; XBUS Peripherals also on External BUS
		51	VISIBLE bit SYSCON.1 ; XBUS Peripherals on Port Pins
		52	XPEN bit SYSCON.2 ; Enable XBUS Peripherals
		53	BDRSTEN bit SYSCON.3 ; Bidirectional /RSTIN
		54	OWDDIS bit SYSCON.4 ; Disable Oscillator Watchdog
		55	CSCFG bit SYSCON.6 ; Chip Select Mode (1=non-latched)
		56	WRCFG bit SYSCON.7 ; /WRL and /WRH instead of /WR and /BHE
		57	CLKEN bit SYSCON.8 ; Emit System Clock on Pin
		58	BYTDIS bit SYSCON.9 ; Block /BHE Pin
		59	ROMENT bit SYSCON.10 ; Enable Internal Rom
		60	SGTDIS bit SYSCON.11 ; Disable Memory Segmentation
		61	ROMS1 bit SYSCON.12 ; Position of Internal ROM
		62
		63
		64	if _n>=168
		65	SYSCON1 equ 0f1dch ; Sleep Mode for IDLE Instruction
		66	; (Bits 1 and 0)
		67	; 00 Normal IDLE Mode
		68	; 01 SLEEP Mode
		69	; 11 SLEEP Mode, RTC and Oscillator off
		70
		71	SYSCON2 equ 0f1d0h ; Clock Generieration
		72	RCS bit SYSCON2.6 ; RTC Clock Source Main Oscillator
		73	SCS bit SYSCON2.7 ; SDD Clock Source Main Oscillator
		74	CLKLOCK bit SYSCON2.15 ; Main Oscillator/PLL stable?
		75
		76	RSTCON equ 0f1e0h ; Reset Control Register
		77
		78	IDCHIP equ 0f07ch ; Chip Identification Register
		79	IDMANUF equ 0f07eh
		80	IDMEM2 equ 0f076h
		81	IDMEM equ 0f07ah
		82	IDPROG equ 0f078h
		83
		84	FOCON equ 0ffaah ; Clock Output Control Register
		85
		86	SYSCON3 equ 0f1d4h ; Peripheral Management
		87	ADCDIS bit SYSCON3.0 ; Disable ADC
		88	ASC0DIS bit SYSCON3.1 ; Disable Asynchronous Serial Port
		89	SSCDIS bit SYSCON3.2 ; Disable Synchronous Serial Port
		90	GPTDIS bit SYSCON3.3 ; Disable GPT Disables
		91	DFMDIS bit SYSCON3.4 ; Disable DFlash (only Variants with Flash)
		92	PFMDIS bit SYSCON3.5 ; Disable PFlash (only Variants with Flash)
		93	CC1DIS bit SYSCON3.6 ; Disable Capcom1
		94	CC2DIS bit SYSCON3.7 ; Disable Capcom2
		95	PWMDIS bit SYSCON3.9 ; Disable PWM
		96	CAN1DIS bit SYSCON3.13 ; Disable CAN1
		97	CAN2DIS bit SYSCON3.14 ; Disable CAN2
		98	PCDDIS bit SYSCON3.15 ; Disable Peripheral Clock Source
		99	endif
		100
		101	elseif
		102	SYSCON equ 0ff0ch
		103	MCTC bit SYSCON.0 ; Memory Cycle Length
		104	RWDC bit SYSCON.4 ; Write/Read Delay
		105	MTTC bit SYSCON.5 ; Tri State Time
		106	BTYP bit SYSCON.6 ; State of EBC-Pins
		107	RDYEN bit SYSCON.12 ; Enable /READY
		108	endif
		109	ROMEN bit SYSCON.10 ; Enable Internal ROM
		110	STKSZ bit SYSCON.13 ; Maximum Size of Stack
		111
		112	if _n>=167
		113	RP0H equ 0f108h ; System Startup Register (Read Only)
		114	CSSEL bit RP0H.1 ; Number of CS Lines
		115	SALSEL bit RP0H.3 ; Number of Address Lines, starting at A16
		116	endif
		117
		118	PSW equ 0ff10h ; Flag Register
		119	N bit PSW.0 ; Negatives Result
		120	C bit PSW.1 ; Carry
		121	V bit PSW.2 ; Overflow
		122	Z bit PSW.3 ; Zero Result
		123	E bit PSW.4 ; End of Table
		124	MULIP bit PSW.5 ; Multiplication/Division interrupted ?
		125	USR0 bit PSW.6 ; User Defined
		126	if _n>=167
		127	HLDEN bit PSW.10 ; Enable Hold
		128	endif
		129	IEN bit PSW.11 ; Enable Interrupts
		130	ILVL bit PSW.12 ; Interrupt Level currently being served
		131
		132	TFR equ 0ffach ; Trap Flag Register
		133	ILLBUS bit TFR.0 ; Externer Bus used, but not configured
		134	ILLINA bit TFR.1 ; Code Access to Odd Address
		135	ILLOPA bit TFR.2 ; Word Access to Odd Address
		136	PRTFLT bit TFR.3 ; Protection Violation
		137	UNDOPC bit TFR.7 ; Undefined Maschine Instruction
		138	STKUF bit TFR.13 ; Stack Underflow
		139	STKOF bit TFR.14 ; Stack Overflow
		140	NMI bit TFR.15 ; Non-Maskable Interrupt
		141	if _n>=167
		142	EXICON equ 0f1c0h ; External Interrupt Controller Control
		143	if _n>=168
		144	EXISEL equ 0f1dah ; External Interrupt Source Register
		145	endif
		146	EXI0ES bit EXICON.0 ; Edge-Triggered Interrupt 0
		147	EXI1ES bit EXICON.2 ; Edge-Triggered Interrupt 1
		148	EXI2ES bit EXICON.4 ; Edge-Triggered Interrupt 2
		149	EXI3ES bit EXICON.6 ; Edge-Triggered Interrupt 3
		150	EXI4ES bit EXICON.8 ; Edge-Triggered Interrupt 4
		151	EXI5ES bit EXICON.10 ; Edge-Triggered Interrupt 5
		152	EXI6ES bit EXICON.12 ; Edge-Triggered Interrupt 6
		153	EXI7ES bit EXICON.14 ; Edge-Triggered Interrupt 7
		154	endif
		155
		156	DPP0 equ 0fe00h ; Paging Register
		157	DPP1 equ 0fe02h
		158	DPP2 equ 0fe04h
		159	DPP3 equ 0fe06h
		160
		161	CSP equ 0fe08h ; Bits 16.. of Program Counter
		162
		163	MDH equ 0fe0ch ; Multiplier/Divider Register
		164	MDL equ 0fe0eh
		165	MDC equ 0ff0eh ; Multiplier/Divider Control
		166	MDRIU bit MDC.4 ; Multiplier in Use
		167
		168	CP equ 0fe10h ; Register Context Pointer
		169
		170	SP equ 0fe12h ; Stack Pointer
		171	STKOV equ 0fe14h ; Upper Bound Stack Pointer
		172	STKUN equ 0fe16h ; Lower Bound Stack Pointer
		173
		174	ZEROS equ 0ff1ch ; Constant All-Zeros
		175	ONES equ 0ff1eh ; Constant All-Ones
		176
		177	;----------------------------------------------------------------------------
		178	; Memory Interface
		179
		180	if _n>=167
		181	ADDRSEL1 equ 0fe18h ; Address Decoder Register 1..4
		182	ADDRSEL2 equ 0fe1ah
		183	ADDRSEL3 equ 0fe1ch
		184	ADDRSEL4 equ 0fe1eh
		185
		186	BUSCON0 equ 0ff0ch ; Bus Configuration Register 0..4
		187	MCTC0 bit BUSCON0.0 ; Memory Cycle Length
		188	RWDC0 bit BUSCON0.4 ; Write/Read Delay
		189	MTTC0 bit BUSCON0.5 ; Tri State Zeit
		190	BTYP0 bit BUSCON0.6 ; State of EBC Pins
		191	ALECTL0 bit BUSCON0.9 ; ALE Extension
		192	BUSACT0 bit BUSCON0.10 ; Bus Active
		193	RDYEN0 bit BUSCON0.12 ; Enable /READY
		194	BUSCON1 equ 0ff14h
		195	MCTC1 bit BUSCON1.0 ; Memory Cycle Length
		196	RWDC1 bit BUSCON1.4 ; Write/Read Delay
		197	MTTC1 bit BUSCON1.5 ; Tri State Zeit
		198	BTYP1 bit BUSCON1.6 ; State of EBC Pins
		199	ALECTL1 bit BUSCON1.9 ; ALE Extension
		200	BUSACT1 bit BUSCON1.10 ; Bus Active
		201	RDYEN1 bit BUSCON1.12 ; Enable /READY
		202	CSREN1 bit BUSCON1.14 ; CS Pins Operating Mode
		203	CSWEN1 bit BUSCON1.15
		204	BUSCON2 equ 0ff16h
		205	MCTC2 bit BUSCON2.0 ; see above
		206	RWDC2 bit BUSCON2.4
		207	MTTC2 bit BUSCON2.5
		208	BTYP2 bit BUSCON2.6
		209	ALECTL2 bit BUSCON2.9
		210	BUSACT2 bit BUSCON2.10
		211	RDYEN2 bit BUSCON2.12
		212	CSREN2 bit BUSCON2.14
		213	CSWEN2 bit BUSCON2.15
		214	BUSCON3 equ 0ff18h
		215	MCTC3 bit BUSCON3.0
		216	RWDC3 bit BUSCON3.4
		217	MTTC3 bit BUSCON3.5
		218	BTYP3 bit BUSCON3.6
		219	ALECTL3 bit BUSCON3.9
		220	BUSACT3 bit BUSCON3.10
		221	RDYEN3 bit BUSCON3.12
		222	CSREN3 bit BUSCON3.14
		223	CSWEN3 bit BUSCON3.15
		224	BUSCON4 equ 0ff1ah
		225	MCTC4 bit BUSCON4.0
		226	RWDC4 bit BUSCON4.4
		227	MTTC4 bit BUSCON4.5
		228	BTYP4 bit BUSCON4.6
		229	ALECTL4 bit BUSCON4.9
		230	BUSACT4 bit BUSCON4.10
		231	RDYEN4 bit BUSCON4.12
		232	CSREN4 bit BUSCON4.14
		233	CSWEN4 bit BUSCON4.15
		234
		235	if _n>=168
		236	XPERCON equ 0f024h ; XPeripherals
		237	XPER0_M equ 0001h ; CAN1 (on after Reset)
		238	XPER1_M equ 0002h ; CAN2 (off after Reset)
		239	XPER10_M equ 0400h ; XRAM 2 KByte (on after Reset)
		240	XPER11_M equ 0800h ; XRAM 6 KByte (off after Reset)!!!
		241	XPER14_M equ 4000h ; 4KByte DFlash (off after Reset)!!!
		242
		243	ISNC equ 0f1deh ; Interrupt Sub Node Control Register
		244	RTCIR bit ISNC.0 ; RTC Interrupt Request Flag
		245	RTCIE bit ISNC.1 ; Enable RTC Interrupt
		246	PLLIR bit ISNC.2 ; PLL Interrupt Request Flag
		247	PLLIE bit ISNC.3 ; Enable PLL Interrupt
		248	endif
		249
		250	DefIntBits XP0,0f186h ; Interrupt Control Peripheral Device 0
		251	DefIntBits XP1,0f18eh ; Interrupt Control Peripheral Device 1
		252	DefIntBits XP2,0f196h ; Interrupt Control Peripheral Device 2
		253	; Flash Termination (Flash Variants)
		254	DefIntBits XP3,0f19eh ; Interrupt Control Peripheral Device 3
		255	endif
		256
		257	;----------------------------------------------------------------------------
		258	; Ports:
		259
		260	if _n>=167
		261	PICON equ 0f1c4h
		262	endif
		263
		264	if _n>=167
		265	P0L equ 0ff00h ; Port 0 Data Register
		266	P0H equ 0ff02h
		267	DP0L equ 0f100h ; Port 0 Data Direction Register
		268	DP0H equ 0f102h
		269	if _n>=168
		270	POCON0H equ 0f082h
		271	POCON0L equ 0f080h
		272	endif
		273	elseif
		274	P0 equ 0ff00h
		275	DP0 equ 0ff02h
		276	endif
		277
		278	if _n>=167
		279	P1L equ 0ff04h ; Port 1 Data Register
		280	P1H equ 0ff06h
		281	DP1L equ 0f104h ; Port 1 Data Direction Register
		282	DP1H equ 0f106h
		283	if _n>=168
		284	P1DIDIS equ 0fea4h ; Port 1 Disable Digital-Input
		285	endif
		286	if _n>=168
		287	POCON1H equ 0f086h ; Port 1 Output Drivers
		288	POCON1L equ 0f084h
		289	endif
		290	elseif
		291	P1 equ 0ff04h
		292	DP1 equ 0ff06h
		293	endif
		294
		295	P2 equ 0ffc0h ; Port 2 Data Register
		296	DP2 equ 0ffc2h ; Port 2 Data Direction Register
		297	if _n>=167
		298	ODP2 equ 0f1c2h ; Port 2 Open Drain Setting
		299	P2LIN bit PICON.0 ; Port 2 Input Threshold Bits 0..7
		300	P2HIN bit PICON.1 ; Port 2 Input Threshold Bits 8..15
		301	if _n>=168
		302	POCON20 equ 0f0aah ; Port 2 Dedicated Pin Control Register
		303	; /RSTOUT,CLKOUT/FOUT,ALE,
		304	; /WH,/RD,/BHE,/WH
		305	POCON2 equ 0f088h ; Port 2 Output Drivers
		306	endif
		307	endif
		308
		309	P3 equ 0ffc4h ; Port 3 Data Register
		310	DP3 equ 0ffc6h ; Port 3 Data Direction Register
		311	if _n>=167
		312	ODP3 equ 0f1c6h ; Port 3 Open Drain Setting
		313	P3LIN bit PICON.2 ; Port 3 Input Threshold Bits 0..7
		314	P3HIN bit PICON.3 ; Port 3 Input Threshold Bits 8..15
		315	if _n>=168
		316	POCON3 equ 0f08ah ; Port 3 Output Drivers
		317	endif
		318	endif
		319
		320	if _n>=167
		321	P4 equ 0ffc8h ; Port 4 Data Register
		322	DP4 equ 0ffcah ; Port 4 Data Direction Register
		323	ODP4 equ 0f1cah ; Port 4 Open Drain Setting
		324	P4LIN bit PICON.4 ; Port 4 Input Threshold
		325	if _n>=168
		326	POCON4 equ 0f08ch ; Port 4 Output Drivers
		327	endif
		328	elseif
		329	P4 equ 0ff08h
		330	DP4 equ 0ff0ah
		331	endif
		332
		333	P5 equ 0ffa2h ; Port 5 Data Register (input-only)
		334
		335	if _n>=167
		336	P5DIDIS equ 0ffa4h
		337	endif
		338
		339	if _n>=167
		340	P6 equ 0ffcch ; Port 6 Data Register
		341	DP6 equ 0ffceh ; Port 6 Data Direction Register
		342	ODP6 equ 0f1ceh ; Port 6 Open Drain Setting
		343	P6LIN bit PICON.5 ; Port 6 Input Threshold
		344	if _n>=168
		345	POCON6 equ 0f08eh ; Port 6 Output Drivers
		346	endif
		347	P7 equ 0ffd0h ; Port 7 Data Register
		348	DP7 equ 0ffd2h ; Port 7 Data Direction Register
		349	ODP7 equ 0f1d2h ; Port 7 Open Drain Setting
		350	P7LIN bit PICON.6 ; Port 7 Input Threshold
		351	if _n>=168
		352	POCON7 equ 0f090h ; Port 7 Output Drivers
		353	endif
		354	P8 equ 0ffd4h ; Port 8 Data Register
		355	DP8 equ 0ffd6h ; Port 8 Data Direction Register
		356	ODP8 equ 0f1d6h ; Port 8 Open Drain Setting
		357	P8LIN bit PICON.7 ; Port 8 Input Threshold
		358	if _n>=168
		359	POCON8 equ 0f092h ; Port 8 Output Drivers
		360	endif
		361	endif
		362
		363	;----------------------------------------------------------------------------
		364	; Timers:
		365
		366	T0 equ 0fe50h ; CAPCOM Timer 0
		367	T0REL equ 0fe54h ; Timer 0 Reload Register
		368	T01CON equ 0ff50h ; Timer 0+1 Control Register
		369	T0I bit T01CON.0 ; Timer 0 Input Selection
		370	T0M bit T01CON.3 ; Timer 0 Mode
		371	T0R bit T01CON.6 ; Timer 0 Start/Stop
		372	T1I bit T01CON.8 ; Timer 1 Input Selection
		373	T1M bit T01CON.11 ; Timer 1 Mode
		374	T1R bit T01CON.14 ; Timer 1 Start/Stop
		375	DefIntBits T0,0ff9ch ; Timer 0 Interrupt Control
		376
		377	T1 equ 0fe52h ; CAPCOM Timer 1
		378	T1REL equ 0fe56h ; Timer 1 Reload Register
		379	DefIntBits T1,0ff9eh ; Timer 1 Interrupt Control
		380
		381	T2 equ 0fe40h ; Timer 2
		382	T2CON equ 0ff40h ; Timer 2 Control Register
		383	T2I bit T2CON.0 ; Timer 2 Input Selection
		384	T2M bit T2CON.3 ; Timer 2 Mode
		385	T2R bit T2CON.6 ; Timer 2 Start/Stop
		386	T2UD bit T2CON.7 ; Timer 2 Direction
		387	if _n>=167
		388	T2UDE bit T2CON.8 ; Timer 2 External Count Direction Selection
		389	endif
		390	DefIntBits T2,0ff60h ; Timer 2 Interrupt Control
		391
		392	T3 equ 0fe42h ; Timer 3
		393	T3CON equ 0ff42h ; Timer 3 Control Register
		394	T3I bit T3CON.0 ; Timer 3 Input Selection
		395	T3M bit T3CON.3 ; Timer 3 Mode
		396	T3R bit T3CON.6 ; Timer 3 Start/Stop
		397	T3UD bit T3CON.7 ; Timer 3 Direction
		398	T3UDE bit T3CON.8 ; Timer 3 External Count Direction Selection
		399	T3OE bit T3CON.9 ; Timer 3 Enable Output
		400	T3OTL bit T3CON.10 ; Timer 3 Overflow
		401	DefIntBits T3,0ff62h ; Timer 3 Interrupt Control
		402
		403	T4 equ 0fe44h ; Timer 4
		404	T4CON equ 0ff44h ; Timer 4 Control Register
		405	T4I bit T4CON.0 ; Timer 4 Eingangssignal
		406	T4M bit T4CON.3 ; Timer 4 Mode
		407	T4R bit T4CON.6 ; Timer 4 Start/Stop
		408	T4UD bit T4CON.7 ; Timer 4 Direction
		409	if _n>=167
		410	T4UDE bit T4CON.8 ; Timer 4 External Count Direction Selection
		411	endif
		412	DefIntBits T4,0ff64h ; Timer 4 Interrupt Control
		413
		414	T5 equ 0fe46h ; Timer 5
		415	T5CON equ 0ff46h ; Timer 5 Control Register
		416	T5I bit T5CON.0 ; Timer 5 Input Selection
		417	T5M bit T5CON.3 ; Timer 5 Mode
		418	T5R bit T5CON.6 ; Timer 5 Start/Stop
		419	T5UD bit T5CON.7 ; Timer 5 Direction
		420	if _n>=167
		421	T5UDE bit T5CON.8 ; Timer 5 External Count Direction Selection
		422	endif
		423	CI bit T5CON.12 ; CAPREL Input Selection
		424	T5CLR bit T5CON.14 ; Timer 5 Clear upon Capture
		425	T5SC bit T5CON.15 ; Timer 5 Capture Enable
		426	DefIntBits T5,0ff66h ; Timer 5 Interrupt Control
		427
		428	T6 equ 0fe48h ; Timer 6
		429	T6CON equ 0ff48h ; Control Register Timer 6
		430	T6I bit T6CON.0 ; Timer 6 Input Selection
		431	if _n>=167
		432	T6M bit T6CON.3 ; Timer 6 Mode
		433	endif
		434	T6R bit T6CON.6 ; Timer 6 Start/Stop
		435	T6UD bit T6CON.7 ; Timer 6 Count Direction
		436	if _n>=167
		437	T6UDE bit T6CON.8 ; Timer 6 External Count Direction Selection
		438	endif
		439	T6OE bit T6CON.9 ; Timer 6 Enable Output
		440	T6OTL bit T6CON.10 ; Timer 6 Overflow
		441	T6SR bit T6CON.15 ; Timer 6 Reload
		442	DefIntBits T6,0ff68h ; Timer 6 Interrupt Control
		443
		444	if _n>=167
		445	T78CON equ 0ff20h ; Timer 7+8 Control Register
		446
		447	T7 equ 0f050h ; Timer 7
		448	T7REL equ 0f054h ; Timer 7 Reload Register
		449	T7M bit T78CON.3 ; Timer 7 Timer/Counter Mode
		450	DefIntBits T7,0f17ah ; Timer 7 Interrupt Control
		451
		452	T8 equ 0f052h ; CAPCOM Timer 8
		453	T8REL equ 0f056h ; Timer 8 Reload Register
		454	T8M bit T78CON.11 ; Timer 8 Timer/Counter Mode
		455	DefIntBits T8,0f17ch ; Timer 8 Interrupt Control
		456	if _n>=168
		457	T14 equ 0f0d2h ; RTC Timer 14
		458	T14REL equ 0f0d0h ; RTC Timer 14 Reload Register
		459	RTCL equ 0f0d4h ; RTC Low Word
		460	RTCH equ 0f0d6h ; RTC High Word
		461	endif
		462	endif
		463
		464	;-----------------------------------------------------------------------
		465	; Capture/Compare Unit:
		466
		467	CAPREL equ 0fe4ah ; Capture/Reload Register
		468	CC0 equ 0fe80h ; CAPCOM Registers
		469	CC1 equ 0fe82h
		470	CC2 equ 0fe84h
		471	CC3 equ 0fe86h
		472	CC4 equ 0fe88h
		473	CC5 equ 0fe8ah
		474	CC6 equ 0fe8ch
		475	CC7 equ 0fe8eh
		476	CC8 equ 0fe90h
		477	CC9 equ 0fe92h
		478	CC10 equ 0fe94h
		479	CC11 equ 0fe96h
		480	CC12 equ 0fe98h
		481	CC13 equ 0fe9ah
		482	CC14 equ 0fe9ch
		483	CC15 equ 0fe9eh
		484	if _n>=167
		485	CC16 equ 0fe60h ; Further CAPCOM Registers
		486	CC17 equ 0fe62h
		487	CC18 equ 0fe64h
		488	CC19 equ 0fe66h
		489	CC20 equ 0fe68h
		490	CC21 equ 0fe6ah
		491	CC22 equ 0fe6ch
		492	CC23 equ 0fe6eh
		493	CC24 equ 0fe70h
		494	CC25 equ 0fe72h
		495	CC26 equ 0fe74h
		496	CC27 equ 0fe76h
		497	CC28 equ 0fe78h
		498	CC29 equ 0fe7ah
		499	CC30 equ 0fe7ch
		500	CC31 equ 0fe7eh
		501	endif
		502
		503	CCM0 equ 0ff52h ; CAPCOM Mode Register
		504	CCMOD0 bit CCM0.0 ; CC0 Mode Selection
		505	ACC0 bit CCM0.3 ; CC0 assigned to Timer 0/1
		506	CCMOD1 bit CCM0.4 ; CC1 Mode Selection
		507	ACC1 bit CCM0.7 ; CC1 assigned to Timer 0/1
		508	CCMOD2 bit CCM0.8 ; CC2 Mode Selection
		509	ACC2 bit CCM0.11 ; CC2 assigned to Timer 0/1
		510	CCMOD3 bit CCM0.12 ; CC3 Mode Selection
		511	ACC3 bit CCM0.15 ; CC3 assigned to Timer 0/1
		512
		513	CCM1 equ 0ff54h
		514	CCMOD4 bit CCM1.0 ; CC4 Mode Selection
		515	ACC4 bit CCM1.3 ; CC4 assigned to Timer 0/1
		516	CCMOD5 bit CCM1.4 ; CC5 Mode Selection
		517	ACC5 bit CCM1.7 ; CC5 assigned to Timer 0/1
		518	CCMOD6 bit CCM1.8 ; CC6 Mode Selection
		519	ACC6 bit CCM1.11 ; CC6 assigned to Timer 0/1
		520	CCMOD7 bit CCM1.12 ; CC7 Mode Selection
		521	ACC7 bit CCM1.15 ; CC7 assigned to Timer 0/1
		522
		523	CCM2 equ 0ff56h
		524	CCMOD8 bit CCM2.0 ; CC8 Mode Selection
		525	ACC8 bit CCM2.3 ; CC8 assigned to Timer 0/1
		526	CCMOD9 bit CCM2.4 ; CC9 Mode Selection
		527	ACC9 bit CCM2.7 ; CC9 assigned to Timer 0/1
		528	CCMOD10 bit CCM2.8 ; CC10 Mode Selection
		529	ACC10 bit CCM2.11 ; CC10 assigned to Timer 0/1
		530	CCMOD11 bit CCM2.12 ; CC11 Mode Selection
		531	ACC11 bit CCM2.15 ; CC11 assigned to Timer 0/1
		532
		533	CCM3 equ 0ff58h
		534	CCMOD12 bit CCM3.0 ; CC12 Mode Selection
		535	ACC12 bit CCM3.3 ; CC12 assigned to Timer 0/1
		536	CCMOD13 bit CCM3.4 ; CC13 Mode Selection
		537	ACC13 bit CCM3.7 ; CC13 assigned to Timer 0/1
		538	CCMOD14 bit CCM3.8 ; CC14 Mode Selection
		539	ACC14 bit CCM3.11 ; CC14 assigned to Timer 0/1
		540	CCMOD15 bit CCM3.12 ; CC15 Mode Selection
		541	ACC15 bit CCM3.15 ; CC15 assigned to Timer 0/1
		542
		543	CCM4 equ 0ff22h
		544	CCMOD16 bit CCM4.0 ; CC16 Mode Selection
		545	ACC16 bit CCM4.3 ; CC16 assigned to Timer 0/1
		546	CCMOD17 bit CCM4.4 ; CC17 Mode Selection
		547	ACC17 bit CCM4.7 ; CC17 assigned to Timer 0/1
		548	CCMOD18 bit CCM4.8 ; CC18 Mode Selection
		549	ACC18 bit CCM4.11 ; CC18 assigned to Timer 0/1
		550	CCMOD19 bit CCM4.12 ; CC19 Mode Selection
		551	ACC19 bit CCM4.15 ; CC19 assigned to Timer 0/1
		552
		553	CCM5 equ 0ff24h
		554	CCMOD20 bit CCM5.0 ; CC20 Mode Selection
		555	ACC20 bit CCM5.3 ; CC20 assigned to Timer 0/1
		556	CCMOD21 bit CCM5.4 ; CC21 Mode Selection
		557	ACC21 bit CCM5.7 ; CC21 assigned to Timer 0/1
		558	CCMOD22 bit CCM5.8 ; CC22 Mode Selection
		559	ACC22 bit CCM5.11 ; CC22 assigned to Timer 0/1
		560	CCMOD23 bit CCM5.12 ; CC23 Mode Selection
		561	ACC23 bit CCM5.15 ; CC23 assigned to Timer 0/1
		562
		563	CCM6 equ 0ff26h
		564	CCMOD24 bit CCM6.0 ; CC24 Mode Selection
		565	ACC24 bit CCM6.3 ; CC24 assigned to Timer 0/1
		566	CCMOD25 bit CCM6.4 ; CC25 Mode Selection
		567	ACC25 bit CCM6.7 ; CC25 assigned to Timer 0/1
		568	CCMOD26 bit CCM6.8 ; CC26 Mode Selection
		569	ACC26 bit CCM6.11 ; CC26 assigned to Timer 0/1
		570	CCMOD27 bit CCM6.12 ; CC27 Mode Selection
		571	ACC27 bit CCM6.15 ; CC27 assigned to Timer 0/1
		572
		573	CCM7 equ 0ff28h
		574	CCMOD28 bit CCM7.0 ; CC28 Mode Selection
		575	ACC28 bit CCM7.3 ; CC28 assigned to Timer 0/1
		576	CCMOD29 bit CCM7.4 ; CC29 Mode Selection
		577	ACC29 bit CCM7.7 ; CC29 assigned to Timer 0/1
		578	CCMOD30 bit CCM7.8 ; CC30 Mode Selection
		579	ACC30 bit CCM7.11 ; CC30 assigned to Timer 0/1
		580	CCMOD31 bit CCM7.12 ; CC31 Mode Selection
		581	ACC31 bit CCM7.15 ; CC31 assigned to Timer 0/1
		582
		583	DefIntBits CR,0ff6ah ; CAPREL Interrupt Control Register
		584
		585	DefIntBits CC0,0ff78h ; Interrupt Control CAPCOM Channels
		586	DefIntBits CC1,0ff7ah
		587	DefIntBits CC2,0ff7ch
		588	DefIntBits CC3,0ff7eh
		589	DefIntBits CC4,0ff80h
		590	DefIntBits CC5,0ff82h
		591	DefIntBits CC6,0ff84h
		592	DefIntBits CC7,0ff86h
		593	DefIntBits CC8,0ff88h
		594	DefIntBits CC9,0ff8ah
		595	DefIntBits CC10,0ff8ch
		596	DefIntBits CC11,0ff8eh
		597	DefIntBits CC12,0ff90h
		598	DefIntBits CC13,0ff92h
		599	DefIntBits CC14,0ff94h
		600	DefIntBits CC15,0ff96h
		601	if _n>=167
		602	DefIntBits CC16,0f160h ; Interrupt Control futher CAPCOM Channels
		603	DefIntBits CC17,0f162h
		604	DefIntBits CC18,0f164h
		605	DefIntBits CC19,0f166h
		606	DefIntBits CC20,0f168h
		607	DefIntBits CC21,0f16ah
		608	DefIntBits CC22,0f16ch
		609	DefIntBits CC23,0f16eh
		610	DefIntBits CC24,0f170h
		611	DefIntBits CC25,0f172h
		612	DefIntBits CC26,0f174h
		613	DefIntBits CC27,0f176h
		614	DefIntBits CC28,0f178h
		615	DefIntBits CC29,0f184h
		616	DefIntBits CC30,0f18ch
		617	DefIntBits CC31,0f194h
		618	endif
		619
		620	PECC0 equ 0fec0h ; PEC Channel Control Register
		621	PECC1 equ 0fec2h
		622	PECC2 equ 0fec4h
		623	PECC3 equ 0fec6h
		624	PECC4 equ 0fec8h
		625	PECC5 equ 0fecah
		626	PECC6 equ 0fecch
		627	PECC7 equ 0feceh
		628
		629	SRCP0 equ 0fce0h ; PEC Source Register
		630	SRCP1 equ 0fce4h
		631	SRCP2 equ 0fce8h
		632	SRCP3 equ 0fcech
		633	SRCP4 equ 0fcf0h
		634	SRCP5 equ 0fcf4h
		635	SRCP6 equ 0fcf8h
		636	SRCP7 equ 0fcfch
		637	DSTP0 equ 0fce2h ; PEC Destination Register
		638	DSTP1 equ 0fce6h
		639	DSTP2 equ 0fceah
		640	DSTP3 equ 0fceeh
		641	DSTP4 equ 0fcf2h
		642	DSTP5 equ 0fcf6h
		643	DSTP6 equ 0fcfah
		644	DSTP7 equ 0fcfeh
		645
		646	;----------------------------------------------------------------------------
		647	; Pulse Width Modulator:
		648
		649	if _n>=167
		650	PP0 equ 0f038h ; PWM Period 0
		651	PT0 equ 0f030h ; PWM Counter 0
		652	PW0 equ 0fe30h ; PWM Pulse Width 0
		653	PP1 equ 0f03ah ; PWM Period 1
		654	PT1 equ 0f032h ; PWM Counter 1
		655	PW1 equ 0fe30h ; PWM Pulse Width 1
		656	PP2 equ 0f03ch ; PWM Period 2
		657	PT2 equ 0f034h ; PWM Counter 2
		658	PW2 equ 0fe30h ; PWM Pulse Width 2
		659	PP3 equ 0f03eh ; PWM Period 3
		660	PT3 equ 0f036h ; PWM Counter 3
		661	PW3 equ 0fe30h ; PWM Pulse Width 3
		662	PWMCON0 equ 0ff30h ; PWM Control Register 0
		663	PTR0 bit PWMCON0.0 ; PT0 Run
		664	PTR1 bit PWMCON0.1 ; PT1 Run
		665	PTR2 bit PWMCON0.2 ; PT2 Run
		666	PTR3 bit PWMCON0.3 ; PT3 Run
		667	PTI0 bit PWMCON0.4 ; PT0 Input Selection
		668	PTI1 bit PWMCON0.5 ; PT1 Input Selection
		669	PTI2 bit PWMCON0.6 ; PT2 Input Selection
		670	PTI3 bit PWMCON0.7 ; PT3 Input Selection
		671	PIE0 bit PWMCON0.8 ; PT0 Enable Interrups
		672	PIE1 bit PWMCON0.9 ; PT1 Enable Interrups
		673	PIE2 bit PWMCON0.10 ; PT2 Enable Interrups
		674	PIE3 bit PWMCON0.11 ; PT3 Enable Interrups
		675	PIR0 bit PWMCON0.12 ; PT0 Interrupt Flag
		676	PIR1 bit PWMCON0.13 ; PT1 Interrupt Flag
		677	PIR2 bit PWMCON0.14 ; PT2 Interrupt Flag
		678	PIR3 bit PWMCON0.15 ; PT3 Interrupt Flag
		679	PWMCON1 equ 0ff32h ; PWM Control Register 1
		680	PEN0 bit PWMCON1.0 ; PT0 Enable Output
		681	PEN1 bit PWMCON1.1 ; PT1 Enable Output
		682	PEN2 bit PWMCON1.2 ; PT2 Enable Output
		683	PEN3 bit PWMCON1.3 ; PT3 Enable Output
		684	PM0 bit PWMCON1.4 ; PT0 Mode
		685	PM1 bit PWMCON1.5 ; PT1 Mode
		686	PM2 bit PWMCON1.6 ; PT2 Mode
		687	PM3 bit PWMCON1.7 ; PT3 Mode
		688	PB01 bit PWMCON1.12 ; PT0&1 Burst Mode
		689	PS2 bit PWMCON1.14 ; PT2 Single Shot Mode
		690	PS3 bit PWMCON1.15 ; PT3 Single Shot Mode
		691	DefIntBits PWM,0f17eh ; PWM Interrupt Control
		692	endif
		693
		694	;----------------------------------------------------------------------------
		695	; A/D-Converter:
		696
		697	ADDAT equ 0fea0h ; A/D-Converter Ergebnis
		698	if _n>=167
		699	ADDAT2 equ 0f0a0h ; A/D-Converter Ergebnis 2
		700	endif
		701	DefIntBits ADC,0ff98h ; A/D-Converter Interrupt Control for End of Conversion
		702	DefIntBits ADE,0ff9ah ; A/D-Converter Interrupt Control for Errors
		703	ADCON equ 0ffa0h ; A/D-Converter Control Register
		704	ADCH bit ADCON.0 ; A/D-Converter Channel Selection
		705	ADM bit ADCON.4 ; A/D-Converter Mode
		706	ADST bit ADCON.7 ; Start A/D Conversion
		707	ADBSY bit ADCON.8 ; A/D-Converter Busy
		708	if _n>=167
		709	ADWR bit ADCON.9 ; do not restart A/D-Converter before being read
		710	ADCIN bit ADCON.10 ; A/D-Converter Channel Injection (??...)
		711	ADCRQ bit ADCON.11 ; A/D-Converter Channel Injection Requested
		712	endif
		713
		714	;----------------------------------------------------------------------------
		715	; Watchdog:
		716
		717	WDT equ 0feaeh ; Watchdog Counter
		718	WDTCON equ 0ffaeh ; Watchdog Control Register
		719	WDTIN bit WDTCON.0 ; Watchdog Input frequency
		720	WDTR bit WDTCON.1 ; Reset by Watchdog
		721	if _n>=167
		722	SWR bit WDTCON.2 ; Software Reset
		723	SHWR bit WDTCON.3 ; Short Hardware-Reset
		724	LHWR bit WDTCON.4 ; Long Hardware-Reset
		725	PONR bit WDTCON.5 ; Power On Reset (Flash Variants)
		726	endif
		727	WDTREL bit WDTCON.8 ; Reload Value Watchdog
		728
		729	;----------------------------------------------------------------------------
		730	; Serielles:
		731
		732	S0TBUF equ 0feb0h ; SIO0 Transmit Register
		733	S0RBUF equ 0feb2h ; SIO0 Receive Register
		734	S0BG equ 0feb4h ; SIO0 Baud Rate Selection
		735	DefIntBits S0T,0ff6ch ; SIO0 Interrupt Control Transmitter
		736	DefIntBits S0R,0ff6eh ; SIO0 Interrupt Control Receiver
		737	DefIntBits S0E,0ff70h ; SIO0 Interrupt Control Errors
		738
		739	if _n>=167
		740	DefIntBits S0TB,0f19ch ; Interrupt Control Transmit Buffer
		741	endif
		742
		743	S0CON equ 0ffb0h ; SIO0 Control Register
		744	S0M bit S0CON.0 ; SIO0 Mode
		745	S0STP bit S0CON.3 ; SIO0 Number of Stopbits
		746	S0REN bit S0CON.4 ; SIO0 Enable Receiver
		747	S0PEN bit S0CON.5 ; SIO0 Enable Parity
		748	S0FEN bit S0CON.6 ; SIO0 Enable Frame Check
		749	S0OEN bit S0CON.7 ; SIO0 Enable Overflow Check
		750	S0PE bit S0CON.8 ; SIO0 Parity Error
		751	S0FE bit S0CON.9 ; SIO0 Framing Error
		752	S0OE bit S0CON.10 ; SIO0 Overflow
		753	if _n>=167
		754	S0ODD bit S0CON.12 ; SIO0 Odd Parity
		755	S0BRS bit S0CON.13 ; SIO0 Baud Rate Factor
		756	endif
		757	S0LB bit S0CON.14 ; SIO0 Loopback
		758	S0R bit S0CON.15 ; SIO0 Enable Baud Rate Generator
		759
		760	if _n>=167
		761	SSCTB equ 0f0b0h ; SSC Transmit Register
		762	SSCRB equ 0f0b2h ; SSC Receive Register
		763	SSCBR equ 0f0b4h ; SSC Baud Rate Selection
		764	DefIntBits SSCT,0ff72h ; SSC Interrupt Control Transmitter
		765	DefIntBits SSCR,0ff74h ; SSC Interrupt Control Receiver
		766	DefIntBits SSCE,0ff76h ; SSC Interrupt Control Errors
		767	SSCCON equ 0ffb2h ; SSC Control Register
		768	SSCBM bit SSCCON.0 ; Word Width
		769	SSCBC bit SSCCON.0 ; Number of Bits
		770	SSCHB bit SSCCON.4 ; Start Bit Control
		771	SSCPH bit SSCCON.5 ; Clock Phase
		772	SSCP0 bit SSCCON.6 ; Clock Polarity
		773	SSCTEN bit SSCCON.8 ; Enable Transmit Errors
		774	SSCTE bit SSCCON.8 ; Transmit Error Flag
		775	SSCREN bit SSCCON.9 ; Enable Receive Errors
		776	SSCRE bit SSCCON.9 ; Receive Errot Flag
		777	SSCPEN bit SSCCON.10 ; Enable Phase Errors
		778	SSCPE bit SSCCON.10 ; Phase Error Flag
		779	SSCBEN bit SSCCON.11 ; Enable Baud Rate Errors
		780	SSCBE bit SSCCON.11 ; Baud Rate Errors Flag
		781	SSCBSY bit SSCCON.12 ; SSC Busy
		782	SSCMS bit SSCCON.14 ; SSC Operate as Master
		783	SSCEN bit SSCCON.15 ; SSC Enable
		784	elseif
		785	S1TBUF equ 0feb8h ; SIO1 Transmit Register
		786	S1RBUF equ 0febah ; SIO1 Receive Register
		787	S1BG equ 0febch ; SIO1 Baud Rate Selection
		788	DefIntBits S1T,0ff72h ; SIO1 Interrupt Control Transmitter
		789	DefIntBits S1R,0ff74h ; SIO1 Interrupt Control Receiver
		790	DefIntBits S1E,0ff76h ; SIO1 Interrupt Control Errors
		791	S1CON equ 0ffb8h ; SIO1 Control Register
		792	S1M bit S1CON.0 ; SIO1 Mode
		793	S1STP bit S1CON.3 ; SIO1 Number of Stopbits
		794	S1REN bit S1CON.4 ; SIO1 Enable Receiver
		795	S1PEN bit S1CON.5 ; SIO1 Enable Parity
		796	S1FEN bit S1CON.6 ; SIO1 Enable Frame Check
		797	S1OEN bit S1CON.7 ; SIO1 Enable Overflow Check
		798	S1PE bit S1CON.8 ; SIO1 Parity Error
		799	S1FE bit S1CON.9 ; SIO1 Framing Error
		800	S1OE bit S1CON.10 ; SIO1 Overflow
		801	S1LB bit S1CON.14 ; SIO1 Loopback
		802	S1R bit S1CON.15 ; SIO1 Enable Baud Rate Generator
		803	endif
		804
		805	;----------------------------------------------------------------------------
		806	; Canbus 1 und 2
		807
		808	if _n>=167
		809
		810	;bitram; DefIntBits C1, 0ef02h ; CAN1 Interrupt Control Register
		811	C1BTR equ 0ef04h ; CAN1 Bit Timing Register
		812	C1CSR equ 0ef00h ; CAN1 Control/Status Register
		813	C1GMS equ 0ef06h ; CAN1 Global Mask Short
		814	C1LAR1 equ 0ef14h ; CAN1 Lower Arbitration Register
		815	C1LAR2 equ 0ef24h
		816	C1LAR3 equ 0ef34h
		817	C1LAR4 equ 0ef44h
		818	C1LAR5 equ 0ef54h
		819	C1LAR6 equ 0ef64h
		820	C1LAR7 equ 0ef74h
		821	C1LAR8 equ 0ef84h
		822	C1LAR9 equ 0ef94h
		823	C1LAR10 equ 0efa4h
		824	C1LAR11 equ 0efb4h
		825	C1LAR12 equ 0efc4h
		826	C1LAR13 equ 0efd4h
		827	C1LAR14 equ 0efe4h
		828	C1LAR15 equ 0eff4h
		829	C1LGML equ 0ef0ah ; CAN1 Lower Global Mask Support Long
		830	C1LMLM equ 0ef0eh ; CAN1 Lower Mask Of Last Message
		831	C1MCFG1 equ 0ef16h ; CAN1 Message Configuration Register
		832	C1MCFG2 equ 0ef26h
		833	C1MCFG3 equ 0ef36h
		834	C1MCFG4 equ 0ef46h
		835	C1MCFG5 equ 0ef56h
		836	C1MCFG6 equ 0ef66h
		837	C1MCFG7 equ 0ef76h
		838	C1MCFG8 equ 0ef86h
		839	C1MCFG9 equ 0ef96h
		840	C1MCFG10 equ 0efa6h
		841	C1MCFG11 equ 0efb6h
		842	C1MCFG12 equ 0efc6h
		843	C1MCFG13 equ 0efd6h
		844	C1MCFG14 equ 0efe6h
		845	C1MCFG15 equ 0eff6h
		846	C1MCR1 equ 0ef10h ; CAN1 Message Control Register
		847	C1MCR2 equ 0ef20h
		848	C1MCR3 equ 0ef30h
		849	C1MCR4 equ 0ef40h
		850	C1MCR5 equ 0ef50h
		851	C1MCR6 equ 0ef60h
		852	C1MCR7 equ 0ef70h
		853	C1MCR8 equ 0ef80h
		854	C1MCR9 equ 0ef90h
		855	C1MCR10 equ 0efa0h
		856	C1MCR11 equ 0efb0h
		857	C1MCR12 equ 0efc0h
		858	C1MCR13 equ 0efd0h
		859	C1MCR14 equ 0efe0h
		860	C1MCR15 equ 0eff0h
		861	C1PCIR equ 0ef02h ; CAN1 Port Control and Interrupt Register
		862	C1UAR1 equ 0ef12h ; CAN1 Upper Arbitration Register
		863	C1UAR2 equ 0ef22h
		864	C1UAR3 equ 0ef32h
		865	C1UAR4 equ 0ef42h
		866	C1UAR5 equ 0ef52h
		867	C1UAR6 equ 0ef62h
		868	C1UAR7 equ 0ef72h
		869	C1UAR8 equ 0ef82h
		870	C1UAR9 equ 0ef92h
		871	C1UAR10 equ 0efa2h
		872	C1UAR11 equ 0efb2h
		873	C1UAR12 equ 0efc2h
		874	C1UAR13 equ 0efd2h
		875	C1UAR14 equ 0efe2h
		876	C1UAR15 equ 0eff2h
		877	C1UGML equ 0ef08h ; CAN1 Upper Global Mask Long
		878	C1UMLM equ 0ef0ch ; CAN1 Upper Mask Of Last Message
		879	endif
		880	if _n>=168
		881
		882	;bitram; DefIntBits C2, 0ee02h ; CAN2 Interrupt Control Register
		883	C2BTR equ 0ee04h ; CAN2 Bit Timing Register
		884	C2CSR equ 0ee00h ; CAN2 Control Status Register
		885	C2GMS equ 0ee06h ; CAN2 Global Mask Support
		886	C2LAR1 equ 0ee14h ; CAN2 Lower Arbitration Register
		887	C2LAR2 equ 0ee24h
		888	C2LAR3 equ 0ee34h
		889	C2LAR4 equ 0ee44h
		890	C2LAR5 equ 0ee54h
		891	C2LAR6 equ 0ee64h
		892	C2LAR7 equ 0ee74h
		893	C2LAR8 equ 0ee84h
		894	C2LAR9 equ 0ee94h
		895	C2LAR10 equ 0eea4h
		896	C2LAR11 equ 0eeb4h
		897	C2LAR12 equ 0eec4h
		898	C2LAR13 equ 0eed4h
		899	C2LAR14 equ 0eee4h
		900	C2LAR15 equ 0eef4h
		901	C2LGML equ 0ee0ah ; CAN2 Lower Global Mask Support
		902	C2LMLM equ 0ee0eh ; CAN2 Lower Mask Of Last Message
		903	C2MCFG1 equ 0ee16h ; CAN2 Message Configuration Register
		904	C2MCFG2 equ 0ee26h
		905	C2MCFG3 equ 0ee36h
		906	C2MCFG4 equ 0ee46h
		907	C2MCFG5 equ 0ee56h
		908	C2MCFG6 equ 0ee66h
		909	C2MCFG7 equ 0ee76h
		910	C2MCFG8 equ 0ee86h
		911	C2MCFG9 equ 0ee96h
		912	C2MCFG10 equ 0eea6h
		913	C2MCFG11 equ 0eeb6h
		914	C2MCFG12 equ 0eec6h
		915	C2MCFG13 equ 0eed6h
		916	C2MCFG14 equ 0eee6h
		917	C2MCFG15 equ 0eef6h
		918	C2MCR1 equ 0ee10h ; CAN2 Message Control Register
		919	C2MCR2 equ 0ee20h
		920	C2MCR3 equ 0ee30h
		921	C2MCR4 equ 0ee40h
		922	C2MCR5 equ 0ee50h
		923	C2MCR6 equ 0ee60h
		924	C2MCR7 equ 0ee70h
		925	C2MCR8 equ 0ee80h
		926	C2MCR9 equ 0ee90h
		927	C2MCR10 equ 0eea0h
		928	C2MCR11 equ 0eeb0h
		929	C2MCR12 equ 0eec0h
		930	C2MCR13 equ 0eed0h
		931	C2MCR14 equ 0eee0h
		932	C2MCR15 equ 0eef0h
		933	C2PCIR equ 0ee02h ; CAN2 Port Control And Interrupt Register
		934	C2UAR1 equ 0ee12h ; CAN2 Upper Arbitration Register
		935	C2UAR2 equ 0ee22h
		936	C2UAR3 equ 0ee32h
		937	C2UAR4 equ 0ee42h
		938	C2UAR5 equ 0ee52h
		939	C2UAR6 equ 0ee62h
		940	C2UAR7 equ 0ee72h
		941	C2UAR8 equ 0ee82h
		942	C2UAR9 equ 0ee92h
		943	C2UAR10 equ 0eea2h
		944	C2UAR11 equ 0eeb2h
		945	C2UAR12 equ 0eec2h
		946	C2UAR13 equ 0eed2h
		947	C2UAR14 equ 0eee2h
		948	C2UAR15 equ 0eef2h
		949	C2UGML equ 0ee08h ; CAN2 Upper Global Mask Support
		950	C2UMLM equ 0ee0ch ; CAN2 Upper Mask Of Last Message
		951	endif
		952
		953
		954	;----------------------------------------------------------------------------
		955	; Vectors / Special Addresses
		956
		957	RESET equ 000h ; Reset Entry
		958	NMITRAP equ 008h ; NMI Entry
		959	STOTRAP equ 010h ; Entry Stack Overflow
		960	STUTRAP equ 018h ; Entry Stack Underflow
		961	BTRAP equ 028h ; Undefined Opcode, Protection Fault,
		962	; Invalid Word Access, Invalid Instruction Address,
		963	; Invalid Bus Access
		964	CC0INT equ 040h ; Interrupt Entry CAPCOM
		965	CC1INT equ 044h
		966	CC2INT equ 048h
		967	CC3INT equ 04ch
		968	CC4INT equ 050h
		969	CC5INT equ 054h
		970	CC6INT equ 058h
		971	CC7INT equ 05ch
		972	CC8INT equ 060h
		973	CC9INT equ 064h
		974	CC10INT equ 068h
		975	CC11INT equ 06ch
		976	CC12INT equ 070h
		977	CC13INT equ 074h
		978	CC14INT equ 078h
		979	CC15INT equ 07ch
		980	if _n>=167
		981	CC16INT equ 0c0h
		982	CC17INT equ 0c4h
		983	CC18INT equ 0c8h
		984	CC19INT equ 0cch
		985	CC20INT equ 0d0h
		986	CC21INT equ 0d4h
		987	CC22INT equ 0d8h
		988	CC23INT equ 0dch
		989	CC24INT equ 0e0h
		990	CC25INT equ 0e4h
		991	CC26INT equ 0e8h
		992	CC27INT equ 0ech
		993	CC28INT equ 0f0h
		994	CC29INT equ 0110h
		995	CC30INT equ 0114h
		996	CC31INT equ 0118h
		997	endif
		998
		999
		1000	T0INT equ 080h ; Interrupt Entry Timer 0
		1001	T1INT equ 084h ; Interrupt Entry Timer 1
		1002	T2INT equ 088h ; Interrupt Entry Timer 2
		1003	T3INT equ 08ch ; Interrupt Entry Timer 3
		1004	T4INT equ 090h ; Interrupt Entry Timer 4
		1005	T5INT equ 094h ; Interrupt Entry Timer 5
		1006	T6INT equ 098h ; Interrupt Entry Timer 6
		1007	if _n>=167
		1008	T7INT equ 0f4h ; Interrupt Entry Timer 7
		1009	T8INT equ 0f8h ; Interrupt Entry Timer 8
		1010	endif
		1011
		1012
		1013	CRINT equ 09ch ; Interrupt Entry CAPREL
		1014	ADCINT equ 0a0h ; Interrupt Entry A/D Conversion Complete
		1015	ADEINT equ 0a4h ; Interrupt Entry A/D Converter Overflow
		1016	S0TINT equ 0a8h ; Interrupt Entry SIO0 Ready to Send
		1017	S0RINT equ 0ach ; Interrupt Entry SIO0 Character Reception
		1018	S0EINT equ 0b0h ; Interrupt Entry SIO0 Error
		1019	S1TINT equ 0b4h ; Interrupt Entry SIO1 Ready to Send
		1020	S1RINT equ 0b8h ; Interrupt Entry SIO1 Character Reception
		1021	S1EINT equ 0bch ; Interrupt Entry SIO1 Error
		1022	if _n>=167
		1023	S0TBINT equ 011ch ; ASC0 Transmit Buffer
		1024	PWMINT equ 0fch ; PWM Channels 0..3
		1025	XP0INT equ 0100h ; CAN1
		1026	XP1INT equ 0104h ; CAN2
		1027	XP2INT equ 0108h ; Unassigned Node
		1028	XP3INT equ 010ch ; PLL,OWD,RTC
		1029	endif
		1030
		1031
		1032	;----------------------------------------------------------------------------
		1033	; Memory Ranges
		1034
		1035	switch _n
		1036	case 168
		1037	IRAM equ 0f200h ; Start of Internal RAM
		1038	case 167
		1039	IRAM equ 0f600h
		1040	elsecase
		1041	IRAM equ 0fa00h
		1042	endcase
		1043	IRAMEND equ 0fdffh ; End " " "
		1044
		1045
		1046	BITRAM equ 0fd00h ; Start of Bit Addressable IRAM Area
		1047	BITRAMEND equ 0fdffh ; End " " " " "
		1048
		1049	if _n>=167
		1050	BITRAM1 equ 0f100h ; Start of Bit Addressable ESFR Area
		1051	BITRAM1END equ 0f1ffh ; End " " " " "
		1052	BITRAM2 equ 0ff00h ; Start of Bit Addressable SFR Area
		1053	BITRAM2END equ 0ffffh ; End " " " " "
		1054	endif
		1055
		1056
		1057	if _n>=167
		1058	PECPTR equ 0fce0h ; Start of PEC-Vektoren (optional)
		1059	PECPTREND equ 0fcffh ; End " "
		1060	elseif
		1061	PECPTR equ 0fde0h
		1062	PECPTREND equ 0fdffh
		1063	endif
		1064
		1065	SFRSTART equ 0fe00h ; Start of SFR-Bereich
		1066	SFREND equ 0ffffh ; End SFR-Bereich
		1067
		1068	if _n>=167
		1069	ESFRSTART equ 0f000h ; Start of Extended SFR Area
		1070	ESFREND equ 0f1ffh ; End of Extended SFR Area
		1071	endif
		1072
		1073	IROM equ 0 ; Start of Internal ROM
		1074	if _n>=167
		1075	IROMEND equ 07fffh ; End of Internal ROM (not fully populated)
		1076	elseif
		1077	IROMEND equ 01fffh
		1078	endif
		1079
		1080	if _n>=168
		1081	EEPROM equ 08000h ; Start of Internal 4 KByte EEprom
		1082	EEPROMEND equ 08fffh ; End of Internal EEprom
		1083	endif
		1084	if _n>=167
		1085	XRAM1 equ 0e000h ; Internal XRAM 2 KByte Start
		1086	XRAM1END equ 0e7ffh ; Internal XRAM 2 KByte End
		1087	endif
		1088	if _n>=168
		1089	XRAM2 equ 0c000h ; Internal XRAM 6 KByte Start
		1090	XRAM2END equ 0d7ffh ; Internal XRAM 6 KByte End
		1091	endif
		1092
		1093
		1094	;----------------------------------------------------------------------------
		1095	; Bequemlichkeitsmakros
		1096
		1097	clr macro op ; Set Operand to 0
		1098	and op,#0
		1099	endm
		1100
		1101	bchg macro op ; Invert Bit
		1102	bmovn op,op
		1103	endm
		1104
		1105	dec macro op ; Decrement
		1106	sub op,#1
		1107	endm
		1108
		1109	inc macro op ; Increment
		1110	add op,#1
		1111	endm
		1112
		1113	swapb macro op ; Swap Bytes
		1114	ror op,#8
		1115	endm
		1116
		1117	;----------------------------------------------------------------------------
		1118
		1119	restore ; enable listing again
		1120
		1121	endif ; reg166inc

Subversion Repositories pentevo

(root)/tools/asl/asl-current/include/reg166.inc – Rev 1186