WebSVN – pentevo – Blame – /tools/asl/asl-current/include/coldfire/mcf5208.inc

Rev	Author	Line No.	Line
1126	savelij	1	ifndef __mcf5208inc ; avoid multiple inclusion
		2	__mcf5208inc equ 1
		3
		4	save
		5	listing off ; no listing over this file
		6
		7	;****************************************************************************
		8	;* *
		9	;* AS 1.42 - File MCF5208.INC *
		10	;* *
		11	;* Contains SFR and Bit Definitions for ColdFire MCF5208 *
		12	;* *
		13	;****************************************************************************
		14
		15	MBAR equ $fc000000
		16
		17	;----------------------------------------------------------------------------
		18	; Clock Module
		19
		20	MBAR_CLK equ MBAR+$9000
		21
		22	PODR equ MBAR_CLK+0 ; PLL Output Divider Register (8b)
		23	BUSDIV cffield PODR,0,4 ; Divider for generating the internal bus frequency
		24	CPUDIV cffield PODR,4,4 ; Divider for generating the core frequency
		25	PCR equ MBAR_CLK+2 ; PLL Control Register (8b)
		26	DITHEN cfbit PCR,7 ; Dithering enable bit
		27	DITHDEV cffield PCR,0,3 ; Dither Deviation
		28	PMDR equ MBAR_CLK+4 ; PLL Modulation Divider Register (8b)
		29	MODDIV cffield PMDR,0,8 ; Dither Modulation Divider
		30	PFDR equ MBAR_CLK+6 ; PLL Feedback Divider Register (8b)
		31	MFD cffield PFDR,0,8 ; Feedback Bits
		32
		33	;----------------------------------------------------------------------------
		34	; Power Management
		35
		36	WCR equ MBAR+$40013 ; Wakeup Control Register (8b)
		37	ENBWCR cfbit WCR,7 ; Enable low-power mode entry
		38	PRILVL cffield WCR,0,3 ; Exit low-power mode interrupt priority level
		39	PPMSR0 equ MBAR+$4002c ; Peripheral Power Management Set Register 0 (8b)
		40	SAMCD cfbit PPMSR0,6 ; Set all module clock disables
		41	SMCD cffield PPMSR0,0,6 ; Set module clock disable
		42	PPMCR0 equ MBAR+$4002d ; Peripheral Power Management Clear Register 0 (8b)
		43	CAMCD cfbit PPMCR0,6 ; Clear all module clock disables
		44	CMCD cffield PPMCR0,0,6 ; Clear module clock disable
		45	PPMHR0 equ MBAR+$40030 ; Peripheral Power Management High Register 0 (32b)
		46	CD42 cfbit PPMHR0,10 ; PIT 0
		47	CD41 cfbit PPMHR0,9 ; PIT 1
		48	CD40 cfbit PPMHR0,8 ; Edge Port
		49	CD36 cfbit PPMHR0,4 ; On-chip Watchdog Timer
		50	CD35 cfbit PPMHR0,3 ; PLL
		51	CD34 cfbit PPMHR0,2 ; CCM, Reset Controller, Power Management
		52	CD33 cfbit PPMHR0,1 ; GPIO Module
		53	CD32 cfbit PPMHR0,0 ; SDRAM Controller
		54	PPMLR0 equ MBAR+$40034 ; Peripheral Power Management Low Register 0 (32b)
		55	CD31 cfbit PPMLR0,31 ; DMA Timer 3
		56	CD30 cfbit PPMLR0,30 ; DMA Timer 2
		57	CD29 cfbit PPMLR0,29 ; DMA Timer 1
		58	CD28 cfbit PPMLR0,28 ; DMA Timer 0
		59	CD26 cfbit PPMLR0,26 ; UART2
		60	CD25 cfbit PPMLR0,25 ; UART1
		61	CD24 cfbit PPMLR0,24 ; UART0
		62	CD23 cfbit PPMLR0,23 ; QSPI
		63	CD22 cfbit PPMLR0,22 ; I2C
		64	CD21 cfbit PPMLR0,21 ; IACK
		65	CD18 cfbit PPMLR0,18 ; Interrupt Controller
		66	CD17 cfbit PPMLR0,17 ; eDMA Controller
		67	CD12 cfbit PPMLR0,12 ; FEC
		68	CD2 cfbit PPMLR0,2 ; FlexBus
		69	LPCR equ MBAR+$a0007 ; Low-Power Control Register (8b)
		70	LPMD cffield LPCR,6,2 ; Low-power mode select
		71	FWKUP cfbit LPCR,5 ; Fast wake-up
		72	STPMD cffield LPCR,3,2 ; FB_CLK stop mode bits
		73	MISCCR equ MBAR+$a0010 ; Miscellaneous Control Register (16b)
		74	PLLLOCK cfbit MISCCR,13 ; PLL lock status
		75	LIMP cfbit MISCCR,12 ; Limp mode enable
		76	LPDIV cffield MISCCR,0,4 ; Low power divider
		77
		78	;----------------------------------------------------------------------------
		79	; Chip Configuration Module
		80
		81	MBAR_CCM equ MBAR+$a0000
		82	CCR equ MBAR_CCM+$0 ; Chip Configuration Register (16b)
		83	CSC cfbit CCR,9 ; Chip select configuration field
		84	OSCFREQ cfbit CCR,7 ; Oscillator frequency
		85	LIMP cfbit CCR,6 ; Limp mode
		86	LOAD cfbit CCR,5 ; Pad driver load
		87	BOOTPS cffield CCR,3,2 ; Boot port size
		88	OSCMODE cfbit CCR,2 ; Oscillator clock mode
		89	PLLMODE cfbit CCR,1 ; PLL clock mode
		90	RCON equ MBAR_CCM+$4 ; Reset Configuration Register (16b)
		91	CSC cfbit RCON,9 ; Chip select configuration field
		92	OSCFREQ cfbit RCON,7 ; Oscillator frequency
		93	LIMP cfbit RCON,6 ; Limp mode
		94	LOAD cfbit RCON,5 ; Pad driver load
		95	BOOTPS cffield RCON,3,2 ; Boot port size
		96	OSCMODE cfbit RCON,2 ; Oscillator clock mode
		97	PLLMODE cfbit RCON,1 ; PLL clock mode
		98	CIR equ MBAR_CCM+$a ; Chip Identification Register (16b)
		99	PIN cffield CIR,8,8 ; Part identification number
		100	PRN cffield CIR,0,8 ; Part revision number
		101
		102	;----------------------------------------------------------------------------
		103	; Reset Controller Module
		104
		105	MBAR_RCM equ MBAR+$a0000
		106	RCR equ MBAR_RCM+0 ; Reset Control Register (8b)
		107	SOFTRST cfbit RCR,7 ; Allows software to request a reset
		108	FRCRSTOUT cfbit RCR,6 ; Allows software to assert or negate the external /RSTOUT pin
		109	RSR equ MBAR_RCM+1 ; Reset Status Register (8b)
		110	SOFT cfbit RSR,5 ; Software reset flag
		111	WDRCHIP cfbit RSR,4 ; On-chip watchdog timer reset flag
		112	POR cfbit RSR,3 ; Power-on reset flag
		113	EXT cfbit RSR,2 ; External reset flag
		114	WDRCORE cfbit RSR,1 ; Core watchdog timer reset flag
		115	LOL cfbit RSR,0 ; Loss-of-lock reset flag
		116
		117	;----------------------------------------------------------------------------
		118	; System Control Module
		119
		120	MBAR_SCM equ MBAR+$0000
		121
		122	__defprot macro {INTLABEL},Reg,Startbit
		123	__LABEL__ cffield Reg,Startbit,4
		124	__LABEL__.MTR cfbit Reg,Startbit+0 ; Master trusted for read
		125	__LABEL__.MTW cfbit Reg,Startbit+1 ; Master trusted for writes
		126	__LABEL__.MPL cfbit Reg,Startbit+2 ; Master privilege level
		127	endm
		128	MPR equ MBAR_SCM+$00 ; Master Privilege Register (32b)
		129	MPROT0 __defprot MBAR_SCM,28 ; ColdFire Core:
		130	MPROT1 __defprot MBAR_SCM,24 ; eDMA Controller:
		131	MPROT2 __defprot MBAR_SCM,20 ; FEC:
		132
		133	__defpacr macro {INTLABEL},Reg,Startbit
		134	__LABEL__ cffield Reg,Startbit,4
		135	__LABEL__.TP cfbit Reg,Startbit+0 ; Trusted Protect
		136	__LABEL__.WP cfbit Reg,Startbit+1 ; Write protect
		137	__LABEL__.SP cfbit Reg,Startbit+2 ; Supervisor protect.
		138	endm
		139	PACRA equ MBAR_SCM+$20 ; Peripheral Access Control Register A (32b)
		140	PACR0 __defpacr PACRA,28 ; SCM (MPR & PACRs)
		141	PACR1 __defpacr PACRA,24 ; Cross-Bar Switch
		142	PACR2 __defpacr PACRA,20 ; FlexBus
		143	PACRB equ MBAR_SCM+$24 ; Peripheral Access Control Register B (32b)
		144	PACR12 __defpacr PACRB,12 ; FEC
		145	PACRC equ MBAR_SCM+$28 ; Peripheral Access Control Register C (32b)
		146	PACR16 __defpacr PACRC,28 ; SCM (CWT & Core Fault Registers
		147	PACR17 __defpacr PACRC,24 ; eDMA Controller
		148	PACR18 __defpacr PACRC,20 ; Interrupt Controller 0
		149	PACR21 __defpacr PACRC,8 ; Interrupt Controller IACK
		150	PACR22 __defpacr PACRC,4 ; I2C
		151	PACR23 __defpacr PACRC,0 ; QSPI
		152	PACRD equ MBAR_SCM+$2C ; Peripheral Access Control Register D (32b)
		153	PACR24 __defpacr PACRD,28 ; UART0
		154	PACR25 __defpacr PACRD,24 ; UART1
		155	PACR26 __defpacr PACRD,20 ; UART2
		156	PACR28 __defpacr PACRD,12 ; DMA Timer 0
		157	PACR29 __defpacr PACRD,8 ; DMA Timer 1
		158	PACR30 __defpacr PACRD,4 ; DMA Timer 2
		159	PACR31 __defpacr PACRD,0 ; DMA Timer 3
		160	PACRE equ MBAR_SCM+$40 ; Peripheral Access Control Register E (32b)
		161	PACR32 __defpacr PACRE,28 ; PIT 0
		162	PACR33 __defpacr PACRE,24 ; PIT 1
		163	PACR34 __defpacr PACRE,20 ; Edge Port
		164	PACR35 __defpacr PACRE,16 ; On-Chip Watchdog Timer
		165	PACR36 __defpacr PACRE,12 ; PLL
		166	PACRF equ MBAR_SCM+$44 ; Peripheral Access Control Register F (32b)
		167	PACR40 __defpacr PACRF,28 ; CCM, Reset Controller, Power Management
		168	PACR41 __defpacr PACRF,24 ; GPIO Module
		169	PACR42 __defpacr PACRF,20 ; SDRAM Controller
		170	BMT equ MBAR_SCM+$54 ; Bus Monitor Timeout (32b)
		171	BMT cffield BMT,0,3 ; Bus Monitor Timeout Period
		172	BME cfbit BMT,3 ; Bus Monitor Timeout Enable
		173	CWCR equ MBAR_SCM+$40016 ; Core Watchdog Control Register (16b)
		174	RO cfbit CWCR,15 ; Read-Only Control
		175	CWRWH cfbit CWCR,8 ; Core Watchdog run while halted
		176	CWE cfbit CWCR,7 ; Core Watchdog Timer Enable
		177	CWRI cffield CWCR,5,2 ; Core Watchdog Reset/Interrupt
		178	CWT cffield CWCR,0,5 ; Core Watchdog Time-Out Period
		179	CWSR equ MBAR_SCM+$4001B ; Core Watchdog Service Register (8b)
		180	SCMISR equ MBAR_SCM+$4001F ; SCM Interrupt Status Register (8b)
		181	CFEI cfbit SCMISR,1 ; Core Fault Error Interrupt Flag
		182	CWIC cfbit SCMISR,0 ; Core Watchdog Interrupt Flag
		183	CFADR equ MBAR_SCM+$40070 ; Core Fault Address Register (32b)
		184	CFIER equ MBAR_SCM+$40075 ; Core Fault Interrupt Enable Register (8b)
		185	ECFEI cfbit CFIER,0 ; Enable Core Fault Error Interrupt
		186	CFLOC equ MBAR_SCM+$40076 ; Core Fault Location Register (8b)
		187	LOC cfbit CFLOC,7 ; Location of the last captured fault
		188	CFATR equ MBAR_SCM+$40077 ; Core Fault Attributes Register (8b)
		189	WRITE cfbit CFATR,7 ; Direction of the last faulted core access
		190	SIZE cffield CFATR,4,2 ; Size of the last faulted core access
		191	CACHE cfbit CFATR,3 ; Indicates if last faulted core access was cacheable
		192	MODE cfbit CFATR,1 ; Indicates the mode the device was in during the last faulted core access
		193	TYPE cfbit CFATR,0 ; Defines the type of last faulted core access
		194	CFDTR equ MBAR_SCM+$4007C ; Core Fault Data Register (32b)
		195
		196	;----------------------------------------------------------------------------
		197	; Crossbar Switch
		198
		199	MBAR_XBS equ MBAR+$4000
		200	__defxbs macro n,Base
		201	XBS_PRS{n} equ Base+$00 ; Priority Register (32b)
		202	M7 cffield XBS_PRS{n},28,3 ; Master 7 (Factory Test) Priority
		203	M2 cffield XBS_PRS{n},8,3 ; Master 2 (FEC) Priority
		204	M1 cffield XBS_PRS{n},4,3 ; Master 1 (eDMA) Priority
		205	M0 cffield XBS_PRS{n},0,3 ; Master 0 (ColdFire core) Priority
		206	XBS_CRS{n} equ Base+$10 ; Control Register (32b)
		207	RO cfbit XBS_CRS{n},31 ; Read Only
		208	ARB cfbit XBS_CRS{n},8 ; Arbitration Mode
		209	PCTL cffield XBS_CRS{n},4,2 ; Parking Control
		210	PARK cffield XBS_CRS{n},0,3 ; Park
		211	endm
		212	__defxbs "1",MBAR_XBS+$100
		213	__defxbs "4",MBAR_XBS+$400
		214	__defxbs "7",MBAR_XBS+$700
		215
		216	;----------------------------------------------------------------------------
		217	; GPIO Module
		218
		219	MBAR_GPIO equ MBAR+$a4000
		220
		221	; Port Output Data Registers
		222
		223	PODR_BUSCTL equ MBAR_GPIO+$000 ; Bus Control Output Data Register (8b)
		224	PODR_BE equ MBAR_GPIO+$001 ; Byte Enable Output Data Register (8b)
		225	PODR_CS equ MBAR_GPIO+$002 ; Chip Select Output Data Register (8b)
		226	PODR_FECI2C equ MBAR_GPIO+$003 ; FEC/I2C Output Data Register (8b)
		227	PODR_QSPI equ MBAR_GPIO+$004 ; QSPI Output Data Register (8b)
		228	PODR_TIMER equ MBAR_GPIO+$005 ; Timer Output Data Register (8b)
		229	PODR_UART equ MBAR_GPIO+$006 ; UART Output Data Register (8b)
		230	PODR_FECH equ MBAR_GPIO+$007 ; FEC High Output Data Register (8b)
		231	PODR_FECL equ MBAR_GPIO+$008 ; FEC Low Output Data Register (8b)
		232
		233	; Port Data Direction Registers
		234
		235	PDDR_BUSCTL equ MBAR_GPIO+$00C ; Bus Control Data Direction Register (8b)
		236	PDDR_BE equ MBAR_GPIO+$00D ; Byte Enable Data Direction Register (8b)
		237	PDDR_CS equ MBAR_GPIO+$00E ; Chip Select Data Direction Register (8b)
		238	PDDR_FECI2C equ MBAR_GPIO+$00F ; FEC/I2C Data Direction Register (8b)
		239	PDDR_QSPI equ MBAR_GPIO+$010 ; QSPI Data Direction Register (8b)
		240	PDDR_TIMER equ MBAR_GPIO+$011 ; Timer Data Direction Register (8b)
		241	PDDR_UART equ MBAR_GPIO+$012 ; UART Data Direction Register (8b)
		242	PDDR_FECH equ MBAR_GPIO+$013 ; FEC High Data Direction Register (8b)
		243	PDDR_FECL equ MBAR_GPIO+$014 ; FEC Low Data Direction Register (8b)
		244
		245	; Port Pin Data/Set Data Registers
		246
		247	PPDSDR_CS equ MBAR_GPIO+$01A ; Chip Select Pin Data/Set Data Register (8b)
		248	PPDSDR_FECI2C equ MBAR_GPIO+$01B ; FEC/I2C Pin Data/Set Data Register (8b)
		249	PPDSDR_QSPI equ MBAR_GPIO+$01C ; QSPI Pin Data/Set Data Register (8b)
		250	PPDSDR_TIMER equ MBAR_GPIO+$01D ; Timer Pin Data/Set Data Register (8b)
		251	PPDSDR_UART equ MBAR_GPIO+$01E ; UART Pin Data/Set Data Register (8b)
		252	PPDSDR_FECH equ MBAR_GPIO+$01F ; FEC High Pin Data/Set Data Register (8b)
		253	PPDSDR_FECL equ MBAR_GPIO+$020 ; FEC Low Pin Data/Set Data Register (8b)
		254
		255	; Port Clear Output Data Registers
		256
		257	PCLRR_BUSCTL equ MBAR_GPIO+$024 ; Bus Control Clear Output Data Register (8b)
		258	PCLRR_BE equ MBAR_GPIO+$025 ; Byte Enable Clear Output Data Register (8b)
		259	PCLRR_CS equ MBAR_GPIO+$026 ; Chip Select Clear Output Data Register (8b)
		260	PCLRR_FECI2C equ MBAR_GPIO+$027 ; FEC/I2C Clear Output Data Register (8b)
		261	PCLRR_QSPI equ MBAR_GPIO+$028 ; QSPI Clear Output Data Register (8b)
		262	PCLRR_TIMER equ MBAR_GPIO+$029 ; Timer Clear Output Data Register (8b)
		263	PCLRR_UART equ MBAR_GPIO+$02A ; UART Clear Output Data Register (8b)
		264	PCLRR_FECH equ MBAR_GPIO+$02B ; FEC High Clear Output Data Register (8b)
		265	PCLRR_FECL equ MBAR_GPIO+$02C ; FEC Low Clear Output Data Register (8b)
		266
		267	; Pin Assignment Registers
		268
		269	PAR_BUSCTL equ MBAR_GPIO+$030 ; External Bus Control Pin Assignment Register (8b)
		270	PAR_OE cfbit PAR_BUSCTL,4 ; /OE Pin Assignment
		271	PAR_TA cfbit PAR_BUSCTL,3 ; /TA Pin Assignment
		272	PAR_RWB cfbit PAR_BUSCTL,2 ; R/-W Pin Assignment
		273	PAR_TS cffield PAR_BUSCTL,0,2 ; /TS Pin Assignment
		274	PAR_BE equ MBAR_GPIO+$031 ; Byte Enable Pin Assignment Register (8b)
		275	PAR_CS equ MBAR_GPIO+$032 ; Chip Select Pin Assignment Register (8b)
		276	PAR_CS3 cfbit PAR_CS,3 ; /FB_CS3 Pin Assignment
		277	PAR_CS2 cfbit PAR_CS,2 ; /FB_CS2 Pin Assignment
		278	PAR_CS1 cffield PAR_CS,0,2 ; /FB_CS1 Pin Assignment
		279	PAR_FECI2C equ MBAR_GPIO+$033 ; FEC/I2C Pin Assignment (8b)
		280	PAR_MDC cffield PAR_FECI2C,6,2 ; MDC Pin Assignment
		281	PAR_MDIO cffield PAR_FECI2C,4,2 ; MDIO Pin Assignment
		282	PAR_SCL cffield PAR_FECI2C,2,2 ; SCL Pin Assignment
		283	PAR_SDA cffield PAR_FECI2C,0,2 ; SDA Pin Assignment
		284	PAR_QSPI equ MBAR_GPIO+$034 ; QSPI Pin Assignment (8b)
		285	PAR_PCS2 cffield PAR_QSPI,6,2 ; QSPI Pin Assignment
		286	PAR_DIN cffield PAR_QSPI,4,2
		287	PAR_DOUT cffield PAR_QSPI,2,2
		288	PAR_SCK cffield PAR_QSPI,0,2
		289	PAR_TIMER equ MBAR_GPIO+$035 ; Timer Pin Assignment (8b)
		290	PAR_T3IN cffield PAR_TIMER,6,2 ; DMA Timer 3 Pin Assignment
		291	PAR_T2IN cffield PAR_TIMER,4,2 ; DMA Timer 2 Pin Assignment
		292	PAR_T1IN cffield PAR_TIMER,2,2 ; DMA Timer 1 Pin Assignment
		293	PAR_T0IN cffield PAR_TIMER,0,2 ; DMA Timer 0 Pin Assignment
		294	PAR_UART equ MBAR_GPIO+$036 ; UART Pin Assignment (16b)
		295	PAR_U1CTS cffield PAR_UART,10,2 ; UART1 Control Pin Assignment
		296	PAR_U1RTS cffield PAR_UART,8,2 ;
		297	PAR_U1TXD cfbit PAR_UART,7 ; U1TXD Pin Assignment
		298	PAR_U1RXD cfbit PAR_UART,6 ; U1RXD Pin Assignment
		299	PAR_U0CTS cffield PAR_UART,4,2 ; UART0 Control Pin Assignment
		300	PAR_U0RTS cffield PAR_UART,2,2 ;
		301	PAR_U0TXD cfbit PAR_UART,1 ; U0TXD Pin Assignment
		302	PAR_U0RXD cfbit PAR_UART,0 ; U0RXD Pin Assignment
		303	PAR_FEC equ MBAR_GPIO+$038 ; FEC Pin Assignment (8b)
		304	PAR_FEC_7W cffield PAR_FEC,2,2 ; FEC 7-wire Pin Assignment
		305	PAR_FEC_MII cffield PAR_FEC,0,2 ; FEC MII Pin Assignment
		306	PAR_IRQ equ MBAR_GPIO+$039 ; IRQ Pin Assignment (8b)
		307	PAR_IRQ4 cfbit PAR_IRQ,0 ; /IRQ4 Pin Assignment
		308
		309	; Mode Select Control Registers
		310
		311	MSCR_FLEXBUS equ MBAR_GPIO+$03A ; FlexBus Mode Select Control Register (8b)
		312	MSCR_FBCLK cffield MSCR_FLEXBUS,6,2; FB_CLK Mode Select Control
		313	MSCR_DUPPER cffield MSCR_FLEXBUS,4,2; FB_D[31:16] Mode Select Control
		314	MSCR_DLOWER cffield MSCR_FLEXBUS,2,2; FB_D[15:0] Mode Select Control
		315	MSCR_ADDRCTL cffield MSCR_FLEXBUS,0,2; FB_A[23:0], BE/BWE[3:0], OE, R/W, FB_CS[5:0], TA, and TS Mode Select Control
		316	MSCR_SDRAM equ MBAR_GPIO+$03B ; SDRAM Mode Select Control Register (8b)
		317	MSCR_SDCLKB cffield MSCR_SDRAM,4,2 ; SD_CLK Mode Select Control
		318	MSCR_SDCLK cffield MSCR_SDRAM,2,2 ; SD_CLK Mode Select Control
		319	MSCR_SDRAM cffield MSCR_SDRAM,0,2 ; SD_A10, SD_CAS, SD_CKE, SD_CS0, SD_DQS[3:2], SD_RAS, SD_SDRDQS, SD_WE Mode Select Control
		320
		321	; Drive Strength Control Registers
		322
		323	DSCR_I2C equ MBAR_GPIO+$03C ; I2C Drive Strength Control Register (8b)
		324	I2C_DSE cffield DSCR_I2C,0,2 ; I2C Drive Strength Control
		325	DSCR_MISC equ MBAR_GPIO+$03D ; Miscellaneous Drive Strength Control Register (8b)
		326	DEBUG_DSE cffield DSCR_MISC,4,2 ; Debug Drive Strength Control
		327	RSTOUT_DSE cffield DSCR_MISC,2,2 ; /RSTOUT Drive Strength Control
		328	TIMER_DSE cffield DSCR_MISC,0,2 ; Timer Drive Strength Control
		329	DSCR_FEC equ MBAR_GPIO+$03E ; FEC Drive Strength Control Register (8b)
		330	FEC_DSE cffield DSCR_FEC,0,2 ; FEC Drive Strength Control
		331	DSCR_UART equ MBAR_GPIO+$03F ; UART/IRQ Drive Strength Control Register (8b)
		332	UART1_DSE cffield DSCR_UART,4,2 ; UART1 Drive Strength Control
		333	UART0_DSE cffield DSCR_UART,2,2 ; UART0 Drive Strength Control
		334	IRQ_DSE cffield DSCR_UART,0,2 ; IRQ drive strength Control
		335	DSCR_QSPI equ MBAR_GPIO+$040 ; QSPI Drive Strength Control Register (8b)
		336	QSPI_DSE cffield DSCR_QSPI,0,2 ; QSPI Drive Strength Control
		337
		338	;----------------------------------------------------------------------------
		339	; Interrupt Controller Module
		340
		341	MBAR_INTC equ MBAR+$48000
		342
		343	IPRH equ MBAR_INTC+$000 ; Interrupt Pending Register High (32b)
		344	IPRL equ MBAR_INTC+$004 ; Interrupt Pending Register Low (32b)
		345	IMRH equ MBAR_INTC+$008 ; Interrupt Mask Register High (32b)
		346	IMRL equ MBAR_INTC+$00C ; Interrupt Mask Register Low (32b)
		347	INTFRCH equ MBAR_INTC+$010 ; Interrupt Force Register High (32b)
		348	INTFRCL equ MBAR_INTC+$014 ; Interrupt Force Register Low (32b)
		349	ICONFIG equ MBAR_INTC+$01A ; Interrupt Configuration Register (16b)
		350	ELVLPRI cffield ICONFIG,9,7 ; Enable core's priority elevation on priority levels
		351	EMASK cfbit ICONFIG,5 ; If set, the interrupt controller automatically loads the level of an interrupt request into the CLMASK (current level mask) when the acknowledge is performed.
		352	SIMR equ MBAR_INTC+$01C ; Set Interrupt Mask (8b)
		353	SALL cfbit SIMR,6 ; Set all bits in the IMR register
		354	CIMR equ MBAR_INTC+$01D ; Clear Interrupt Mask (8b)
		355	CALL cfbit CIMR,6 ; Clear all bits in the IMR register
		356	CLMASK equ MBAR_INTC+$01E ; Current Level Mask (8b)
		357	SLMASK equ MBAR_INTC+$01F ; Saved Level Mask (8b)
		358	__N set 0
		359	rept 64
		360	__decstr __NS,__N ; note we need name with decimal number!
		361	ICR{"\{__NS}"} set MBAR_INTC+$040+__N ; Interrupt Control Register N (8b)
		362	LEVEL cffield ICR{"\{__NS}"},0,3 ; Interrupt Level
		363	__N set __N+1
		364	endm
		365	SWIACK equ MBAR_INTC+$0E0 ; Software Interrupt Acknowledge (8b)
		366	__N set 1
		367	rept 7
		368	L{"\{__N}"}IACK set MBAR_INTC+$0e0+(4*__N) ; Interrupt Acknowledge Register N (8b)
		369	__N set __n+1
		370	endm
		371
		372	;----------------------------------------------------------------------------
		373	; Edge Port Module
		374
		375	MBAR_EPORT equ MBAR+$88000
		376	include "52xxeport.inc"
		377
		378	;----------------------------------------------------------------------------
		379	; Enhanced Direct Memory Access
		380
		381	MBAR_EDMA equ MBAR+$44000
		382	include "52xxedma.inc"
		383
		384	;----------------------------------------------------------------------------
		385	; FlexBus
		386
		387	MBAR_FBUS equ MBAR+$8000
		388	include "52xxfbus.inc"
		389
		390	;----------------------------------------------------------------------------
		391	; SDRAM Controller
		392
		393	MBAR_SDRAM equ MBAR+$a8000
		394	include "52xxdram.inc"
		395
		396	;----------------------------------------------------------------------------
		397	; Fast Ethernet Controller
		398
		399	MBAR_FEC equ MBAR+$30000
		400	include "52xxfec.inc"
		401
		402	;----------------------------------------------------------------------------
		403	; Watchdog Timer
		404
		405	MBAR_WDT equ MBAR+$8c000
		406	include "52xxwdt.inc"
		407
		408	;----------------------------------------------------------------------------
		409	; Programmable Interrupt Timer
		410
		411	include "52xxpit.inc"
		412	__defpit "1",MBAR+$80000
		413	__defpit "2",MBAR+$84000
		414
		415	;----------------------------------------------------------------------------
		416	; DMA Timer
		417
		418	include "52xxdtim.inc"
		419	__defdtim "0",MBAR+$70000
		420	__defdtim "1",MBAR+$74000
		421	__defdtim "2",MBAR+$78000
		422	__defdtim "3",MBAR+$7c000
		423
		424	;----------------------------------------------------------------------------
		425	; Queued Serial Peripheral Interface
		426
		427	MBAR_QSPI equ MBAR+$5c000
		428	include "52xxqspi.inc"
		429
		430	;----------------------------------------------------------------------------
		431	; UARTs
		432
		433	include "52xxuart.inc"
		434	__defuart "0",MBAR+$60000
		435	__defuart "1",MBAR+$64000
		436	__defuart "2",MBAR+$68000
		437
		438	;----------------------------------------------------------------------------
		439	; I2C
		440
		441	MBAR_I2C equ MBAR+$58000
		442	include "52xxi2c.inc"
		443
		444	;----------------------------------------------------------------------------
		445
		446	restore ; re-enable listing
		447
		448	endif ; __mcf5208inc

Subversion Repositories pentevo

(root)/tools/asl/asl-current/include/coldfire/mcf5208.inc @ 1126 – Rev