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1126 savelij 1 
		ifndef	__52xxpwminc		; avoid multiple inclusion
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__52xxpwminc	equ	1
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		save
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		listing	off			; no listing over this file
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;****************************************************************************
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;*                                                                          *
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;*   AS 1.42 - File 52XXPWM.INC                                             *
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;*                                                                          *
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;*   Contains SFR and Bit Definitions for ColdFire MCF52xx PWM Module       *
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;*                                                                          *
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;****************************************************************************
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PWME		equ		MBAR_PWM+$020	; PWM Enable Register (8b)
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PWME7		cfbit		PWME,7		;  PWM Channel 7 Enable.
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PWME5		cfbit		PWME,5		;  PWM Channel 5 Output Enable.
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PWME3		cfbit		PWME,3		;  PWM Channel 3 Output Enable.
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PWME1		cfbit		PWME,1		;  PWM Channel 1 Output Enable.
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PWMPOL		equ		MBAR_PWM+$021	; PWM Polarity Register (8b)
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PPOL7		cfbit		PWMPOL,7	;  PWM channel 7 polarity.
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PPOL5		cfbit		PWMPOL,5	;  PWM channel 5 polarity.
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PPOL3		cfbit		PWMPOL,3	;  PWM channel 3 polarity.
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PPOL1		cfbit		PWMPOL,1	;  PWM channel 1 polarity.
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PWMCLK		equ		MBAR_PWM+$022	; PWM Clock Select Register (8b)
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PCLK7		cfbit		PWMCLK,7	;  PWM channel 7 clock select.
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PCLK5		cfbit		PWMCLK,5	;  PWM channel 5 clock select.
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PCLK3		cfbit		PWMCLK,3	;  PWM channel 3 clock select.
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PCLK1		cfbit		PWMCLK,1	;  PWM channel 1 clock select.
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PWMPRCLK	equ		MBAR_PWM+$023	; PWM Prescale Clock Select Register (8b)
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PCKB		cffield		PWMPRCLK,4,3	;  Clock B prescaler select.
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PCKA		cffield		PWMPRCLK,0,3	;  Clock A prescaler select.
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PWMCAE		equ		MBAR_PWM+$024	; PWM Center Align Enable Register (8b)
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CAE7		cfbit		PWMCAE,7	;  Center align enable for channel 7.
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CAE5		cfbit		PWMCAE,5	;  Center align enable for channel 5.
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CAE3		cfbit		PWMCAE,3	;  Center align enable for channel 3.
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CAE1		cfbit		PWMCAE,1	;  Center align enable for channel 1.
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PWMCTL		equ		MBAR_PWM+$025	; PWM Control Register (8b)
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CON67		cfbit		PWMCTL,7	;  Concatenates PWM channels 6 and 7 to form one 16-bit PWM channel.
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CON45		cfbit		PWMCTL,6	;  Concatenates PWM channels 4 and 5 to form one 16-bit PWM channel.
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CON23		cfbit		PWMCTL,5	;  Concatenates PWM channels 2 and 3 to form one 16-bit PWM channel.
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CON01		cfbit		PWMCTL,4	;  Concatenates PWM channels 0 and 1 to form one 16-bit PWM channel.
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PSWAI		cfbit		PWMCTL,3	;  PWM stops in doze mode.
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PFRZ		cfbit		PWMCTL,2	;  PWM counters stop in debug mode
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PWMSCLA		equ		MBAR_PWM+$028	; PWM Scale A Register (8b)
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SCALEA		cffield		PWMSCLA,0,8	;  Part of divisor used to form Clock SA from Clock A.
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PWMSCLB		equ		MBAR_PWM+$029	; PWM Scale B Register (8b)
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SCALEB		cffield		PWMSCLB,0,8	;  Divisor used to form Clock SB from Clock B.
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__N		set		0
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		rept		8
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		__decstr	__NS,__N
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PWMCNT{"\{__NS}"}	equ	MBAR_PWM+$02C+__N	; PWM Channel n Counter Register (8b)
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COUNT		cffield		PWMCNT{"\{__NS}"},0,8	;  Current value of the PWM up counter.
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PWMPER{"\{__NS}"}	equ	MBAR_PWM+$034+__N	; PWM Channel n Period Register (8b)
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PERIOD		cffield		PWMPER{"\{__NS}"},0,8	;  Period counter for the output PWM signal.
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PWMDTY{"\{__NS}"}	equ	MBAR_PWM+$03C+__N	; PWM Channel n Duty Register (8b)
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DUTY		cffield		PWMDTY{"\{__NS}"},0,8	;  Contains the duty value used to determine when a transition occurs on the PWM output signal
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__N		set		__N+1
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		endm
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PWMSDN		equ		MBAR_PWM+$044	; PWM Shutdown Register (8b)
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IF		cfbit		PWMSDN,7	;  PWM interrupt flag.
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IE		cfbit		PWMSDN,6	;  PWM interrupt enable.
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RESTART		cfbit		PWMSDN,5	;  PWM restart.
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LVL		cfbit		PWMSDN,4	;  PWM shutdown output level.
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PWM7IN		cfbit		PWMSDN,2	;  PWM channel 7 input status.
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PWM7IL		cfbit		PWMSDN,1	;  PWM channel 7 input polarity.
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SDNEN		cfbit		PWMSDN,0	;  PWM emergency shutdown enable.
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		restore				; re-enable listing
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                endif                           ; __52xxpwminc