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1126 savelij 1 
		ifndef	__52xxedmainc		; avoid multiple inclusion
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__52xxedmainc	equ	1
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		save
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		listing	off			; no listing over this file
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;****************************************************************************
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;*                                                                          *
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;*   AS 1.42 - File 52XXEDMA.INC                                            *
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;*                                                                          *
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;*   Contains SFR and Bit Definitions for ColdFire MCF52xx EDMA             *
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;*                                                                          *
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;****************************************************************************
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EDMA_CR		equ		MBAR_EDMA+$000	; Control Register (32b)
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ERCA		cfbit		EDMA_CR,2	;  Enable Round Robin Channel Arbitration
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EDBG		cfbit		EDMA_CR,1	;  Enable Debug
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EDMA_ES		equ		MBAR_EDMA+$004	; Error Status Register (32b)
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VLD		cfbit		EDMA_ES,31	;  Logical OR of all EDMA_ERR Status Bits
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CPE		cfbit		EDMA_ES,14	;  Channel Priority Error
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ERRCHN		cffield		EDMA_ES,8,4	;  Error Channel Number
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SAE		cfbit		EDMA_ES,7	;  Source Address Error
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SOE		cfbit		EDMA_ES,6	;  Source Offset Error
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DAE		cfbit		EDMA_ES,5	;  Destination Address Error
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DOE		cfbit		EDMA_ES,4	;  Destination Offset Error
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NCE		cfbit		EDMA_ES,3	;  NBYTES/CITER Configuration Error
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SGE		cfbit		EDMA_ES,2	;  Scatter/Gather Configuration Error
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SBE		cfbit		EDMA_ES,1	;  Source Bus Error
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DBE		cfbit		EDMA_ES,0	;  Destination Bus Error
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EDMA_ERQ	equ		MBAR_EDMA+$00E	; Enable Request Register (16b)
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EDMA_EEI	equ		MBAR_EDMA+$016	; Enable Error Interrupt Register (16b)
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EDMA_SERQ	equ		MBAR_EDMA+$018	; Set Enable Request (8b)
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SAER		cfbit		EDMA_SERQ,6	;  Set All Enable Requests
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SERQ		cffield		EDMA_SERQ,0,4	;  Set Enable Request
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EDMA_CERQ	equ		MBAR_EDMA+$019	; Clear Enable Request (8b)
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CAER		cfbit		EDMA_CERQ,6	;  Clear All Enable Requests
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CERQ		cffield		EDMA_CERQ,0,4	;  Clear Enable Request
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EDMA_SEEI	equ		MBAR_EDMA+$01A	; Set Enable Error Interrupt Register (8b)
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SAEE		cfbit		EDMA_CERR,6	;  Sets All Enable Error Interrupts
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SEEI		cffield		EDMA_CERR,0,4	;  Set Enable Error Interrupt
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EDMA_CEEI	equ		MBAR_EDMA+$01B	; Clear Enable Error Interrupt Register (8b)
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CAEE		cfbit		EDMA_CEEI,6	;  Clear All Enable Error Interrupts
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CEEI		cffield		EDMA_CEEI,0,4	;  Clear Enable Error Interrupt
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EDMA_CINT	equ		MBAR_EDMA+$01C	; Clear Interrupt Request Register (8b)
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CAIR		cfbit		EDMA_CINT,6	;  Clear All Interrupt Requests
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CINT		cffield		EDMA_CINT,0,4	;  Clear Interrupt Request
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EDMA_CERR	equ		MBAR_EDMA+$01D	; Clear Error Register (8b)
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CAEI		cfbit		EDMA_CERR,6	;  Clear All Error Indicators
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CERR		cffield		EDMA_CERR,0,4	;  Clear Error Indicator
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EDMA_SSRT	equ		MBAR_EDMA+$01E	; Set START Bit Register (8b)
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SAST		cfbit		EDMA_SSRT,6	;  Set All START Bits
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SSRT		cffield		EDMA_SSRT,0,4	;  Set START Bit
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EDMA_CDNE	equ		MBAR_EDMA+$01F	; Clear DONE Status Bit Register (8b)
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CADN		cfbit		EDMA_CDNE,6	;  Clears All DONE Bits
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CDNE		cffield		EDMA_CDNE,0,4	;  Clear DONE Bit
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EDMA_INT	equ		MBAR_EDMA+$026	; Interrupt Request Register (32b)
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EDMA_ERR	equ		MBAR_EDMA+$02E	; Error Register (32b)
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__N		set		0
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		rept		16
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		__decstr	__NS,__N
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DCHPRI{__NS}	equ		MBAR_EDMA+$100+__N ; Channel n Priority Register (8b)
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ECP		cfbit		DCHPRI{__NS},7	;  Enable Channel Preemption
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CHPRI		cffield		DCHPRI{__NS},0,4 ;  Channel n Arbitration Priority
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TCD{__NS}	equ		MBAR_EDMA+$1000+(__N*32) ; Transfer Control Descriptor (256b)
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TCD{__NS}_SADDR	equ		TCD{__NS}+0	;  Source Address (32b)
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TCD{__NS}_ATTR	equ		TCD{__NS}+4	;  Transfer Attributes (16b)
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SMOD		cffield		TCD{__NS}_ATTR,11,5 ;   Source Address Modulo
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SSIZE		cffield		TCD{__NS}_ATTR,8,3 ;   Source data Transfer Size
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DMOD		cffield		TCD{__NS}_ATTR,3,5 ;   Destination Address Modulo
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DSIZE		cffield		TCD{__NS}_ATTR,0,3 ;   Destination Data Transfer Size
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TCD{__NS}_SOFF	equ		TCD{__NS}+6	;  Signed Source Address Offset (16b)
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TCD{__NS}_NBYTES	equ	TCD{__NS}+8	;  Minor Byte Count (32b)
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TCD{__NS}_SLAST	equ		TCD{__NS}+12	;  Last Source Address Adjustment (32b)
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TCD{__NS}_DADDR	equ		TCD{__NS}+16	;  Destination Address (32b)
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TCD{__NS}_CITER	equ		TCD{__NS}+20	;  Current Minor Loop Link, Major Loop Count (16b)
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E_LINK		cfbit		TCD{__NS}_CITER,15 ;   Enable Channel-to-Channel Linking
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LINKCH		cffield		TCD{__NS}_CITER,9,4 ;   Link Channel Number
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TCD{__NS}_DOFF	equ		TCD{__NS}+22	;  Signed Destination Address Offset (16b)
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TCD{__NS}_DLAST_SGA	equ	TCD{__NS}+24	;  Last Destination Address Adjustment/Scatter Gather Address (32b)
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TCD{__NS}_BITER	equ		TCD{__NS}+28	;  Beginning Minor Loop Link, Major Loop Count (16b)
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E_LINK		cfbit		TCD{__NS}_BITER,15 ;   Enables Channel-to-Channel Linking
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LINKCH		cffield		TCD{__NS}_BITER,9,4 ;   Link Channel Number
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TCD{__NS}_CSR	equ		TCD{__NS}+30	;  Control and Status (16b)
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BWC		cffield		TCD{__NS}_CSR,14,2 ;   Bandwidth Control
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MAJOR_LINKCH	cffield		TCD{__NS}_CSR,8,4 ;   Link Channel Number
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DONE		cfbit		TCD{__NS}_CSR,7 ;   Channel Done
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ACTIVE		cfbit		TCD{__NS}_CSR,6 ;   Channel Active
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MAJOR_E_LINK	cfbit		TCD{__NS}_CSR,5 ;   Enable Channel-to-Channel Linking
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E_SG		cfbit		TCD{__NS}_CSR,4 ;   Enable Scatter/Gather Processing
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D_REQ		cfbit		TCD{__NS}_CSR,3 ;   Disable Request
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INT_HALF	cfbit		TCD{__NS}_CSR,2 ;   Enable an interrupt when major counter is half complete
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INT_MAJOR	cfbit		TCD{__NS}_CSR,1 ;   Enable an interrupt when major iteration count completes
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START		cfbit		TCD{__NS}_CSR,0 ;   Channel Start
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__N		set		__N+1
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		endm
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		restore				; re-enable listing
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                endif                           ; __52xxedmainc