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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1186 | savelij | 1 | /* code68.c */ |
| 2 | /*****************************************************************************/ |
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| 3 | /* SPDX-License-Identifier: GPL-2.0-only OR GPL-3.0-only */ |
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| 4 | /* */ |
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| 5 | /* AS-Portierung */ |
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| 6 | /* */ |
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| 7 | /* Codegenerator fuer 68xx Prozessoren */ |
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| 8 | /* */ |
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| 9 | /*****************************************************************************/ |
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| 10 | |||
| 11 | #include "stdinc.h" |
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| 12 | #include <string.h> |
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| 13 | #include <ctype.h> |
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| 14 | |||
| 15 | #include "bpemu.h" |
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| 16 | #include "strutil.h" |
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| 17 | #include "asmdef.h" |
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| 18 | #include "asmpars.h" |
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| 19 | #include "asmallg.h" |
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| 20 | #include "asmsub.h" |
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| 21 | #include "errmsg.h" |
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| 22 | #include "codepseudo.h" |
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| 23 | #include "motpseudo.h" |
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| 24 | #include "intpseudo.h" |
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| 25 | #include "asmitree.h" |
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| 26 | #include "codevars.h" |
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| 27 | #include "cpu2phys.h" |
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| 28 | #include "function.h" |
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| 29 | #include "nlmessages.h" |
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| 30 | #include "as.rsc" |
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| 31 | |||
| 32 | #include "code68.h" |
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| 33 | |||
| 34 | /*---------------------------------------------------------------------------*/ |
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| 35 | |||
| 36 | typedef struct |
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| 37 | { |
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| 38 | CPUVar MinCPU, MaxCPU; |
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| 39 | Word Code; |
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| 40 | } FixedOrder; |
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| 41 | |||
| 42 | typedef struct |
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| 43 | { |
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| 44 | CPUVar MinCPU; |
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| 45 | Word Code; |
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| 46 | } RelOrder; |
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| 47 | |||
| 48 | typedef struct |
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| 49 | { |
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| 50 | Boolean MayImm; |
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| 51 | CPUVar MinCPU; /* Shift andere ,Y */ |
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| 52 | Byte PageShift; /* 0 : nix Pg 2 */ |
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| 53 | Byte Code; /* 1 : Pg 3 Pg 4 */ |
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| 54 | } ALU16Order; /* 2 : nix Pg 4 */ |
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| 55 | /* 3 : Pg 2 Pg 3 */ |
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| 56 | |||
| 57 | enum |
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| 58 | { |
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| 59 | ModNone = -1, |
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| 60 | ModAcc = 0, |
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| 61 | ModDir = 1, |
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| 62 | ModExt = 2, |
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| 63 | ModInd = 3, |
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| 64 | ModImm = 4 |
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| 65 | }; |
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| 66 | |||
| 67 | #define MModAcc (1 << ModAcc) |
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| 68 | #define MModDir (1 << ModDir) |
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| 69 | #define MModExt (1 << ModExt) |
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| 70 | #define MModInd (1 << ModInd) |
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| 71 | #define MModImm (1 << ModImm) |
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| 72 | |||
| 73 | #define Page2Prefix 0x18 |
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| 74 | #define Page3Prefix 0x1a |
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| 75 | #define Page4Prefix 0xcd |
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| 76 | |||
| 77 | |||
| 78 | static Byte PrefCnt; /* Anzahl Befehlspraefixe */ |
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| 79 | static ShortInt AdrMode; /* Ergebnisadressmodus */ |
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| 80 | static Byte AdrPart; /* Adressierungsmodusbits im Opcode */ |
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| 81 | static Byte AdrVals[4]; /* Adressargument */ |
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| 82 | |||
| 83 | static FixedOrder *FixedOrders; |
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| 84 | static RelOrder *RelOrders; |
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| 85 | static ALU16Order *ALU16Orders; |
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| 86 | |||
| 87 | static LongInt Reg_MMSIZ, Reg_MMWBR, Reg_MM1CR, Reg_MM2CR, Reg_INIT, Reg_INIT2, Reg_CONFIG; |
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| 88 | |||
| 89 | static CPUVar CPU6800, CPU6801, CPU6301, CPU6811, CPU68HC11K4; |
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| 90 | |||
| 91 | /*---------------------------------------------------------------------------*/ |
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| 92 | |||
| 93 | /*!------------------------------------------------------------------------ |
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| 94 | * \fn compute_window(Byte w_size_code, Byte cpu_start_code, LongInt phys_start_code, LongWord phys_offset) |
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| 95 | * \brief compute single window from MMU registers |
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| 96 | * \param w_size_code MMSIZ bits (0..3) |
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| 97 | * \param cpu_start_code Reg_MMWBR bits (0,2,4,6...14) |
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| 98 | * \param phys_start_code Reg_MMxCR bits |
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| 99 | * \param phys_offset offset in physical space |
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| 100 | * ------------------------------------------------------------------------ */ |
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| 101 | |||
| 102 | static void compute_window(Byte w_size_code, Byte cpu_start_code, LongInt phys_start_code, LongWord phys_offset) |
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| 103 | { |
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| 104 | if (w_size_code) |
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| 105 | { |
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| 106 | Word size, cpu_start; |
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| 107 | LongWord phys_start; |
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| 108 | |||
| 109 | /* window size */ |
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| 110 | |||
| 111 | size = 0x1000 << w_size_code; |
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| 112 | |||
| 113 | /* CPU space start address: assume 8K window, systematically clip out bits for |
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| 114 | larger windows */ |
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| 115 | |||
| 116 | cpu_start = (Word)cpu_start_code << 12; |
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| 117 | if (w_size_code > 1) |
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| 118 | cpu_start &= ~0x2000; |
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| 119 | if (w_size_code > 2) |
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| 120 | cpu_start = (cpu_start == 0xc000) ? 0x8000 : cpu_start; |
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| 121 | |||
| 122 | /* physical space start: mask out lower bits according to window size */ |
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| 123 | |||
| 124 | phys_start = ((phys_start_code & 0x7f & (~((1 << w_size_code) - 1))) << 12) + phys_offset; |
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| 125 | |||
| 126 | /* set addresses */ |
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| 127 | |||
| 128 | cpu_2_phys_area_add(SegCode, cpu_start, phys_start, size); |
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| 129 | } |
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| 130 | } |
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| 131 | |||
| 132 | static void SetK4Ranges(void) |
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| 133 | { |
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| 134 | Word ee_bank, io_bank, ram_bank; |
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| 135 | |||
| 136 | cpu_2_phys_area_clear(SegCode); |
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| 137 | |||
| 138 | /* Add window 1 after window 2, since it has higher priority and may partially overlap window 2 */ |
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| 139 | |||
| 140 | compute_window((Reg_MMSIZ >> 4) & 0x3, (Reg_MMWBR >> 4) & 0x0e, Reg_MM2CR, 0x90000); |
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| 141 | compute_window(Reg_MMSIZ & 0x3, Reg_MMWBR & 0x0e, Reg_MM1CR, 0x10000); |
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| 142 | |||
| 143 | /* Internal registers, RAM and EEPROM (if enabled) have priority in CPU address space: */ |
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| 144 | |||
| 145 | if (Reg_CONFIG & 1) |
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| 146 | { |
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| 147 | ee_bank = ((Reg_INIT & 15) << 12) + 0x0d80; |
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| 148 | cpu_2_phys_area_add(SegCode, ee_bank, ee_bank, 640); |
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| 149 | } |
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| 150 | |||
| 151 | io_bank = (Reg_INIT & 15) << 12; |
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| 152 | cpu_2_phys_area_add(SegCode, io_bank, io_bank, 128); |
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| 153 | |||
| 154 | /* If RAM position overlaps registers, 128 bytes of RAM get relocated to upper end: */ |
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| 155 | |||
| 156 | ram_bank = ((Reg_INIT >> 4) & 15) << 12; |
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| 157 | if (ram_bank == io_bank) |
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| 158 | ram_bank += 128; |
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| 159 | cpu_2_phys_area_add(SegCode, ram_bank, ram_bank, 768); |
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| 160 | |||
| 161 | /* Fill the remainder of CPU address space with 1:1 mappings: */ |
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| 162 | |||
| 163 | cpu_2_phys_area_fill(SegCode, 0x0000, 0xffff); |
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| 164 | } |
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| 165 | |||
| 166 | /*---------------------------------------------------------------------------*/ |
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| 167 | |||
| 168 | static Boolean DecodeAcc(const char *pArg, Byte *pReg) |
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| 169 | { |
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| 170 | static const char Regs[] = "AB"; |
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| 171 | |||
| 172 | if (strlen(pArg) == 1) |
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| 173 | { |
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| 174 | const char *pPos = strchr(Regs, as_toupper(*pArg)); |
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| 175 | |||
| 176 | if (pPos) |
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| 177 | { |
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| 178 | *pReg = pPos - Regs; |
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| 179 | return True; |
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| 180 | } |
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| 181 | } |
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| 182 | return False; |
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| 183 | } |
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| 184 | |||
| 185 | static void DecodeAdr(int StartInd, int StopInd, tSymbolSize op_size, Byte Erl) |
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| 186 | { |
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| 187 | tStrComp *pStartArg = &ArgStr[StartInd]; |
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| 188 | Boolean OK, ErrOcc; |
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| 189 | tSymbolFlags Flags; |
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| 190 | Word AdrWord; |
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| 191 | Byte Bit8; |
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| 192 | |||
| 193 | AdrMode = ModNone; |
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| 194 | AdrPart = 0; |
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| 195 | ErrOcc = False; |
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| 196 | |||
| 197 | /* eine Komponente ? */ |
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| 198 | |||
| 199 | if (StartInd == StopInd) |
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| 200 | { |
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| 201 | /* Akkumulatoren ? */ |
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| 202 | |||
| 203 | if (DecodeAcc(pStartArg->str.p_str, &AdrPart)) |
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| 204 | { |
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| 205 | if (MModAcc & Erl) |
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| 206 | AdrMode = ModAcc; |
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| 207 | } |
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| 208 | |||
| 209 | /* immediate ? */ |
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| 210 | |||
| 211 | else if ((strlen(pStartArg->str.p_str) > 1) && (*pStartArg->str.p_str == '#')) |
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| 212 | { |
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| 213 | if (MModImm & Erl) |
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| 214 | { |
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| 215 | if (op_size == eSymbolSize16Bit) |
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| 216 | { |
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| 217 | AdrWord = EvalStrIntExpressionOffs(pStartArg, 1, Int16, &OK); |
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| 218 | if (OK) |
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| 219 | { |
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| 220 | AdrMode = ModImm; |
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| 221 | AdrVals[AdrCnt++] = Hi(AdrWord); |
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| 222 | AdrVals[AdrCnt++] = Lo(AdrWord); |
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| 223 | } |
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| 224 | else |
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| 225 | ErrOcc = True; |
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| 226 | } |
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| 227 | else |
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| 228 | { |
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| 229 | AdrVals[AdrCnt] = EvalStrIntExpressionOffs(pStartArg, 1, Int8, &OK); |
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| 230 | if (OK) |
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| 231 | { |
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| 232 | AdrMode = ModImm; |
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| 233 | AdrCnt++; |
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| 234 | } |
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| 235 | else |
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| 236 | ErrOcc = True; |
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| 237 | } |
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| 238 | } |
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| 239 | } |
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| 240 | |||
| 241 | /* absolut ? */ |
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| 242 | |||
| 243 | else |
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| 244 | { |
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| 245 | unsigned Offset = 0; |
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| 246 | |||
| 247 | Bit8 = 0; |
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| 248 | if (pStartArg->str.p_str[Offset] == '<') |
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| 249 | { |
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| 250 | Bit8 = 2; |
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| 251 | Offset++; |
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| 252 | } |
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| 253 | else if (pStartArg->str.p_str[Offset] == '>') |
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| 254 | { |
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| 255 | Bit8 = 1; |
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| 256 | Offset++; |
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| 257 | } |
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| 258 | if (MomCPU == CPU68HC11K4) |
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| 259 | { |
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| 260 | LargeWord AdrLWord = EvalStrIntExpressionOffsWithFlags(pStartArg, Offset, UInt21, &OK, &Flags); |
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| 261 | if (OK) |
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| 262 | { |
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| 263 | if (!def_phys_2_cpu(SegCode, &AdrLWord)) |
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| 264 | { |
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| 265 | WrError(ErrNum_InAccPage); |
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| 266 | AdrWord = AdrLWord & 0xffffu; |
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| 267 | } |
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| 268 | else |
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| 269 | AdrWord = AdrLWord; |
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| 270 | } |
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| 271 | else |
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| 272 | AdrWord = 0; |
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| 273 | } |
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| 274 | else |
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| 275 | AdrWord = EvalStrIntExpressionOffsWithFlags(pStartArg, Offset, UInt16, &OK, &Flags); |
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| 276 | if (OK) |
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| 277 | { |
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| 278 | if ((MModDir & Erl) && (Bit8 != 1) && ((Bit8 == 2) || (!(MModExt & Erl)) || (Hi(AdrWord) == 0))) |
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| 279 | { |
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| 280 | if ((Hi(AdrWord) != 0) && !mFirstPassUnknown(Flags)) |
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| 281 | { |
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| 282 | WrError(ErrNum_NoShortAddr); |
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| 283 | ErrOcc = True; |
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| 284 | } |
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| 285 | else |
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| 286 | { |
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| 287 | AdrMode = ModDir; |
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| 288 | AdrPart = 1; |
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| 289 | AdrVals[AdrCnt++] = Lo(AdrWord); |
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| 290 | } |
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| 291 | } |
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| 292 | else if ((MModExt & Erl)!=0) |
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| 293 | { |
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| 294 | AdrMode = ModExt; |
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| 295 | AdrPart = 3; |
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| 296 | AdrVals[AdrCnt++] = Hi(AdrWord); |
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| 297 | AdrVals[AdrCnt++] = Lo(AdrWord); |
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| 298 | } |
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| 299 | } |
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| 300 | else |
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| 301 | ErrOcc = True; |
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| 302 | } |
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| 303 | } |
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| 304 | |||
| 305 | /* zwei Komponenten ? */ |
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| 306 | |||
| 307 | else if (StartInd + 1 == StopInd) |
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| 308 | { |
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| 309 | Boolean IsX = !as_strcasecmp(ArgStr[StopInd].str.p_str, "X"), |
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| 310 | IsY = !as_strcasecmp(ArgStr[StopInd].str.p_str, "Y"); |
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| 311 | |||
| 312 | /* indiziert ? */ |
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| 313 | |||
| 314 | if (IsX || IsY) |
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| 315 | { |
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| 316 | if (MModInd & Erl) |
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| 317 | { |
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| 318 | if (pStartArg->str.p_str[0]) |
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| 319 | AdrWord = EvalStrIntExpression(pStartArg, UInt8, &OK); |
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| 320 | else |
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| 321 | { |
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| 322 | AdrWord = 0; |
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| 323 | OK = True; |
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| 324 | } |
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| 325 | if (OK) |
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| 326 | { |
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| 327 | if (IsY && !ChkMinCPUExt(CPU6811, ErrNum_AddrModeNotSupported)) |
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| 328 | ErrOcc = True; |
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| 329 | else |
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| 330 | { |
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| 331 | AdrVals[AdrCnt++] = Lo(AdrWord); |
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| 332 | AdrMode = ModInd; |
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| 333 | AdrPart = 2; |
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| 334 | if (IsY) |
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| 335 | { |
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| 336 | BAsmCode[PrefCnt++] = 0x18; |
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| 337 | } |
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| 338 | } |
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| 339 | } |
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| 340 | else |
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| 341 | ErrOcc = True; |
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| 342 | } |
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| 343 | } |
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| 344 | else |
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| 345 | { |
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| 346 | WrStrErrorPos(ErrNum_InvReg, &ArgStr[StopInd]); |
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| 347 | ErrOcc = True; |
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| 348 | } |
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| 349 | } |
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| 350 | |||
| 351 | else |
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| 352 | { |
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| 353 | char Str[100]; |
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| 354 | |||
| 355 | as_snprintf(Str, sizeof(Str), getmessage(Num_ErrMsgAddrArgCnt), 1, 2, StopInd - StartInd + 1); |
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| 356 | WrXError(ErrNum_WrongArgCnt, Str); |
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| 357 | ErrOcc = True; |
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| 358 | } |
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| 359 | |||
| 360 | if ((!ErrOcc) && (AdrMode == ModNone)) |
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| 361 | WrError(ErrNum_InvAddrMode); |
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| 362 | } |
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| 363 | |||
| 364 | static void AddPrefix(Byte Prefix) |
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| 365 | { |
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| 366 | BAsmCode[PrefCnt++] = Prefix; |
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| 367 | } |
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| 368 | |||
| 369 | static void Try2Split(int Src) |
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| 370 | { |
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| 371 | char *p; |
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| 372 | size_t SrcLen; |
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| 373 | |||
| 374 | KillPrefBlanksStrComp(&ArgStr[Src]); |
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| 375 | KillPostBlanksStrComp(&ArgStr[Src]); |
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| 376 | SrcLen = strlen(ArgStr[Src].str.p_str); |
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| 377 | p = ArgStr[Src].str.p_str + SrcLen - 1; |
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| 378 | while ((p > ArgStr[Src].str.p_str) && !as_isspace(*p)) |
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| 379 | p--; |
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| 380 | if (p > ArgStr[Src].str.p_str) |
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| 381 | { |
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| 382 | InsertArg(Src + 1, SrcLen); |
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| 383 | StrCompSplitRight(&ArgStr[Src], &ArgStr[Src + 1], p); |
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| 384 | KillPostBlanksStrComp(&ArgStr[Src]); |
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| 385 | KillPrefBlanksStrComp(&ArgStr[Src + 1]); |
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| 386 | } |
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| 387 | } |
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| 388 | |||
| 389 | /*---------------------------------------------------------------------------*/ |
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| 390 | |||
| 391 | static void DecodeFixed(Word Index) |
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| 392 | { |
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| 393 | const FixedOrder *forder = FixedOrders + Index; |
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| 394 | |||
| 395 | if (!ChkArgCnt(0, 0)); |
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| 396 | else if (!ChkRangeCPU(forder->MinCPU, forder->MaxCPU)); |
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| 397 | else if (Hi(forder->Code) != 0) |
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| 398 | { |
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| 399 | CodeLen = 2; |
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| 400 | BAsmCode[0] = Hi(forder->Code); |
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| 401 | BAsmCode[1] = Lo(forder->Code); |
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| 402 | } |
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| 403 | else |
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| 404 | { |
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| 405 | CodeLen = 1; |
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| 406 | BAsmCode[0] = Lo(forder->Code); |
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| 407 | } |
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| 408 | } |
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| 409 | |||
| 410 | static void DecodeRel(Word Index) |
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| 411 | { |
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| 412 | const RelOrder *pOrder = &RelOrders[Index]; |
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| 413 | Integer AdrInt; |
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| 414 | Boolean OK; |
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| 415 | tSymbolFlags Flags; |
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| 416 | |||
| 417 | if (ChkArgCnt(1, 1) |
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| 418 | && ChkMinCPU(pOrder->MinCPU)) |
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| 419 | { |
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| 420 | AdrInt = EvalStrIntExpressionWithFlags(&ArgStr[1], Int16, &OK, &Flags); |
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| 421 | if (OK) |
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| 422 | { |
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| 423 | AdrInt -= EProgCounter() + 2; |
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| 424 | if (((AdrInt < -128) || (AdrInt > 127)) && !mSymbolQuestionable(Flags)) WrError(ErrNum_JmpDistTooBig); |
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| 425 | else |
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| 426 | { |
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| 427 | CodeLen = 2; |
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| 428 | BAsmCode[0] = pOrder->Code; |
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| 429 | BAsmCode[1] = Lo(AdrInt); |
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| 430 | } |
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| 431 | } |
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| 432 | } |
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| 433 | } |
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| 434 | |||
| 435 | static void DecodeALU16(Word Index) |
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| 436 | { |
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| 437 | const ALU16Order *forder = ALU16Orders + Index; |
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| 438 | |||
| 439 | if (ChkArgCnt(1, 2) |
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| 440 | && ChkMinCPU(forder->MinCPU)) |
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| 441 | { |
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| 442 | DecodeAdr(1, ArgCnt, eSymbolSize16Bit, (forder->MayImm ? MModImm : 0) | MModInd | MModExt | MModDir); |
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| 443 | if (AdrMode != ModNone) |
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| 444 | { |
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| 445 | switch (forder->PageShift) |
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| 446 | { |
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| 447 | case 1: |
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| 448 | if (PrefCnt == 1) |
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| 449 | BAsmCode[PrefCnt - 1] = Page4Prefix; |
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| 450 | else |
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| 451 | AddPrefix(Page3Prefix); |
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| 452 | break; |
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| 453 | case 2: |
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| 454 | if (PrefCnt == 1) |
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| 455 | BAsmCode[PrefCnt - 1] = Page4Prefix; |
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| 456 | break; |
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| 457 | case 3: |
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| 458 | if (PrefCnt == 0) |
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| 459 | AddPrefix((AdrMode == ModInd) ? Page3Prefix : Page2Prefix); |
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| 460 | break; |
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| 461 | } |
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| 462 | BAsmCode[PrefCnt] = forder->Code + (AdrPart << 4); |
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| 463 | CodeLen = PrefCnt + 1 + AdrCnt; |
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| 464 | memcpy(BAsmCode + 1 + PrefCnt, AdrVals, AdrCnt); |
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| 465 | } |
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| 466 | } |
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| 467 | } |
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| 468 | |||
| 469 | static void DecodeBit63(Word Code) |
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| 470 | { |
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| 471 | if (ChkArgCnt(2, 3) |
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| 472 | && ChkExactCPU(CPU6301)) |
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| 473 | { |
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| 474 | DecodeAdr(1, 1, eSymbolSize8Bit, MModImm); |
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| 475 | if (AdrMode != ModNone) |
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| 476 | { |
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| 477 | DecodeAdr(2, ArgCnt, eSymbolSizeUnknown, MModDir | MModInd); |
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| 478 | if (AdrMode != ModNone) |
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| 479 | { |
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| 480 | BAsmCode[PrefCnt] = Code; |
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| 481 | if (AdrMode == ModDir) |
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| 482 | BAsmCode[PrefCnt] |= 0x10; |
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| 483 | CodeLen = PrefCnt + 1 + AdrCnt; |
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| 484 | memcpy(BAsmCode + 1 + PrefCnt, AdrVals, AdrCnt); |
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| 485 | } |
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| 486 | } |
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| 487 | } |
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| 488 | } |
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| 489 | |||
| 490 | static void DecodeJMP(Word Index) |
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| 491 | { |
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| 492 | UNUSED(Index); |
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| 493 | |||
| 494 | if (ChkArgCnt(1, 2)) |
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| 495 | { |
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| 496 | DecodeAdr(1, ArgCnt, eSymbolSizeUnknown, MModExt | MModInd); |
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| 497 | if (AdrMode != ModImm) |
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| 498 | { |
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| 499 | CodeLen = PrefCnt + 1 + AdrCnt; |
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| 500 | BAsmCode[PrefCnt] = 0x4e + (AdrPart << 4); |
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| 501 | memcpy(BAsmCode + 1 + PrefCnt, AdrVals, AdrCnt); |
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| 502 | } |
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| 503 | } |
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| 504 | } |
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| 505 | |||
| 506 | static void DecodeJSR(Word Index) |
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| 507 | { |
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| 508 | UNUSED(Index); |
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| 509 | |||
| 510 | if (ChkArgCnt(1, 2)) |
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| 511 | { |
||
| 512 | DecodeAdr(1, ArgCnt, eSymbolSizeUnknown, MModExt | MModInd | ((MomCPU >= CPU6801) ? MModDir : 0)); |
||
| 513 | if (AdrMode != ModImm) |
||
| 514 | { |
||
| 515 | CodeLen=PrefCnt + 1 + AdrCnt; |
||
| 516 | BAsmCode[PrefCnt] = 0x8d + (AdrPart << 4); |
||
| 517 | memcpy(BAsmCode + 1 + PrefCnt, AdrVals, AdrCnt); |
||
| 518 | } |
||
| 519 | } |
||
| 520 | } |
||
| 521 | |||
| 522 | static void DecodeBRxx(Word Index) |
||
| 523 | { |
||
| 524 | Boolean OK; |
||
| 525 | Byte Mask; |
||
| 526 | Integer AdrInt; |
||
| 527 | |||
| 528 | if (ArgCnt == 1) |
||
| 529 | { |
||
| 530 | Try2Split(1); |
||
| 531 | Try2Split(1); |
||
| 532 | } |
||
| 533 | else if (ArgCnt == 2) |
||
| 534 | { |
||
| 535 | Try2Split(ArgCnt); |
||
| 536 | Try2Split(2); |
||
| 537 | } |
||
| 538 | if (ChkArgCnt(3, 4) |
||
| 539 | && ChkMinCPU(CPU6811)) |
||
| 540 | { |
||
| 541 | Mask = EvalStrIntExpressionOffs(&ArgStr[ArgCnt - 1], !!(*ArgStr[ArgCnt - 1].str.p_str == '#'), Int8, &OK); |
||
| 542 | if (OK) |
||
| 543 | { |
||
| 544 | DecodeAdr(1, ArgCnt - 2, eSymbolSizeUnknown, MModDir | MModInd); |
||
| 545 | if (AdrMode != ModNone) |
||
| 546 | { |
||
| 547 | AdrInt = EvalStrIntExpression(&ArgStr[ArgCnt], Int16, &OK); |
||
| 548 | if (OK) |
||
| 549 | { |
||
| 550 | AdrInt -= EProgCounter() + 3 + PrefCnt + AdrCnt; |
||
| 551 | if ((AdrInt < -128) || (AdrInt > 127)) WrError(ErrNum_JmpDistTooBig); |
||
| 552 | else |
||
| 553 | { |
||
| 554 | CodeLen = PrefCnt + 3 + AdrCnt; |
||
| 555 | BAsmCode[PrefCnt] = 0x12 + Index; |
||
| 556 | if (AdrMode == ModInd) |
||
| 557 | BAsmCode[PrefCnt] += 12; |
||
| 558 | memcpy(BAsmCode + PrefCnt + 1, AdrVals, AdrCnt); |
||
| 559 | BAsmCode[PrefCnt + 1 + AdrCnt] = Mask; |
||
| 560 | BAsmCode[PrefCnt + 2 + AdrCnt] = Lo(AdrInt); |
||
| 561 | } |
||
| 562 | } |
||
| 563 | } |
||
| 564 | } |
||
| 565 | } |
||
| 566 | } |
||
| 567 | |||
| 568 | static void DecodeBxx(Word Index) |
||
| 569 | { |
||
| 570 | Byte Mask; |
||
| 571 | Boolean OK; |
||
| 572 | int AddrStart, AddrEnd; |
||
| 573 | tStrComp *pMaskArg; |
||
| 574 | |||
| 575 | if (MomCPU == CPU6301) |
||
| 576 | { |
||
| 577 | pMaskArg = &ArgStr[1]; |
||
| 578 | AddrStart = 2; |
||
| 579 | AddrEnd = ArgCnt; |
||
| 580 | } |
||
| 581 | else |
||
| 582 | { |
||
| 583 | if ((ArgCnt >= 1) && (ArgCnt <= 2)) Try2Split(ArgCnt); |
||
| 584 | pMaskArg = &ArgStr[ArgCnt]; |
||
| 585 | AddrStart = 1; |
||
| 586 | AddrEnd = ArgCnt - 1; |
||
| 587 | } |
||
| 588 | if (ChkArgCnt(2, 3) |
||
| 589 | && ChkMinCPU(CPU6301)) |
||
| 590 | { |
||
| 591 | Mask = EvalStrIntExpressionOffs(pMaskArg, !!(*pMaskArg->str.p_str == '#'), |
||
| 592 | (MomCPU == CPU6301) ? UInt3 : Int8, &OK); |
||
| 593 | if (OK && (MomCPU == CPU6301)) |
||
| 594 | { |
||
| 595 | Mask = 1 << Mask; |
||
| 596 | if (Index == 1) Mask = 0xff - Mask; |
||
| 597 | } |
||
| 598 | if (OK) |
||
| 599 | { |
||
| 600 | DecodeAdr(AddrStart, AddrEnd, eSymbolSizeUnknown, MModDir | MModInd); |
||
| 601 | if (AdrMode != ModNone) |
||
| 602 | { |
||
| 603 | CodeLen = PrefCnt + 2 + AdrCnt; |
||
| 604 | if (MomCPU == CPU6301) |
||
| 605 | { |
||
| 606 | BAsmCode[PrefCnt] = 0x62 - Index; |
||
| 607 | if (AdrMode == ModDir) |
||
| 608 | BAsmCode[PrefCnt] += 0x10; |
||
| 609 | BAsmCode[1 + PrefCnt] = Mask; |
||
| 610 | memcpy(BAsmCode + 2 + PrefCnt, AdrVals, AdrCnt); |
||
| 611 | } |
||
| 612 | else |
||
| 613 | { |
||
| 614 | BAsmCode[PrefCnt] = 0x14 + Index; |
||
| 615 | if (AdrMode == ModInd) |
||
| 616 | BAsmCode[PrefCnt] += 8; |
||
| 617 | memcpy(BAsmCode + 1 + PrefCnt, AdrVals, AdrCnt); |
||
| 618 | BAsmCode[1 + PrefCnt + AdrCnt] = Mask; |
||
| 619 | } |
||
| 620 | } |
||
| 621 | } |
||
| 622 | } |
||
| 623 | } |
||
| 624 | |||
| 625 | static void DecodeBTxx(Word Index) |
||
| 626 | { |
||
| 627 | Boolean OK; |
||
| 628 | Byte AdrByte; |
||
| 629 | |||
| 630 | if (ChkArgCnt(2, 3) |
||
| 631 | && ChkExactCPU(CPU6301)) |
||
| 632 | { |
||
| 633 | AdrByte = EvalStrIntExpressionOffs(&ArgStr[1], !!(*ArgStr[1].str.p_str == '#'), UInt3, &OK); |
||
| 634 | if (OK) |
||
| 635 | { |
||
| 636 | DecodeAdr(2, ArgCnt, eSymbolSizeUnknown, MModDir | MModInd); |
||
| 637 | if (AdrMode != ModNone) |
||
| 638 | { |
||
| 639 | CodeLen = PrefCnt + 2 + AdrCnt; |
||
| 640 | BAsmCode[1 + PrefCnt] = 1 << AdrByte; |
||
| 641 | memcpy(BAsmCode + 2 + PrefCnt, AdrVals, AdrCnt); |
||
| 642 | BAsmCode[PrefCnt] = 0x65 + Index; |
||
| 643 | if (AdrMode == ModDir) |
||
| 644 | BAsmCode[PrefCnt] += 0x10; |
||
| 645 | } |
||
| 646 | } |
||
| 647 | } |
||
| 648 | } |
||
| 649 | |||
| 650 | static void DecodeALU8(Word Code) |
||
| 651 | { |
||
| 652 | Byte Reg; |
||
| 653 | int MinArgCnt = Hi(Code) & 3; |
||
| 654 | |||
| 655 | /* dirty hack: LDA/STA/ORA, and first arg is not A or B, treat like LDAA/STAA/ORAA: */ |
||
| 656 | |||
| 657 | if ((MinArgCnt == 2) |
||
| 658 | && (as_toupper(OpPart.str.p_str[2]) == 'A') |
||
| 659 | && (ArgCnt >= 1) |
||
| 660 | && !DecodeAcc(ArgStr[1].str.p_str, &Reg)) |
||
| 661 | MinArgCnt = 1; |
||
| 662 | |||
| 663 | if (ChkArgCnt(MinArgCnt, MinArgCnt + 1)) |
||
| 664 | { |
||
| 665 | DecodeAdr(MinArgCnt, ArgCnt, eSymbolSize8Bit, ((Code & 0x8000) ? MModImm : 0) | MModInd | MModExt | MModDir); |
||
| 666 | if (AdrMode != ModNone) |
||
| 667 | { |
||
| 668 | BAsmCode[PrefCnt] = Lo(Code) | (AdrPart << 4); |
||
| 669 | if (MinArgCnt == 1) |
||
| 670 | { |
||
| 671 | AdrMode = ModAcc; |
||
| 672 | AdrPart = (Code & 0x4000) >> 14; |
||
| 673 | } |
||
| 674 | else |
||
| 675 | DecodeAdr(1, 1, eSymbolSizeUnknown, MModAcc); |
||
| 676 | if (AdrMode != ModNone) |
||
| 677 | { |
||
| 678 | BAsmCode[PrefCnt] |= AdrPart << 6; |
||
| 679 | CodeLen = PrefCnt + 1 + AdrCnt; |
||
| 680 | memcpy(BAsmCode + 1 + PrefCnt, AdrVals, AdrCnt); |
||
| 681 | } |
||
| 682 | } |
||
| 683 | } |
||
| 684 | } |
||
| 685 | |||
| 686 | static void DecodeSing8(Word Code) |
||
| 687 | { |
||
| 688 | if (ChkArgCnt(1, 2)) |
||
| 689 | { |
||
| 690 | DecodeAdr(1, ArgCnt, eSymbolSizeUnknown, MModAcc | MModExt | MModInd); |
||
| 691 | if (AdrMode != ModNone) |
||
| 692 | { |
||
| 693 | CodeLen = PrefCnt + 1 + AdrCnt; |
||
| 694 | BAsmCode[PrefCnt] = Code | (AdrPart << 4); |
||
| 695 | memcpy(BAsmCode + 1 + PrefCnt, AdrVals, AdrCnt); |
||
| 696 | } |
||
| 697 | } |
||
| 698 | } |
||
| 699 | |||
| 700 | static void DecodeSing8_Acc(Word Code) |
||
| 701 | { |
||
| 702 | if (ChkArgCnt(0, 0)) |
||
| 703 | { |
||
| 704 | BAsmCode[PrefCnt] = Code; |
||
| 705 | CodeLen = PrefCnt + 1; |
||
| 706 | } |
||
| 707 | } |
||
| 708 | |||
| 709 | static void DecodePSH_PUL(Word Code) |
||
| 710 | { |
||
| 711 | if (ChkArgCnt(1, 1)) |
||
| 712 | { |
||
| 713 | DecodeAdr(1, 1, eSymbolSizeUnknown, MModAcc); |
||
| 714 | if (AdrMode != ModNone) |
||
| 715 | { |
||
| 716 | CodeLen = 1; |
||
| 717 | BAsmCode[0] = Code | AdrPart; |
||
| 718 | } |
||
| 719 | } |
||
| 720 | } |
||
| 721 | |||
| 722 | static void DecodePRWINS(Word Code) |
||
| 723 | { |
||
| 724 | UNUSED(Code); |
||
| 725 | |||
| 726 | if (ChkExactCPU(CPU68HC11K4)) |
||
| 727 | { |
||
| 728 | printf("\nMMSIZ $%02x MMWBR $%02x MM1CR $%02x MM2CR $%02x INIT $%02x INIT2 $%02x CONFIG $%02x\n", |
||
| 729 | (unsigned)Reg_MMSIZ, (unsigned)Reg_MMWBR, (unsigned)Reg_MM1CR, (unsigned)Reg_MM2CR, |
||
| 730 | (unsigned)Reg_INIT, (unsigned)Reg_INIT2, (unsigned)Reg_CONFIG); |
||
| 731 | cpu_2_phys_area_dump(SegCode, stdout); |
||
| 732 | } |
||
| 733 | } |
||
| 734 | |||
| 735 | /*---------------------------------------------------------------------------*/ |
||
| 736 | |||
| 737 | static void AddFixed(const char *NName, CPUVar NMin, CPUVar NMax, Word NCode) |
||
| 738 | { |
||
| 739 | order_array_rsv_end(FixedOrders, FixedOrder); |
||
| 740 | FixedOrders[InstrZ].MinCPU = NMin; |
||
| 741 | FixedOrders[InstrZ].MaxCPU = NMax; |
||
| 742 | FixedOrders[InstrZ].Code = NCode; |
||
| 743 | AddInstTable(InstTable, NName, InstrZ++, DecodeFixed); |
||
| 744 | } |
||
| 745 | |||
| 746 | static void AddRel(const char *NName, CPUVar NMin, Word NCode) |
||
| 747 | { |
||
| 748 | order_array_rsv_end(RelOrders, RelOrder); |
||
| 749 | RelOrders[InstrZ].MinCPU = NMin; |
||
| 750 | RelOrders[InstrZ].Code = NCode; |
||
| 751 | AddInstTable(InstTable, NName, InstrZ++, DecodeRel); |
||
| 752 | } |
||
| 753 | |||
| 754 | static void AddALU8(const char *NamePlain, const char *NameA, const char *NameB, const char *NameB2, Boolean MayImm, Byte NCode) |
||
| 755 | { |
||
| 756 | Word BaseCode = NCode | (MayImm ? 0x8000 : 0); |
||
| 757 | |||
| 758 | AddInstTable(InstTable, NamePlain, BaseCode | (2 << 8), DecodeALU8); |
||
| 759 | AddInstTable(InstTable, NameA, BaseCode | (1 << 8), DecodeALU8); |
||
| 760 | AddInstTable(InstTable, NameB, BaseCode | (1 << 8) | 0x4000, DecodeALU8); |
||
| 761 | if (NameB2) |
||
| 762 | AddInstTable(InstTable, NameB2, BaseCode | (1 << 8) | 0x4000, DecodeALU8); |
||
| 763 | } |
||
| 764 | |||
| 765 | static void AddALU16(const char *NName, Boolean NMay, CPUVar NMin, Byte NShift, Byte NCode) |
||
| 766 | { |
||
| 767 | order_array_rsv_end(ALU16Orders, ALU16Order); |
||
| 768 | ALU16Orders[InstrZ].MayImm = NMay; |
||
| 769 | ALU16Orders[InstrZ].MinCPU = NMin; |
||
| 770 | ALU16Orders[InstrZ].PageShift = NShift; |
||
| 771 | ALU16Orders[InstrZ].Code = NCode; |
||
| 772 | AddInstTable(InstTable, NName, InstrZ++, DecodeALU16); |
||
| 773 | } |
||
| 774 | |||
| 775 | static void AddSing8(const char *NamePlain, const char *NameA, const char *NameB, Byte NCode) |
||
| 776 | { |
||
| 777 | AddInstTable(InstTable, NamePlain, NCode, DecodeSing8); |
||
| 778 | AddInstTable(InstTable, NameA, NCode | 0, DecodeSing8_Acc); |
||
| 779 | AddInstTable(InstTable, NameB, NCode | 0x10, DecodeSing8_Acc); |
||
| 780 | } |
||
| 781 | |||
| 782 | static void InitFields(void) |
||
| 783 | { |
||
| 784 | InstTable = CreateInstTable(317); |
||
| 785 | |||
| 786 | add_null_pseudo(InstTable); |
||
| 787 | |||
| 788 | AddInstTable(InstTable, "JMP" , 0, DecodeJMP); |
||
| 789 | AddInstTable(InstTable, "JSR" , 0, DecodeJSR); |
||
| 790 | AddInstTable(InstTable, "BRCLR", 1, DecodeBRxx); |
||
| 791 | AddInstTable(InstTable, "BRSET", 0, DecodeBRxx); |
||
| 792 | AddInstTable(InstTable, "BCLR" , 1, DecodeBxx); |
||
| 793 | AddInstTable(InstTable, "BSET" , 0, DecodeBxx); |
||
| 794 | AddInstTable(InstTable, "BTST" , 6, DecodeBTxx); |
||
| 795 | AddInstTable(InstTable, "BTGL" , 0, DecodeBTxx); |
||
| 796 | |||
| 797 | InstrZ = 0; |
||
| 798 | AddFixed("ABA" ,CPU6800, CPU68HC11K4, 0x001b); AddFixed("ABX" ,CPU6801, CPU68HC11K4, 0x003a); |
||
| 799 | AddFixed("ABY" ,CPU6811, CPU68HC11K4, 0x183a); AddFixed("ASLD" ,CPU6801, CPU68HC11K4, 0x0005); |
||
| 800 | AddFixed("CBA" ,CPU6800, CPU68HC11K4, 0x0011); AddFixed("CLC" ,CPU6800, CPU68HC11K4, 0x000c); |
||
| 801 | AddFixed("CLI" ,CPU6800, CPU68HC11K4, 0x000e); AddFixed("CLV" ,CPU6800, CPU68HC11K4, 0x000a); |
||
| 802 | AddFixed("DAA" ,CPU6800, CPU68HC11K4, 0x0019); AddFixed("DES" ,CPU6800, CPU68HC11K4, 0x0034); |
||
| 803 | AddFixed("DEX" ,CPU6800, CPU68HC11K4, 0x0009); AddFixed("DEY" ,CPU6811, CPU68HC11K4, 0x1809); |
||
| 804 | AddFixed("FDIV" ,CPU6811, CPU68HC11K4, 0x0003); AddFixed("IDIV" ,CPU6811, CPU68HC11K4, 0x0002); |
||
| 805 | AddFixed("INS" ,CPU6800, CPU68HC11K4, 0x0031); AddFixed("INX" ,CPU6800, CPU68HC11K4, 0x0008); |
||
| 806 | AddFixed("INY" ,CPU6811, CPU68HC11K4, 0x1808); AddFixed("LSLD" ,CPU6801, CPU68HC11K4, 0x0005); |
||
| 807 | AddFixed("LSRD" ,CPU6801, CPU68HC11K4, 0x0004); AddFixed("MUL" ,CPU6801, CPU68HC11K4, 0x003d); |
||
| 808 | AddFixed("NOP" ,CPU6800, CPU68HC11K4, 0x0001); AddFixed("PSHX" ,CPU6801, CPU68HC11K4, 0x003c); |
||
| 809 | AddFixed("PSHY" ,CPU6811, CPU68HC11K4, 0x183c); AddFixed("PULX" ,CPU6801, CPU68HC11K4, 0x0038); |
||
| 810 | AddFixed("PULY" ,CPU6811, CPU68HC11K4, 0x1838); AddFixed("RTI" ,CPU6800, CPU68HC11K4, 0x003b); |
||
| 811 | AddFixed("RTS" ,CPU6800, CPU68HC11K4, 0x0039); AddFixed("SBA" ,CPU6800, CPU68HC11K4, 0x0010); |
||
| 812 | AddFixed("SEC" ,CPU6800, CPU68HC11K4, 0x000d); AddFixed("SEI" ,CPU6800, CPU68HC11K4, 0x000f); |
||
| 813 | AddFixed("SEV" ,CPU6800, CPU68HC11K4, 0x000b); AddFixed("SLP" ,CPU6301, CPU6301 , 0x001a); |
||
| 814 | AddFixed("STOP" ,CPU6811, CPU68HC11K4, 0x00cf); AddFixed("SWI" ,CPU6800, CPU68HC11K4, 0x003f); |
||
| 815 | AddFixed("TAB" ,CPU6800, CPU68HC11K4, 0x0016); AddFixed("TAP" ,CPU6800, CPU68HC11K4, 0x0006); |
||
| 816 | AddFixed("TBA" ,CPU6800, CPU68HC11K4, 0x0017); AddFixed("TPA" ,CPU6800, CPU68HC11K4, 0x0007); |
||
| 817 | AddFixed("TSX" ,CPU6800, CPU68HC11K4, 0x0030); AddFixed("TSY" ,CPU6811, CPU68HC11K4, 0x1830); |
||
| 818 | AddFixed("TXS" ,CPU6800, CPU68HC11K4, 0x0035); AddFixed("TYS" ,CPU6811, CPU68HC11K4, 0x1835); |
||
| 819 | AddFixed("WAI" ,CPU6800, CPU68HC11K4, 0x003e); |
||
| 820 | AddFixed("XGDX" ,CPU6301, CPU68HC11K4, (MomCPU == CPU6301) ? 0x0018 : 0x008f); |
||
| 821 | AddFixed("XGDY" ,CPU6811, CPU68HC11K4, 0x188f); |
||
| 822 | |||
| 823 | InstrZ = 0; |
||
| 824 | AddRel("BCC", CPU6800, 0x24); |
||
| 825 | AddRel("BCS", CPU6800, 0x25); |
||
| 826 | AddRel("BEQ", CPU6800, 0x27); |
||
| 827 | AddRel("BGE", CPU6800, 0x2c); |
||
| 828 | AddRel("BGT", CPU6800, 0x2e); |
||
| 829 | AddRel("BHI", CPU6800, 0x22); |
||
| 830 | AddRel("BHS", CPU6800, 0x24); |
||
| 831 | AddRel("BLE", CPU6800, 0x2f); |
||
| 832 | AddRel("BLO", CPU6800, 0x25); |
||
| 833 | AddRel("BLS", CPU6800, 0x23); |
||
| 834 | AddRel("BLT", CPU6800, 0x2d); |
||
| 835 | AddRel("BMI", CPU6800, 0x2b); |
||
| 836 | AddRel("BNE", CPU6800, 0x26); |
||
| 837 | AddRel("BPL", CPU6800, 0x2a); |
||
| 838 | AddRel("BRA", CPU6800, 0x20); |
||
| 839 | AddRel("BRN", CPU6801, 0x21); |
||
| 840 | AddRel("BSR", CPU6800, 0x8d); |
||
| 841 | AddRel("BVC", CPU6800, 0x28); |
||
| 842 | AddRel("BVS", CPU6800, 0x29); |
||
| 843 | |||
| 844 | AddALU8("ADC", "ADCA", "ADCB", NULL , True , 0x89); |
||
| 845 | AddALU8("ADD", "ADDA", "ADDB", NULL , True , 0x8b); |
||
| 846 | AddALU8("AND", "ANDA", "ANDB", NULL , True , 0x84); |
||
| 847 | AddALU8("BIT", "BITA", "BITB", NULL , True , 0x85); |
||
| 848 | AddALU8("CMP", "CMPA", "CMPB", NULL , True , 0x81); |
||
| 849 | AddALU8("EOR", "EORA", "EORB", NULL , True , 0x88); |
||
| 850 | AddALU8("LDA", "LDAA", "LDAB", "LDB", True , 0x86); |
||
| 851 | AddALU8("ORA", "ORAA", "ORAB", "ORB", True , 0x8a); |
||
| 852 | AddALU8("SBC", "SBCA", "SBCB", NULL , True , 0x82); |
||
| 853 | AddALU8("STA", "STAA", "STAB", "STB", False, 0x87); |
||
| 854 | AddALU8("SUB", "SUBA", "SUBB", NULL , True , 0x80); |
||
| 855 | |||
| 856 | InstrZ = 0; |
||
| 857 | AddALU16("ADDD", True , CPU6801, 0, 0xc3); |
||
| 858 | AddALU16("CPD" , True , CPU6811, 1, 0x83); |
||
| 859 | AddALU16("CMPD", True , CPU6811, 1, 0x83); |
||
| 860 | AddALU16("CPX" , True , CPU6800, 2, 0x8c); |
||
| 861 | AddALU16("CMPX", True , CPU6800, 2, 0x8c); |
||
| 862 | AddALU16("CPY" , True , CPU6811, 3, 0x8c); |
||
| 863 | AddALU16("CMPY", True , CPU6811, 3, 0x8c); |
||
| 864 | AddALU16("LDD" , True , CPU6801, 0, 0xcc); |
||
| 865 | AddALU16("LDS" , True , CPU6800, 0, 0x8e); |
||
| 866 | AddALU16("LDX" , True , CPU6800, 2, 0xce); |
||
| 867 | AddALU16("LDY" , True , CPU6811, 3, 0xce); |
||
| 868 | AddALU16("STD" , False, CPU6801, 0, 0xcd); |
||
| 869 | AddALU16("STS" , False, CPU6800, 0, 0x8f); |
||
| 870 | AddALU16("STX" , False, CPU6800, 2, 0xcf); |
||
| 871 | AddALU16("STY" , False, CPU6811, 3, 0xcf); |
||
| 872 | AddALU16("SUBD", True , CPU6801, 0, 0x83); |
||
| 873 | |||
| 874 | AddSing8("ASL", "ASLA", "ASLB", 0x48); |
||
| 875 | AddSing8("ASR", "ASRA", "ASRB", 0x47); |
||
| 876 | AddSing8("CLR", "CLRA", "CLRB", 0x4f); |
||
| 877 | AddSing8("COM", "COMA", "COMB", 0x43); |
||
| 878 | AddSing8("DEC", "DECA", "DECB", 0x4a); |
||
| 879 | AddSing8("INC", "INCA", "INCB", 0x4c); |
||
| 880 | AddSing8("LSL", "LSLA", "LSLB", 0x48); |
||
| 881 | AddSing8("LSR", "LSRA", "LSRB", 0x44); |
||
| 882 | AddSing8("NEG", "NEGA", "NEGB", 0x40); |
||
| 883 | AddSing8("ROL", "ROLA", "ROLB", 0x49); |
||
| 884 | AddSing8("ROR", "RORA", "RORB", 0x46); |
||
| 885 | AddSing8("TST", "TSTA", "TSTB", 0x4d); |
||
| 886 | |||
| 887 | AddInstTable(InstTable, "PSH" , 0x36, DecodePSH_PUL); |
||
| 888 | AddInstTable(InstTable, "PSHA", 0x36, DecodeSing8_Acc); |
||
| 889 | AddInstTable(InstTable, "PSHB", 0x37, DecodeSing8_Acc); |
||
| 890 | AddInstTable(InstTable, "PUL" , 0x32, DecodePSH_PUL); |
||
| 891 | AddInstTable(InstTable, "PULA", 0x32, DecodeSing8_Acc); |
||
| 892 | AddInstTable(InstTable, "PULB", 0x33, DecodeSing8_Acc); |
||
| 893 | |||
| 894 | AddInstTable(InstTable, "AIM", 0x61, DecodeBit63); |
||
| 895 | AddInstTable(InstTable, "EIM", 0x65, DecodeBit63); |
||
| 896 | AddInstTable(InstTable, "OIM", 0x62, DecodeBit63); |
||
| 897 | AddInstTable(InstTable, "TIM", 0x6b, DecodeBit63); |
||
| 898 | |||
| 899 | AddInstTable(InstTable, "PRWINS", 0, DecodePRWINS); |
||
| 900 | |||
| 901 | add_moto8_pseudo(InstTable, e_moto_pseudo_flags_be); |
||
| 902 | AddMoto16Pseudo(InstTable, e_moto_pseudo_flags_be); |
||
| 903 | AddInstTable(InstTable, "DB", eIntPseudoFlag_BigEndian | eIntPseudoFlag_AllowInt | eIntPseudoFlag_AllowString | eIntPseudoFlag_MotoRep, DecodeIntelDB); |
||
| 904 | AddInstTable(InstTable, "DW", eIntPseudoFlag_BigEndian | eIntPseudoFlag_AllowInt | eIntPseudoFlag_AllowString | eIntPseudoFlag_MotoRep, DecodeIntelDW); |
||
| 905 | } |
||
| 906 | |||
| 907 | static void DeinitFields(void) |
||
| 908 | { |
||
| 909 | DestroyInstTable(InstTable); |
||
| 910 | order_array_free(FixedOrders); |
||
| 911 | order_array_free(RelOrders); |
||
| 912 | order_array_free(ALU16Orders); |
||
| 913 | } |
||
| 914 | |||
| 915 | static Boolean DecodeAttrPart_68(void) |
||
| 916 | { |
||
| 917 | if (strlen(AttrPart.str.p_str) > 1) |
||
| 918 | { |
||
| 919 | WrStrErrorPos(ErrNum_UndefAttr, &AttrPart); |
||
| 920 | return False; |
||
| 921 | } |
||
| 922 | return DecodeMoto16AttrSize(*AttrPart.str.p_str, &AttrPartOpSize[0], False); |
||
| 923 | } |
||
| 924 | |||
| 925 | static void MakeCode_68(void) |
||
| 926 | { |
||
| 927 | PrefCnt = 0; |
||
| 928 | AdrCnt = 0; |
||
| 929 | |||
| 930 | /* Operandengroesse festlegen */ |
||
| 931 | |||
| 932 | if (AttrPartOpSize[0] == eSymbolSizeUnknown) |
||
| 933 | AttrPartOpSize[0] = eSymbolSize8Bit; |
||
| 934 | |||
| 935 | /* gehashtes */ |
||
| 936 | |||
| 937 | if (!LookupInstTable(InstTable, OpPart.str.p_str)) |
||
| 938 | WrStrErrorPos(ErrNum_UnknownInstruction, &OpPart); |
||
| 939 | } |
||
| 940 | |||
| 941 | static void InitCode_68(void) |
||
| 942 | { |
||
| 943 | Reg_MMSIZ = Reg_MMWBR = Reg_MM1CR = Reg_MM2CR = 0; |
||
| 944 | } |
||
| 945 | |||
| 946 | static Boolean IsDef_68(void) |
||
| 947 | { |
||
| 948 | return False; |
||
| 949 | } |
||
| 950 | |||
| 951 | static void SwitchTo_68(void) |
||
| 952 | { |
||
| 953 | TurnWords = False; |
||
| 954 | SetIntConstMode(eIntConstModeMoto); |
||
| 955 | |||
| 956 | PCSymbol = "*"; |
||
| 957 | HeaderID = 0x61; |
||
| 958 | NOPCode = 0x01; |
||
| 959 | DivideChars = ","; |
||
| 960 | HasAttrs = True; |
||
| 961 | AttrChars = "."; |
||
| 962 | |||
| 963 | ValidSegs = 1 << SegCode; |
||
| 964 | Grans[SegCode] = 1; ListGrans[SegCode] = 1; SegInits[SegCode] = 0; |
||
| 965 | SegLimits[SegCode] = (MomCPU == CPU68HC11K4) ? 0x10ffffl : 0xffff; |
||
| 966 | |||
| 967 | DecodeAttrPart = DecodeAttrPart_68; |
||
| 968 | MakeCode = MakeCode_68; |
||
| 969 | IsDef = IsDef_68; |
||
| 970 | SwitchFrom = DeinitFields; |
||
| 971 | InitFields(); |
||
| 972 | AddMoto16PseudoONOFF(False); |
||
| 973 | |||
| 974 | if (MomCPU == CPU68HC11K4) |
||
| 975 | { |
||
| 976 | static const ASSUMERec ASSUMEHC11s[] = |
||
| 977 | { |
||
| 978 | {"MMSIZ" , &Reg_MMSIZ , 0, 0xff, 0, SetK4Ranges}, |
||
| 979 | {"MMWBR" , &Reg_MMWBR , 0, 0xff, 0, SetK4Ranges}, |
||
| 980 | {"MM1CR" , &Reg_MM1CR , 0, 0xff, 0, SetK4Ranges}, |
||
| 981 | {"MM2CR" , &Reg_MM2CR , 0, 0xff, 0, SetK4Ranges}, |
||
| 982 | {"INIT" , &Reg_INIT , 0, 0xff, 0, SetK4Ranges}, |
||
| 983 | {"INIT2" , &Reg_INIT2 , 0, 0xff, 0, SetK4Ranges}, |
||
| 984 | {"CONFIG", &Reg_CONFIG, 0, 0xff, 0, SetK4Ranges}, |
||
| 985 | }; |
||
| 986 | |||
| 987 | pASSUMERecs = ASSUMEHC11s; |
||
| 988 | ASSUMERecCnt = as_array_size(ASSUMEHC11s); |
||
| 989 | |||
| 990 | SetK4Ranges(); |
||
| 991 | } |
||
| 992 | else |
||
| 993 | cpu_2_phys_area_clear(SegCode); |
||
| 994 | } |
||
| 995 | |||
| 996 | void code68_init(void) |
||
| 997 | { |
||
| 998 | CPU6800 = AddCPU("6800", SwitchTo_68); |
||
| 999 | CPU6801 = AddCPU("6801", SwitchTo_68); |
||
| 1000 | CPU6301 = AddCPU("6301", SwitchTo_68); |
||
| 1001 | CPU6811 = AddCPU("6811", SwitchTo_68); |
||
| 1002 | CPU68HC11K4 = AddCPU("68HC11K4", SwitchTo_68); |
||
| 1003 | |||
| 1004 | AddInitPassProc(InitCode_68); |
||
| 1005 | } |