Subversion Repositories pentevo

2025-01-01 [1.42 Bld 282]

- Addition    : new command line switch '-radix' to set

                default number system

- Addition    : implement built-in JS instruction macro

                for SC/MP

- Addition    : new command line switch '-intsyntax' to

                change default syntax for integer constants

2024-11-20 [1.42 Bld 281]

- Bugfix      : DB/DW on 68xx are big endian again

2024-11-15 [1.42 Bld 280]

- Addition    : DB and DW on 65xx and 68xx targets allow

                both Intel and Motorola style duplication

                of values.

- Addition    : Allow the {EXPAND}, {NOEXPAND}, {EXPIF},

                {NOEXPIF}, {EXPMACRO}, {NOEXPMACRO},

                {EXPREST}, and {NOEXPREST} directives

                also for IRP, IRPC, REPT, and WHILE,

2024-11-09 [1.42 Bld 279]

- Bugfix      : Add missing error message about invalid

                symbol name in some situations.

- Change      : Differentiate negative/positive floating

                point constant overflow.

- Change      : Detect overflow on integer constants,

                and try to treat them as float instead.

- Bugfix      : LONG instruction did not test for 32 bit

                value range.

2024-10-20 [1.42 Bld 278]

- Bugfix      : correct encoding of PDP-11 instructions

                M(F|T)P(D|I)

- Change      : uCOM-43: Issue warning when decision about

                CZP's argument type is unclear

- Change      : Introduce short circuit evaluation for

                logical AND and OR.

- Bugfix      : regard different arguments for LDS/LDD on

                TMS99110 and TI990.

2024-09-29 [1.42 Bld 277]

- Change      : IFDEF, IFNDEF, and DEFINED() also accept an

                expression as argument, not only a simple

                symbol name.  They return true if the

                expression does not contain any symbols

                that are undefined up to now.

- Bugfix      : Add missing PDP-11 instructions STCFD and STCDF.

- Bugfix      : 68K: Assume default operand size of 8 bits also

                for FScc and PScc, not only for Scc.

- Bugfix      : 68K: Allow PC-relative addressing for FRESTORE

                and PRESTORE.

2024-09-15 [1.42 Bld 276]

- Bugfix      : Regard infinities for DC.{SDP}, DD, and DQ

- Bugfix      : ...as a consequence, do not allow 'INF' for

                user-defined symbols

- Bugfix      : ifdef ..., if defined(...), and ifused ...

                did not check for valid symbol names

- Bugfix      : correct entry address printout for PLIST

2024-09-01 [1.42 Bld 275]

- Addition    : P2BIN warns if checksum overwrites data from

                source file(s)

- Bugfix      : uCOM-43: correct behaviour of JCP on last

                address in 64 byte page.

2024-08-25 [1.42 Bld 274]

- Addition    : pre-define variable FLOATMAX

- Addition    : use 80 bit extended float on host platforms

                supporting it

2024-08-05 [1.42 Bld 273]

- Addition    : support NEC uCOM 43/44/45

2024-07-24 [1.42 Bld 272]

- Change      : If the file name given as argument to INCLUDE

                or BINCLUDE does not contain an extension, the

                name extended by .INC and the plain name is

                searched for (in this order).

- Bugfix      : The message "Additional pass not started..."

                is now also added to the summary written

                to the console.

- Change      : Allow MFPT and XOR on T-11 (architecture

                handbook seems to be wrong on this)

- Change      : The DT pseudo instruction stores integer

                arguments in packed BCD format, instead

                of converting integers to floats

- Addition    : support Zilog eZ80

2024-06-26 [1.42 Bld 271]

- Bugfix      : warn about usage of MOV A,ACC on MCS-51

- Bugfix      : disallow odd addresses for CALL #IA on Super8

- Bugfix      : correct operand size of DIVD on 6309

- Bugfix      : correct FMOVE FPcr<->An handling on 68K

- Bugfix      : correct FMOVEM handling of dynamic register

                lists on 68K

- Addition    : add support for register symbols on x86

2024-06-19 [1.42 Bld 270]

- Bugfix      : allow .byte and .word on PDP-11 again.

- Addition    : initial VAX support

2024-04-13 [1.42 Bld 269]

- Addition    : Make per-line header in listing configurable

                via format string

2024-04-03 [1.42 Bld 268]

- Bugfix      : Z80: Do not warn about possible relative jump if

                relative jumping is not allowed for the given

                condition.

- Bugfix      : Z80: Do not warn about possible relative jump if

                the target address's value is questionable.  This

                applies e.g. to forward references in the first

                pass.

2024-03-30 [1.42 Bld 267]

- Addition    : Add new Z80 pseudo instruction 'J' that assembles

                as JR or JP, depending on branch distance.

- Bugfix      : Correct PHASE when handling addresses beyond 2 GByte.

- Addition    : Add a command-line switch '-wrelative' to enable

                warnings about possible relative jump.

- Change      : Rework the indiredt address expression parser for

                the following targets: 80C16x, uCOM78, 8086,

                TLCS-870(C), TLCS-90(0(0)), XA, Z80, Z8000.

                Behaviour *should* be the same as before.

2024-03-25 [1.42 Bld 266]

- Bugfix      : Add missing error message about invalid length

                of multi character constants.

- Bugfix      : Regard questionable forward references for Z80.

- Change      : The default target is now NONE instead of 68008.

                A target has to be set explicitly to generate code.

2024-03-15 [1.42 Bld 265]

- Change      : Learn maximum include level in first pass, so

                include nesting field in listing has fixed length

                in subsequent passes.

- Bugfix      : Correct address range checking for TLCS-900 and Z380.

2024-03-08 [1.42 Bld 264]

- Bugfix      : On Zx80, do not use indexed mode with extended

                displacement if the target is not Z380, even in

                case of a first-pass-unknown symbol.

2024-03-03 [1.42 Bld 263]

- Addition    : Add support for Sharp SC62015/SC61860 (contribution

                by Haruo Asano)

2024-02-11 [1.42 Bld 262]

- Addition    : New command line switch '-underscore-macroargs' to

                allow underscores in macro parameter names

- Change      : No longer allow omission of an empty index argument

                on 6809.  Use 'plainbase on' or '-plainbase' to allow

                this again.

- Bugfix      : 'DS 0' to align program counter did not operate

                correctly on addresses beyond 2 GByte

2024-01-28 [1.42 Bld 261]

- Bugfix      : On Z80-like targets, also do not parse double/triple

                -/+ as indirect expression

- Bugfix      : On NS32K, make parsing of address expressions more

                robust against arguments like '\'' or X'xx

2023-12-31 [1.42 Bld 260]

- Bugfix      : On Z80-like targets, do not parse single -/+ as

                indirect expression

- Bugfix      : If address overflow occured, the code that triggered

                it was displayed anyway in the listing, and with

                a wrong start address.

2023-12-27 [1.42 Bld 259]

- Bugfix      : On 68K, correctly skip spaces in indirect

                addressing argument lists

2023-12-23 [1.42 Bld 258]

- Bugfix      : disallow a few addressing modes for TST on 68K

- Bugfix      : reduce size of icon resource for Windows binaries

2023-12-17 [1.42 Bld 257]

- Change      : On F8, I/O accesses to addresses 0 to 3 via IN or

                OUT now result in a warning, since they are

                only accessible via INS and OUTS.

- Bugfix      : correct several 8087 instructions

2023-12-02 [1.42 Bld 256]

- Bugfix      : TLCS-90(0): Allow arguments of LDA, JP amd CALL to be

                written without enclosing parentheses.

- Addition    : Support register symbols for SC/MP

- Change      : On SC/MP, Usage of -128 as displacement with P1...P3

                emits a warning instead of an error 

2023-11-17 [1.42 Bld 255]

- Bugfix      : SC/MP: Allow PC-relative addressing with displacement

                of -128, but disallow using E.  Likewise, allow E and

                forbid -128 if pointer register is P1...P3.

- Change      : Message source files now have the extension '.mes'

                instead of '.res' to avoid extension conflicts with

                resource files on some systems

- Bugfix      : (Default) endianess for DW, DD,... on NS32K is little endian

- Addition    : Add BIGENDIAN for NS32K

2023-11-04 [1.42 Bld 254]

- Bugfix      : TLCS-9000: correct condition parsing

2023-11-04 [1.42 Bld 253]

- Bugfix      : SC/MP: Allow PC with displacement as address argument,

                as long as no auto-increment is used

- Bugfix      : SC/MP: Check whether PC-relative addressing would result

                in a displacement of -128

- Change      : Incorporate a couple of changes to compile with MSVC,

                provided by Fred N. van Kempen

2023-10-29 [1.42 Bld 252]

- Change      : Add $(EOBJ), $(OOBJ), $(TARG_EOBJ), and $(TARG_OOBJ)

                variables to Makefiles, which may be overridden by

                Makefile.def for non-'UNIX-style' compilers that do

                not use '-o'

- Addition    : 78(C)xx: Implement 'Z80-style' instructions for

                a couple of machine instructions

- Bugfix      : 78(C)xx: Do not accept undefined instructions:

                ADIW, ACIW, ADINCW, SUIW, SBIW, SUINBW

- Bugfix      : MCS-51: flag invalid addressing mode '@DPTR+disp'

2023-10-01 [1.42 Bld 251]

- Bugfix      : IM6100: Operand combination SZL OSR HLT did not work

- Bugfix      : IM6100: Allow combined instructions in lowercase

2023-09-27 [1.42 Bld 250]

- Bugfix      : Setting field length of PC in listing also works

                if target is given via CPU statement in source file

2023-09-25 [1.42 Bld 249]

- Addition    : Allow zero-padded PC in listing by setting a list

                radix with leading zero

2023-09-17 [1.42 Bld 248]

- Change      : Allow values between 0x80 and 0xff on 68K, but warn

                about sign extension

- Bugfix      : Correct encoding of V35 BRKS/BRKN instructions

- Addition    : Add new NEC Vxx variants

- Bugfix      : Add missing JLT, JGT, and JGE instructions for

                TMS7000

2023-07-10 [1.42 Bld 247]

- Change      : No separate .msg files any more for most platforms

- Bugfix      : Several fixes to work with compilers shipped with

                Debian 12 (Bookworm)

2023-05-24 [1.42 Bld 246]

- Change      : The binary's name is now 'asl' on all platforms.

- Bugfix      : Use system-specific path separator when searching

                for suffix

2023-05-14 [1.42 Bld 245]

- Change      : Rework command line output and operation:

                - No interactive query of input files, if none

                  are given via command line.

                - Version information is only printed if verbose

                  operation (-v) or version info (-version) is

                  requested.

                - Verbose help is printed upon request (-help).

                - CPU list is printed if requested via '-cpu list'

                  or '-cpu ?'.

                - paging of CPU list or help is off by default

                  and may be re-enabled by '-screenheight' argument

- Change      : Remove proposal for new program name (for the

                moment)

2023-05-07 [1.42 Bld 244]

- Addition    : Make proposal for new program name

- Addition    : Always allow .SET, .EQU, .PAGE, .SWITCH,

                .SHIFT, .SAVE and .RESTORE as alternatives to

                the 'undotted' instructions, regardless whether

                machine instructions of same name exist.

- Bugfix      : Correct handling of on/off instructions inside

                expanded macros

2023-04-15 [1.42 Bld 243]

- Addition    : Add Renesas RX target (contribution

                by Haruo Asano)

- Bugfix      : WD16: correct format 11 addressing modes

- Bugfix      : PDP-11/WD16: @(Rn) was wrongly assembled as @Rn

2023-04-10 [1.42 Bld 242]

- Change      : Enable more FP16 tests

- Bugfix      : assign unique header ID to PDP-11

- Change      : Multi-character constants are now little endian

                on PDP-11

- Addition    : Add Western Digital WD16 target

2023-04-01 [1.42 Bld 241]

- Bugfix      : Correct displacement value for relative branches

                and PC-relative addressing on PDP-11

- Addition    : Support CALL as alias for JSR on PDP-11 with PC

                as register

- Bugfix      : Correct availibility of MTPS/MFPS on PDP-11 variants

- Bugfix      : Correct 16-bit indexed addressing on Konami 052001

                if index register is not PC

2023-03-27 [1.42 Bld 240]

- Addition    : add Konami 052001 as target

2023-03-08 [1.42 Bld 239]

- Addition    : allow to set BIGENDIAN flag's default value by

                command line

- Addition    : allow to set PACKING flag's default value by

                command line

- Bugfix      : Allow 8 bit AND/OR on H8/300(L)

- Addition    : German documentation may optionally be built

                with Babel-based German style

2023-02-19 [1.42 Bld 238]

- Bugfix      : Extend and correct Code page 037 definition

- Addition    : Support ORB as alias for OR on PALM

- Addition    : Add definition of IBM 5110's variant of EBCDIC

- Addition    : Add character set definition for IBM 5100

- Addition    : JMP on PALM encodes as BRA if possible

- Addition    : CHARSET allows characters to be defined

                'non-existant' on the target system

- Addition    : Allow alternative conditions P/N/Z on 2650,

                plus numeric conditions

- Addition    : Add ACON and RES instructions on 2650

- Addition    : Optionally allow A'...' syntax for multi

                character constants.

- Addition    : Support BIGENDIAN on 2650 to control

                behaviour of DW, DD, DQ...

- Bugfix      : JMP on PALM now also supports auto-increment

                and -decrement

2023-02-05 [1.42 Bld 237]

- Addition    : Add National Semiconductor IMP-16 and PACE targets

2023-01-18 [1.42 Bld 236]

- Addition    : Add Rockwell PPS-4 target

- Addition    : Add DCM statement to 6502 to dispose

                floating point constants in Apple format

2022-12-31 [1.42 Bld 235]

- Addition    : Add AEG/Olympia CP-3F target

- Change      : Reworked symbol table handling to make it

                slightly faster

2022-12-21 [1.42 Bld 234]

- Addition    : Allow DB as alias for BYT on 65xx

- Addition    : Allow DW as alias for ADR on 65xx

- Addition    : Allow DS as alias for RMB on 65xx

- Addition    : Add DDB for 65xx and MELPS-7700

2022-12-05 [1.42 Bld 233]

- Bugfix      : Correct encoding of SP register alias on SH

- Bugfix      : Add missing comparison operators for register symbols

- Addition    : Allow != as unequality operator

- Bugfix      : addr(ireg) was correctly encoded as PC-relative on V60,

                but without encoding a possible index register

2022-11-01 [1.42 Bld 232]

- Addition    : Add translation of non-printable ASCII control characters

                to EBCDIC code page

- Addition    : Add BCDINC (code page 359)

- Addition    : Add RADIX 50 code page and packing macro

- Addition    : Add CODEPAGE_VAL function to query mapping of a

                single character

- Bugfix      : DC.x on V60 gets correct operand size, uses little

                endian and does not pad by default

- Bugfix      : V60: plain address as address operand is treated as

                PC-relative instead of being silently ignored

2022-10-23 [1.42 Bld 231]

- Addition    : Add IBM PALM target

2022-10-03 [1.42 Bld 230]

- Addition    : Add DEC PDP-11 target

2022-08-24 [1.42 Bld 229]

- Addition    : Add NEC V60 target

2022-08-03 [1.42 Bld 228]

- Addition    : Add Intersil IM6100/6120 target (contribution

                by Haruo Asano)

2022-07-17 [1.42 Bld 227, the Asano & Tadaoka build ;-) ]

- Bugfix      : re-initialize radix & outradix base at every

                pass

- Bugfix      : assemble LODZ R0 as IORZ R0 on 2650

- Bugfix      : explicitly disallow STRZ R0 on 2650

- Bugfix      : regard 8K modulo arithmetic for relative addressing on 2650

- Change      : Allow 32K (4*8K) address space on 2650

- Bugfix      : Add missing V30 BRKEM instruction

- Addition    : Add V30EMU target as variant of 8080 with

                CALLN and RETEM instructions

2022-07-13  [1.42 Bld 226]

- Bugfix      : Correct argument separator for DSP56K (Tab)

- Bugfix      : If line continuation is used, use the line

                number of the first line, not the last one

2022-07-09  [1.42 Bld 225]

- Addition    : Add HP Nano Processor target (contribution by Haruo Asano)

- Change      : No longer provide manual as PostScript (may be generated

                from PDF version or from doc_*/as.pdf target).

2022-07-03  [1.42 Bld 224]

- Addition    : Support PACKING for 56000, TMS320C3x/4x, TMS32060, 

                uPD7720/7725, and uPD77230

- Bugfix      : DATA on uPD7720/7725 in packed mode behaves the same

                way as DW for uPD77230, i.e. characters are filled in

                from left to right into words

- Bugfix      : Correct INS/EXT on V30 with immediate operand

- Bugfix      : On V30, allow CY as operand to NOT1/CLR1/SET1

2022-06-15 [1.42 Bld 223]

- Addition    : Support PACKING for MN1610 (contribution by Haruo Asano)

                and CP1600 (contribution by Kasumi Yoshino)

- Addition    : Support floating point constants for MN1610 (contribution by Haruo Asano)

- Addition    : 68HC11K4: ASSUME may be informed about the values

                of CONFIG, INIT and INIT2 registers

- Addition    : Z180: Value of CBAR, CBR, and BBR may be specified

                via ASSUME, to define the 64K -> 512K address mapping

2022-03-16 [1.42 Bld 222]

- Bugfix      : -supmode command line switch works again

- Bugfix      : Z8000: correct register overlap check for PUSH/POP

2022-03-12 [1.42 Bld 221]

- Bugfix      : 68K: allow k factor to FMOVE on dest operand

2022-02-13 [1.42 Bld 220]

- Bugfix      : correct MCS-96 RST instruction (was 'RSC' instead)

- Change      : MCS-96: change a few 32 bit operand alignment warnings

                to errors, to make consistent with 16 bit alignment

                errors

2022-02-09 [1.42 Bld 219]

- Bugfix      : Symbols without assigned address space did not appear

                in MAP file

2022-02-02 [1.42 Bld 218]

- Addition    : add DEFBIT for uPD7807...7809

- Change      : A couple of target-specific symbols now only appear

                in the symbol table if the respective target was

                actually used

2022-01-30 [1.42 Bld 217]

- Bugfix      : 2650: do not allow ANDZ R0 (decodes as HALT)

- Bugfix      : uPD780x: disallow some uPD781x-specific addressing modes

                for LDAX and STAX

- Addition    : support NEC uPD7807...7809

- Bugfix      : Do not attempt to expand string expansion for symbol

                names in quoted regions

- Bugfix      : The default for PADDING for 6805, 6809, 6816, 68RS08,

                and S12Z should be OFF

2022-01-19 [1.42 Bld 216]

- Bugfix      : Z80: add error messages about address/displacement

                overflow that got lost during address parser rework

2021-12-26 [1.42 Bld 215]

- Bugfix      : Z80: Allow register symbols for JP (IX/IY), forbid

                on Gameboy Z80

2021-12-23 [1.42 Bld 214]

- Addition    : Add some syntax variants for Sharp SM83

- Addition    : Allow SLI/SL1 as alias for SLIA/SLS on Z80UNDOC

- Addition    : Allow EXA as alias for EX AF,AF' on Z80

- Addition    : Allow EXD as alias for EX DE,HL on Z80

- Addition    : For undocumented Z80 instructions with extra

                destination reg, allow dest reg to be last arg

                instead of first

- Addition    : Allow register symbols for Z80

2021-11-22 [1.42 Bld 213]

- Bugfix      : Correct TMS1100 XMA instruction

- Addition    : Add Sharp LR35902 ('Gameboy Z80') as target

- Bugfix      : Allow (X0)/(X1) as argument on MN1613 LR

- Bugfix      : Allow lowercase register names  on MN1613 LR

2021-11-03 [1.42 Bld 212]

- Bugfix      : Do not print empty file name () on listing pages with symbol tables

- Addition    : Add CP-1600 target (contribution by Haruo Asano)

2021-10-03 [1.42 Bld 211]

- Bugfix      : Allow register aliases starting with period in 68K address expressions

2021-09-28 [1.42 Bld 210]

- Bugfix      : Regard Address-Shift instructions with single argument on TMS3201x

- Bugfix      : Be more tolerant about leading/trailing spaces in indirect address

                expressions on 68K

2021-09-19 [1.42 Bld 209]

- Addition    : Add built-in IN/OUT symbols PA0..PA7 for TMS3201x

2021-09-13 [1.42 Bld 208]

- Addition    : Add support for NEC uCOM87 (uPD780x)

2021-07-26 [1.42 Bld 207]

- Bugfix      : NS32K: allow immediate destination operand for CMPf

2021-07-25 [1.42 Bld 206]

- Bugfix      : NS32K: allow immediate destination operand for CMPQi

- Bugfix      : correct address output for Intel32 Hex format

2021-07-03 [1.42 Bld 205]

- Bugfix      : correct encoding and allowed addressing modes of XCH(B) on MCS-96

- Change      : huge internal rework to allow strings longer than 255 characters

                at some (but far off from all...) places

2021-05-08 [1.42 Bld 204]

- Bugfix      : fix SC/MP target

2021-05-07 [1.42 Bld 203]

- Addition    : Allow changing the program counter by assigning value to PC

                symbol

- Addition    : Allow BIGENDIAN for SC/MP

- Bugfix      : Several bugfixes if host system is big-endian

2021-04-25 [1.42 Bld 202]

- Change      : Somewhat less unintuitive error message if source file cannot

                be opened

- Bugfix      : Better handling of DUP operator in DB, DW, DD... if there is

                also a symbol of this name

- Addition    : Add file name to all error messages when file open fails

2021-04-17 [1.42 Bld 201]

- Bugfix      : fix MSP430X MOVA instruction with 0(Rn) or @Rn as destination

- Change      : Logic to update label's value in case of implicit padding gets

                reset by less pseudo instructions

2021-03-28 [1.42 Bld 200]

- Addition    : Add NS32K custom processor instructions

- Addition    : Add NS32K floating point register names Lx

- Bugfix      : repair -D <var>=<value> option

2021-03-19 [1.42 Bld 199]

- Bugfix      : Correct address of NS32082 BPR1 register 

- Bugfix      : Correct operand size handling of NS32xxx MOVLF/MOVFL

- Bugfix      : Correct operand size of NS32xxx shift/rotate instructions

- Addition    : Allow addr(pc) as syntax for NS32xxx PC-relative addressing

- Addition    : Allow disp2(disp1(ext)) as syntax variant for NS32xxx

                external mode

2021-03-17 [1.42 Bld 198]

- Bugfix      : Some cleanups regarding Z180 I/O instructions

- Addition    : PMMU instruction on NS32000 allows differentiation

                of MMU variants

- Bugfix      : NS32000: Correct addressing modes of INDEXi and CVTP

- Bugfix      : NS32000: Correct EXT addressing mode

2021-03-14 [1.42 Bld 197]

- Addition    : Support NS32000 as target

2021-03-02 [1.42 Bld 196]

- Bugfix      : Correct ADDQ/SUBQ range checking for 68K

2021-02-18 [1.42 Bld 195]

- Bugfix      : Avoid identifying 0B....H as C-style binary in relaxed mode

- Bugfix      : correct indexed addressing mode with short base for Z8000

2021-02-15 [1.42 Bld 194]

- Bugfix      : fix SAVE/RESTORE instructions

- Addition    : add J... variable branch instructions for 180x

2021-02-13 [1.42 Bld 193]

- Addition    : add more flexible integer format configuration

- Addition    : add PORT statement for 8008

- Addition    : add Z80SYNTAX for 8008

2021-01-30 [1.42 Bld 192]

- Addition    : Initial support for Padauk controllers

- Bugfix      : fix ST6 ASCII/ASCIZ instructions

2021-01-21 [1.42 Bld 191]

- Addition    : SC/MP: allow writing registers as 0..3 instead of P0..P3

- Addition    : SC/MP: add x'... notation option for integer literals

- Bugfix      : correct NoICE debug output

- Bugfix      : corect cross reference list output

2021-01-18 [1.42 Bld 190]

- Bugfix      : emit more reasonable error message when trying to

                convert multi-character constant resp. string of

                excessive length to integer

- Addition    : Z8000 Syntax extensions:

                - Add a few aliases for conditions

                - Add a few aliases for flag names

                - Allow Rn^ instead of @Rn for indirect addressing

                - for alternate (AMD) syntax, allow leaving away

                  indirection character for indirectly addressed I/O

- Bugfix      : repair NoICE debug output

- Addition    : add -supmode switch to enable supervisor mode

                right from the beginning

2021-01-10 [1.42 Bld 189]

- Bugfix      : correct encoding of Z8000 CALR instruction

- Bugfix      : string expansion was not done for names of structure

                elements

- Bugfix      : correct inclusion of bit symbols in nested structures

- Addition    : extend list of supported F8 variants

- Addition    : add option to define arrays of structures

2020-12-27 [1.42 Bld 188]

- Bugfix      : correct encoding of Z8000 EI/DI instruction

- Addition    : Add F3850 as target (contribution by Haruo Asano)

- Bugfix      : do not display line numbers in split byte notation

2020-12-25 [1.42 Bld 187]

- Bugfix      : add a couple of missing instructions and

                instruction/operand combinations to Z8000 target

2020-12-21 [1.42 Bld 186]

- Addition    : add -q(uiet) command line switch to PLIST and support

                multiple files

- Addition    : Support Z8000 as target

- Addition    : add -splitbyte command line switch

2020-12-09 [1.42 Bld 185]

- Addition    : Add compatibility mode switch for better compatibility

                with original assemblers on certain targets

2020-12-08 [1.42 Bld 184]

- Change      : Output generated by MESSAGE to console is suppressed

                in quiet mode

- Addition    : Add configurable maximum include nesting level

- Addition    : add -q(uiet) command line switch to P2BIN and P2HEX

- Change      : 'make test' now runs in quiet mode on *IX systems, set V=1

                to get verbose output back

- Addition    : Optimize SUB #(-2...+2),... to ADD:Q only if Q format requested

2020-12-03 [1.42 Bld 183]

- Bugfix      : Disallow optimzation to CoMPare 8-bit immediate value with

                16-bit operand on H8/500

2020-11-26 [1.42 Bld 182]

- Bugfix      : Better treatment of (mis)detection of non-octal constants

                in relaxed mode

- Bugfix      : If whole instruction has dot prefix, still search for

                attribute in it

2020-11-25 [1.42 Bld 181]

- Addition    : Support :8 and :16 instruction formats for branches on H8/500

- Bugfix      : Some fixes to H'xxxx hex syntax on H8/500 and H8/300

- Bugfix      : correct TLCS-90 MUL/DIV with immediate addressing

2020-11-18 [1.42 Bld 180]

- Addition    : Support Toshiba TLCS-870/C as target

- Bugfix      : do not search relative to current file's path if (B)INCLUDEd

                file's path is absolute

2020-11-08 [1.42 Bld 179]

- Bugfix      : MCS-48: correctly regard forward references when checking

                memory bank of CALL/JMP target

2020-11-04 [1.42 Bld 178]

- Addition    : Add DW and DB as aliases for BYT/ADR for 68xx targets

- Addition    : Add MB assume value for MCS-48

- Bugfix      : fix -r option on p2bin and p2hex

2020-10-25 [1.42 Bld 177]

- Addition    : Add some 68xx instruction aliases used on other assemblers

- Addition    : new target: KENBAK

2020-10-19 [1.42 Bld 176]

- Addition    : bit symbols for H8/300 and H8/500

- Addition    : support half size (16 bit) floating point type

2020-10-02 [1.42 Bld 175]

- Addition    : register symbols for TLCS-9000

- Addition    : -relaxed command line switch to enable RELAXED mode

                by default

- Addition    : For H8/500, allow H'... syntax for hex constants in

                relaxed mode

- Addition    : For H8/500, bit operations by default assume word size

                if destination is a register

- Addition    : For H8/500, allow :8 and :16 size specifiers on immediate

                source operand for MOV and CMP

- Addition    : For H8/500, allow DATA as an alias for DC

2020-09-19 [1.42 Bld 174]

- Change      : rework register symbol handling

- Addition    : register symbols for 68K, M16, M16C, H8/300, H8/500,

                SH7x00, XGATE, H16, i960, XA, and 29K

2020-08-25 [1.42 Bld 173]

- Change      : avoid error/warning number of zero

- Addition    : allow operand size attributes for SET and EQU

2020-06-22 [1.42 Bld 172]

- Addition    : add column to MAP file declaring whether symbol is constant

                or variable

- Bugfix      : Z8: do not allow odd indirect register pairs

- Bugfix      : differentiate CMOS/NMOS Z8 variants, remove Z8604 due to lack of documentation

- Bugfix      : Super8: Allow arguments with bit 3 set for SRP0/SRP1

- Bugfix      : Super8: correct CALL IA encoding

- Bugfix      : Super8: Only allow even register addresses for MULT/DIV/LDW/DECW/INCW on Super8/Z8

- Change      : Super8: rename devices to Z88C00 and Z88C01

- Bugfix      : Z8/Super8: correct 8-bit-displacements to be signed

- Addition    : allow argument 1/2/4 to RTWP on TMS99105/99110

2020-06-13 [1.42 Bld 171]

- Addition    : add option to operate AVR target with byte-structured

                code segment

2020-06-08 [1.42 Bld 170]

- Bugfix      : catch segfault when being called with non-existent

                file

2020-05-27 [1.42 Bld 169]

- Addition    : new built-in function DEFINED() to test whether

                a symbol is defined

- Change      : remove strict distinction between strings and

                multi-character constants

- Bugfix      : do not allow CMPI with PC-relative destination

                up to 68010.

- Bugfix      : 68K: forbid usage of An with byte size in a few

                instructions

2020-05-18 [1.42 Bld 168]

- Bugfix      : avoid spurious occurences of 'pointer size passed to as_vsnprcatf' message

- Bugfix      : fix 6301 BSET/BCLR instructions

2020-05-17 [1.42 Bld 167]

- Bugfix      : do not allow BRN on 6800

- Addition    : add 6801 as target

2020-05-15 [1.42 Bld 166]

- Bugfix      : add HALT instruction for 8080/8085 in Z80 syntax mode

- Addition    : implement 8085(UNDOC) instructions also in Z80 syntax

- Addition    : provide exclusive Z80 syntax mode

2020-05-03 [1.42 Bld 165]

- Addition    : Add Philips (MAB)84X1

2020-04-26 [1.42 Bld 164]

- Bugfix      : correct encoding of 65816 MVP/MVN instructions

- Addition    : Add DN instruction to dispose nibbles (because I can...)

- Addition    : Support DB/DW/DD/DQ/DT instructions for Atmel AVR

- Addition    : Add EEDATA segment for Atmel AVR and PIC16C8x

- Addition    : Extend P2BIN & P2HEX to allow data conversion from

                other segments than CODE

2020-04-12 [1.42 Bld 163]

- Change      : make codepage/character set handling more flexible

2020-04-05 [1.42 Bld 162]

- Change      : rework remaining include files to English comments

- Bugfix      : correct 4004 RnP register pair syntax

2020-04-04 [1.42 Bld 161]

- Addition    : Allow numeric condition argument to JCN on 4004

- Addition    : Allow alternate register pair syntax for 4004

- Change      : rework more include files to English comments

2020-04-02 [1.42 Bld 160]

- Bugfix      : change handling of 65816 BRK instruction, similar to 6502

- Bugfix      : correct PER instruction on 65816

- Change      : start reworking include files to English comments

2020-03-29 [1.42 Bld 159]

- Change      : change the strategy PADDING uses

2020-03-21 [1.42 Bld 158]

- Addition    : Provide register definitions for a couple of

                Z8 Encore targets

- Addition    : Provide bit object support for Z8 Encore

- Change      : allow more 8-bit characters in macro parameter names

2020-03-04 [1.42 Bld 157]

- Addition    : Add Zilog Super8 as target

2020-02-19 [1.42 Bld 156]

- Change      : rework build system to allow cross-builds

2020-01-31 [1.42 Bld 155]

- Addition    : Add TI990/12

- Bugfix      : 68xxx RESET instruction should be privileged

- Bugfix      : ANDI/ORI with CCR should be available on 68008 as well

2020-01-24 [1.42 Bld 154]

- Addition    : differentiate TMS9900 and Model 990 computer regarding

                privileged mode, add TMS9995, TMS99105 and TMS9940

2020-01-12 [1.42 Bld 153]

- Bugfix      : Corrections for 6309 PC-relative addressing

                when opcode is longer than one byte

- Change      : change handling of 6502 BRK instruction

- Bugfix      : allow some more addressing modes for 6309

2020-01-06 [1.42 Bld 152]

- Bugfix      : eliminate redundant error messages on 6502

- Change/Fix  : rework handling of listing macro expansion modifiers

- Bugfix      : correct operand order for shift instructions on MIL STD 1750

- Bugfix      : escape again spaces in MAP file output

- Bugfix      : handle case of empty label with : marker

2019-12-07 [1.42 Bld 151]

- Addition    : Add MN161x as target (contribution by Haruo Asano)

- Addition    : allow explicit address size specification on BBC/BBR/RMB/SMB for 65C02++

- Bugfix      : LDA (nn) was accidentally allowed for 6502

- Bugfix      : Change addressing mode from (nnnn) to (nn) for HuC6280

- Addition    : Add more devices and bit symbols for ST6

2019-09-25 [1.42 Bld 150]

- Addition    : Add a couple of ST7 types

2019-09-15 [1.42 Bld 149]

- Bugfix      : built-in function abs() works again

- Change      : ORG to same address no longer starts a new record

                in output file

- Addition    : new command line switch '-listradix' to set number

                system in listing

2019-07-20 [1.42 Bld 148]

- Addition    : Add P2HEX output format "C arrays".

- Addition    : Add a couple of ST7/STM8 types

2019-06-09 [1.42 Bld 147]

- Addition    : Make include file search strategy more C-like:

                primarily search in the directory of the file

                that contains the INCLUDE statement, not the

                current directory the assembler was called from.

- Change      : Allow forward references in "\{...}" expressions

- Change      : Allow SET as both pseudo and machine instruction

                if it can be differentiated by argument count.

- Addition    : Add STM8 target

2019-04-20 [1.42 Bld 146]

- Addition    : Added J as generic relative jump for 78C1x

- Bugfix      : correct index underflow access on Z80 for some cases

- Bugfix      : Allow spaces between function name and argument(s)

- Bugfix      : Correct file closing/cleanup

2019-03-09 [1.42 Bld 145]

- Bugfix      : correct argument count check for STRUCT

- Addition    : Added Hitachi H16 target

- Addition    : allow displacement/address length override on TLCS-900

- Bugfix      : regard phase errors in data disposition instructions

- Addition    : add Commodore/CSG 65CE02 target

2019-02-15 [1.42 Bld 144]

- Bugfix      : correct/augment addressing modes for TLCS-900

2019-02-08 [1.42 Bld 143]

- Bugfix      : correct ColdFire MAC/EMAC syntax 

2019-02-02 [1.42 Bld 142]

- Addition    : Added Parallax SX20/28 target

- Bugfix      : Fix some errors regarding escaped characters in quoted sections

- Bugfix      : Allow index register scaling for Coldfire (again)

- Bugfix      : Better handling of forward-defined displacements on 68K/Coldfire

2019-01-03 [1.42 Bld 141]

- Addition    : Added Coldfire target MCF51QM

2018-12-21 [1.42 Bld 140]

- Addition    : support Fairchild F8

- Addition    : allow < and > modifiers on MCS-96 to force short resp.

                long address coding

- Addition    : allow < and > modifiers on C16x to force short resp.

                long coding

- Change      : remove limit of 20 instruction arguments

2018-11-26 [1.42 Bld 139]

- Bugfix      : allow word size for 68K move-to-CCR

- Change      : regard address space limit for short addressing on 68K

- Bugfix      : several fixes regarding forward references for 68K

2018-11-02 [1.42 Bld 138]

- Addition    : new command line swith -maxerrors to allow termination

                of assembly after a given number of errors.

- Addition    : new command line switch -Werror to treat warnings as

                errors

- Bugfix      : correct value range of 68K MOVEQ instruction

- Addition    : allow bit-addressable locations to be written in

                internal representation for 80C16x

- Addition    : reworked and extended ColdFire support

2018-09-04 [1.42 Bld 137]

- Change      : Huge internal reworks to allow reporting column of error

2018-08-06 [1.42 Bld 136]

- Addition    : allow nested use of PHASE and DEPHASE

- Addition    : allow some pseudo-ops and aliases for operators/phases for 53C8XX

- Bugfix      : fix assembly of 8086 OUT <imm>,AX/AL

- Bugfix      : fix assembly of 78K4 CALLF/CALLT/RETCS with !-marked argument

- Bugfix      : fix assembly of DSAREL() expressions on 53C8xx

- Bugfix      : fix specification of data register as 68K PMMU function code

2018-06-18 [1.42 Bld 135]

- Bugfix      : some instructions no longer worked on 68008

- Change      : P2HEX and P2BIN by default use auto-ranging

2018-05-06 [1.42 Bld 134]

- Addition    : add support NXP S12Z ("MagniV") family

2018-04-18 [1.42 Bld 133]

- Change      : ALIGN uses execution instead of load address as base

- Addition    : allow ALIGN to optionally fill padding area with

                byte pattern

2018-04-10 [1.42 Bld 132]

- Bugfix      : correct result of strstr() if search string is at end

                of string

- Bugfix      : correct month display on locale systems (off-by-one)

- Bugfix      : Also regard ' and " if enclosed in () or []

2018-03-29 [1.42 Bld 131]

- Bugfix      : correct date display on locale systems

2018-03-28 [1.42 Bld 130]

- Bugfix      : clean up date & time format handling for locale-based systems

2018-03-16 [1.42 Bld 129]

- Bugfix      : correct assumption of length of forward JSR/JMP on 68HC12

2018-03-11 [1.42 Bld 128]

- Bugfix      : correct distance range checking on SC/MP

2018-03-04 [1.42 Bld 127]

- Bugfix      : avoid 'target not on same page' for forward references

                on several platforms

2018-02-28 [1.42 Bld 126]

- Addition    : add AT43USB355

- Bugfix      : when writing line to .i file that contained a macro

                call and a label, only write out the label, plus an

                eventual comment.

2018-02-24 [1.42 Bld 125]

- Bugfix      : correct argument checking for CHARSET

- Bugfix      : If a line calling a macro contains a label not consumed

                by the macro, output the line (minus tha macro call)

                in the -P output

- Addition    : Optionally display column and position in source line

                for some errors

2018-01-21 [1.42 Bld 124]

- Addition    : add ATmega{8|16|32}U2,

                    ATmega{16|32}U4,

                    ATmega32U6,AT90USB646/647,AT90USB1286/1287

- Bugfix      : correct address space deduction for AVR

- Bugfix      : defining CPU aliases for AVR works again

2017-12-26 [1.42 Bld 123]

- Addition    : add ATtiny48/88/43u/441/841/828/1634/87/167/

                4/5/9/10/20/40/102/104/28/11/12/15/13A/24A/44A/

                84A, AT90S2323/2333/2343/8534

- Addition    : replace MACEXP with MACEXP_DFT/MACEXP_OVR

2017-11-27 [1.42 Bld 122]

- Bugfix      : correct double ASSR definition for ATmega8/16/32

- Bugfix      : correct UPE definition for ATmega162

- Bugfix      : correct SFR area size for ATmega1284RFR2

- Addition    : add a first batch of ATtiny variants

2017-11-21 [1.42 Bld 121]

- Bugfix      : correct behaviour of DATA for Atmel AVR

2017-11-20 [1.42 Bld 120]

- Addition    : add more ATmega variants