WebSVN – pentevo – Blame – /rom/page5/source/fat/sl811_equ.a80

Rev	Author	Line No.	Line
845	savelij	1
		2	;last update: 16.06.2019 savelij
		3
		4	sl811clock EQU 12000000
		5
		6	MAX_EP EQU 5
		7	BUFFER_LENGTH EQU 1024
		8
		9	;Usb Ethernet ports
		10	;#define UE_INT_RES 0x83AB
		11	;#define UE_CONTROL 0x82AB
		12	;#define UE_MAPW5300 0x81AB
		13	;#define SL811H_ADDR 0x80ab// 0x08000
		14	;#define SL811H_DATA 0x00ab// 0x08001
		15	UE_INT_RES EQU 0X83AB
		16	UE_CONTROL EQU 0X82AB
		17	UE_MAPW5300 EQU 0X81AB
		18	SL811H_ADDR EQU 0X80AB
		19	SL811H_DATA EQU 0X00AB
		20
		21	RBC_CMD_READ10 EQU 0x28
		22	RBC_CMD_READCAPACITY EQU 0x25
		23	RBC_CMD_WRITE10 EQU 0x2A
		24	SPC_CMD_INQUIRY EQU 0x12
		25	SPC_CMD_PRVENTALLOWMEDIUMREMOVAL EQU 0x1E
		26	SPC_CMD_REQUESTSENSE EQU 0x03
		27	SPC_CMD_TESTUNITREADY EQU 0x00
		28
		29	bFlags struct
		30	SLAVE_IS_ATTACHED DB ? ;
		31	SLAVE_REMOVED DB ? ;
		32	SLAVE_FOUND DB ? ; // Slave USB device found
		33	SLAVE_ENUMERATED DB ? ; // slave USB device enumeration done
		34	SLAVE_ONLINE DB ? ;
		35	TIMEOUT_ERR DB ? ; // timeout error during data endpoint transfer
		36	DATA_STOP DB ? ; // device unplugged during data transfer
		37	bData1 DB ? ;
		38	bMassDevice DB ? ;
		39	BULK_OUT_DONE DB ? ;
		40	DATA_INPROCESS DB ? ;
		41	bFlags endstruct
		42
		43	pUSBDEV struct
		44	wVID DW ?
		45	wPID DW ?
		46	bClass DB ?
		47	bNumOfEPs DB ?
		48	iMfg DB ?
		49	iPdt DB ?
		50	bId1 DB ?
		51	bId2 DB ?
		52	bEPAddr DB MAX_EP dup (?)
		53	bAttr DB MAX_EP dup (?)
		54	wPayLoad DW MAX_EP dup (?)
		55	bInterval DW MAX_EP dup (?)
		56	bData1 DB MAX_EP dup (?)
		57	pUSBDEV endstruct
		58
		59	SetupPKG struct
		60	bmRequest DB ?
		61	bRequest DB ?
		62	wValue DW ?
		63	wIndex DW ?
		64	wLength DW ?
		65	SetupPKG endstruct
		66
		67	PKG struct
		68	usbaddr DB ?
		69	endpoint DB ?
		70	pid DB ?
		71	wPayload DB ?
		72	wLen DW ?
		73	buffer DW ?
		74	setup SetupPKG
		75	epbulkin DB ?
		76	epbulkout DB ?
		77	PKG endstruct
		78
		79	;-------------------------------------------------------------------------
		80	; EP0 use for configuration and Vendor Specific command interface
		81	;-------------------------------------------------------------------------
		82	EP0_Buf EQU 0x10 ;define start of EP0 64-byte buffer
		83	EP1_Buf EQU 0x40 ;define start of EP1 64-byte buffer
		84
		85	;-------------------------------------------------------------------------
		86	; SL811H Register Control memory map
		87	; --Note:
		88	; --SL11H only has one control register set from 0x00-0x04
		89	; --SL811H has two control register set from 0x00-0x04 and 0x08-0x0c
		90	;-------------------------------------------------------------------------
		91
		92	EP0Control EQU 0x00
		93	EP0Address EQU 0x01
		94	EP0XferLen EQU 0x02
		95	EP0Status EQU 0x03
		96	EP0Counter EQU 0x04
		97
		98	EP1Control EQU 0x08
		99	EP1Address EQU 0x09
		100	EP1XferLen EQU 0x0a
		101	EP1Status EQU 0x0b
		102	EP1Counter EQU 0x0c
		103
		104	CtrlReg EQU 0x05
		105	IntEna EQU 0x06
		106
		107	IntStatus EQU 0x0d
		108	cDATASet EQU 0x0e
		109	cSOFcnt EQU 0x0f ;Master=1 Slave=0, D+/D-Pol Swap=1 0=not [0-5] SOF Count
		110	;0xAE = 1100 1110
		111	;0xEE = 1110 1110
		112	cSOFMasterMode EQU 0x80
		113	cSOFLowSpeed EQU 0x40
		114	cSOFSlaveMode EQU 0x00
		115	cSOFFullSpeed EQU 0x00
		116	msSOFHighCountFS EQU ((sl811clock / 1000) >> 8) & 0x3f ;for FullSpeed 1ms rtfm
		117	msSOFLowCountFS EQU ((sl811clock / 1000) & 0xff) ;for FullSpeed 1ms rtfm
		118
		119	IntMask EQU 0x57 ;Reset\|DMA\|EP0\|EP2\|EP1 for IntEna
		120	HostMask EQU 0x47 ;Host request command for IntStatus
		121	ReadMask EQU 0xd7 ;Read mask interrupt for IntStatus
		122
		123	;Interrupt Status Mask
		124	USB_A_DONE EQU 0x01
		125	USB_B_DONE EQU 0x02
		126	BABBLE_DETECT EQU 0x04
		127	INT_RESERVE EQU 0x08
		128	SOF_TIMER EQU 0x10
		129	INSERT_REMOVE EQU 0x20
		130	USB_RESET EQU 0x40
		131	USB_DPLUS EQU 0x80
		132	INT_CLEAR EQU 0xFF
		133
		134	;EP0 Status Mask
		135	EP0_ACK EQU 0x01 ;EPxStatus bits mask during a read
		136	EP0_ERROR EQU 0x02
		137	EP0_TIMEOUT EQU 0x04
		138	EP0_SEQUENCE EQU 0x08
		139	EP0_SETUP EQU 0x10
		140	EP0_OVERFLOW EQU 0x20
		141	EP0_NAK EQU 0x40
		142	EP0_STALL EQU 0x80
		143
		144	;-------------------------------------------------------------------------
		145	; Standard Chapter 9 definition
		146	;-------------------------------------------------------------------------
		147	GET_STATUS EQU 0x00
		148	CLEAR_FEATURE EQU 0x01
		149	SET_FEATURE EQU 0x03
		150	SET_ADDRESS EQU 0x05
		151	GET_DESCRIPTOR EQU 0x06
		152	SET_DESCRIPTOR EQU 0x07
		153	GET_CONFIG EQU 0x08
		154	SET_CONFIG EQU 0x09
		155	GET_INTERFACE EQU 0x0a
		156	SET_INTERFACE EQU 0x0b
		157	SYNCH_FRAME EQU 0x0c
		158
		159	DEVICE EQU 0x01
		160	CONFIGURATION EQU 0x02
		161	STRING EQU 0x03
		162	INTERFACE EQU 0x04
		163	ENDPOINT EQU 0x05
		164
		165	STDCLASS EQU 0x00
		166
		167	;-------------------------------------------------------------------------
		168	; SL11H/SL811H definition
		169	;-------------------------------------------------------------------------
		170	;USB-A, USB-B Host Control Register [00H, 08H]
		171	;Pre Reserved
		172	;DatT Dir [1=Trans, 0=Recv]
		173	;OF Enable
		174	;ISO Arm
		175	DATA0_WR EQU 0x07 ;0000 0111 ( Data0 + OUT + Enable + Arm)
		176	sDATA0_WR EQU 0x27 ;0010 0111 ( Data0 + SOF + OUT + Enable + Arm)
		177
		178	DATA0_RD EQU 0x03 ;0000 0011 ( Data0 + IN + Enable + Arm)
		179	sDATA0_RD EQU 0x23 ;0010 0011 ( Data0 + SOF + IN + Enable + Arm)
		180
		181	PID_SETUP EQU 0xD0
		182	PID_IN EQU 0x90
		183	PID_OUT EQU 0x10

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(root)/rom/page5/source/fat/sl811_equ.a80 – Rev 845