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668 lvd 1 
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
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//
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// 'PFD' design based on ZEK code
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668 lvd 5 
/*
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    This file is part of ZX-Evo Base Configuration firmware.
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    ZX-Evo Base Configuration firmware is free software:
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    you can redistribute it and/or modify it under the terms of
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    the GNU General Public License as published by
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    the Free Software Foundation, either version 3 of the License, or
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    (at your option) any later version.
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    ZX-Evo Base Configuration firmware is distributed in the hope that
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    it will be useful, but WITHOUT ANY WARRANTY; without even
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    the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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    See the GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
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    along with ZX-Evo Base Configuration firmware.
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    If not, see <http://www.gnu.org/licenses/>.
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*/
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module fapch_zek
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(
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        input  wire fclk,
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        input  wire rdat_n,
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        output reg  vg_rclk,
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        output reg  vg_rawr
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);
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        reg [3:0] rdat_sr;
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        reg       rawr_sync;
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        reg rdat_n_r;
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        always @ (posedge fclk)
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        begin
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                rdat_n_r <= rdat_n;
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            rdat_sr <= { rdat_sr[2:0], rdat_n_r };
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            if (rdat_sr == 4'hF || rdat_sr == 4'h0)
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                rawr_sync <= rdat_sr[3];
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        end
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        // rawr
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        reg [4:0] rawr_sr;
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        always @ (posedge fclk)
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        begin
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            rawr_sr <= { rawr_sr[3:0], rawr_sync };
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            vg_rawr <= !(rawr_sr[4] && !rawr_sr[0] ); // rawr 140ns
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        end
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        // rclk
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        reg [5:0] counter = 0;
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        wire[5:0] delta = 27 - counter;
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        wire[5:0] shift = { delta[5], delta[5], delta[4:1] }; // sign div
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        wire[5:0] inc   = rawr_sr[1:0] == 2'b10 ? shift : 1;
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        always @ (posedge fclk)
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        begin
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            if (counter < 55)
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                counter <= counter + inc;
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            else
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            begin
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                counter <= 0;
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                vg_rclk = ~vg_rclk;
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            end
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        end
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        initial
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            vg_rclk = 0;
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endmodule
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