WebSVN – pentevo – Blame – /fpga/sdload/trunk/video/video

Rev	Author	Line No.	Line
668	lvd	1	// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
334	lvd	2	//
		3	// fetches video data for renderer
		4
668	lvd	5	/*
		6	This file is part of ZX-Evo Base Configuration firmware.
		7
		8	ZX-Evo Base Configuration firmware is free software:
		9	you can redistribute it and/or modify it under the terms of
		10	the GNU General Public License as published by
		11	the Free Software Foundation, either version 3 of the License, or
		12	(at your option) any later version.
		13
		14	ZX-Evo Base Configuration firmware is distributed in the hope that
		15	it will be useful, but WITHOUT ANY WARRANTY; without even
		16	the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
		17	See the GNU General Public License for more details.
		18
		19	You should have received a copy of the GNU General Public License
		20	along with ZX-Evo Base Configuration firmware.
		21	If not, see <http://www.gnu.org/licenses/>.
		22	*/
		23
		24	`include "../include/tune.v"
		25
334	lvd	26	module video_fetch(
		27
		28	input wire clk, // 28 MHz clock
		29
		30
		31	input wire cend, // general
		32	input wire pre_cend, // synchronization
		33
333	lvd	34	input wire vpix, // vertical window
334	lvd	35
		36	input wire fetch_start, // fetching start and stop
		37	input wire fetch_end, //
		38
336	lvd	39	output reg fetch_sync, // 1 cycle after cend
334	lvd	40
		41
		42	input wire [15:0] video_data, // video data receiving from dram arbiter
		43	input wire video_strobe, //
		44	output reg video_go, // indicates need for data
		45
336	lvd	46	output reg [63:0] pic_bits // picture bits -- data for renderer
334	lvd	47
		48	// currently, video_fetch assigns that there are only 1/8 and 1/4
		49	// bandwidth. !!needs correction for higher bandwidths!!
		50
		51
		52	);
		53	reg [3:0] fetch_sync_ctr; // generates fetch_sync to synchronize
		54	// fetch cycles (each 16 dram cycles long)
		55	// fetch_sync coincides with cend
		56
		57	reg [1:0] fetch_ptr; // pointer to fill pic_bits buffer
		58	reg fetch_ptr_clr; // clears fetch_ptr
		59
		60
		61	reg [15:0] fetch_data [0:3]; // stores data fetched from memory
		62
		63	// fetch window
		64	always @(posedge clk)
		65	if( fetch_start && vpix )
		66	video_go <= 1'b1;
		67	else if( fetch_end )
		68	video_go <= 1'b0;
		69
		70
		71
		72	// fetch sync counter
330	lvd	73	always @(posedge clk) if( cend )
334	lvd	74	begin
		75	if( fetch_start )
		76	fetch_sync_ctr <= 0;
		77	else
		78	fetch_sync_ctr <= fetch_sync_ctr + 1;
330	lvd	79	end
334	lvd	80
		81
		82	// fetch sync signal
		83	always @(posedge clk)
339	lvd	84	if( (fetch_sync_ctr==1) && pre_cend )
334	lvd	85	fetch_sync <= 1'b1;
		86	else
		87	fetch_sync <= 1'b0;
		88
		89
335	lvd	90
334	lvd	91	// fetch_ptr clear signal
		92	always @(posedge clk)
		93	if( (fetch_sync_ctr==0) && pre_cend )
		94	fetch_ptr_clr <= 1'b1;
		95	else
		96	fetch_ptr_clr <= 1'b0;
		97
		98
		99	// buffer fill pointer
		100	always @(posedge clk)
		101	if( fetch_ptr_clr )
		102	fetch_ptr <= 0;
		103	else if( video_strobe )
		104	fetch_ptr <= fetch_ptr + 1;
		105
		106
		107
		108	// store fetched data
		109	always @(posedge clk) if( video_strobe )
		110	fetch_data[fetch_ptr] <= video_data;
		111
339	lvd	112
334	lvd	113	// pass fetched data to renderer
336	lvd	114	always @(posedge clk) if( fetch_sync )
334	lvd	115	begin
		116	pic_bits[ 7:0 ] <= fetch_data[0][15:8 ];
		117	pic_bits[15:8 ] <= fetch_data[0][ 7:0 ];
		118	pic_bits[23:16] <= fetch_data[1][15:8 ];
		119	pic_bits[31:24] <= fetch_data[1][ 7:0 ];
		120	pic_bits[39:32] <= fetch_data[2][15:8 ];
		121	pic_bits[47:40] <= fetch_data[2][ 7:0 ];
		122	pic_bits[55:48] <= fetch_data[3][15:8 ];
		123	pic_bits[63:56] <= fetch_data[3][ 7:0 ];
		124	end
		125
		126	endmodule
		127
		128

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