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668 lvd 1 
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
334 lvd 2 
//
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// fetches video data for renderer
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668 lvd 5 
/*
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    This file is part of ZX-Evo Base Configuration firmware.
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    ZX-Evo Base Configuration firmware is free software:
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    you can redistribute it and/or modify it under the terms of
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    the GNU General Public License as published by
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    the Free Software Foundation, either version 3 of the License, or
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    (at your option) any later version.
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    ZX-Evo Base Configuration firmware is distributed in the hope that
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    it will be useful, but WITHOUT ANY WARRANTY; without even
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    the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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    See the GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
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    along with ZX-Evo Base Configuration firmware.
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    If not, see <http://www.gnu.org/licenses/>.
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*/
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`include "../include/tune.v"
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334 lvd 26 
module video_fetch(
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        input  wire        clk, // 28 MHz clock
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        input  wire        cend,     // general
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        input  wire        pre_cend, //        synchronization
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333 lvd 34 
        input  wire        vpix, // vertical window
334 lvd 35 
 
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        input  wire        fetch_start, // fetching start and stop
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        input  wire        fetch_end,   //
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336 lvd 39 
        output reg         fetch_sync,     // 1 cycle after cend
334 lvd 40 
 
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        input  wire [15:0] video_data,   // video data receiving from dram arbiter
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        input  wire        video_strobe, //
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        output reg         video_go, // indicates need for data
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336 lvd 46 
        output reg  [63:0] pic_bits // picture bits -- data for renderer
334 lvd 47 
 
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        // currently, video_fetch assigns that there are only 1/8 and 1/4
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        // bandwidth. !!needs correction for higher bandwidths!!
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);
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        reg [3:0] fetch_sync_ctr; // generates fetch_sync to synchronize
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                                  // fetch cycles (each 16 dram cycles long)
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                                  // fetch_sync coincides with cend
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        reg [1:0] fetch_ptr; // pointer to fill pic_bits buffer
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        reg       fetch_ptr_clr; // clears fetch_ptr
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        reg [15:0] fetch_data [0:3]; // stores data fetched from memory
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        // fetch window
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        always @(posedge clk)
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                if( fetch_start && vpix )
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                        video_go <= 1'b1;
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                else if( fetch_end )
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                        video_go <= 1'b0;
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        // fetch sync counter
330 lvd 73 
        always @(posedge clk) if( cend )
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        begin
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                if( fetch_start )
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                        fetch_sync_ctr <= 0;
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                else
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                        fetch_sync_ctr <= fetch_sync_ctr + 1;
330 lvd 79 
        end
334 lvd 80 
 
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        // fetch sync signal
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        always @(posedge clk)
339 lvd 84 
                if( (fetch_sync_ctr==1) && pre_cend )
334 lvd 85 
                        fetch_sync <= 1'b1;
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                else
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                        fetch_sync <= 1'b0;
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335 lvd 90 
 
334 lvd 91 
        // fetch_ptr clear signal
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        always @(posedge clk)
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                if( (fetch_sync_ctr==0) && pre_cend )
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                        fetch_ptr_clr <= 1'b1;
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                else
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                        fetch_ptr_clr <= 1'b0;
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        // buffer fill pointer
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        always @(posedge clk)
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                if( fetch_ptr_clr )
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                        fetch_ptr <= 0;
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                else if( video_strobe )
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                        fetch_ptr <= fetch_ptr + 1;
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        // store fetched data
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        always @(posedge clk) if( video_strobe )
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                fetch_data[fetch_ptr] <= video_data;
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339 lvd 112 
 
334 lvd 113 
        // pass fetched data to renderer
336 lvd 114 
        always @(posedge clk) if( fetch_sync )
334 lvd 115 
        begin
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                pic_bits[ 7:0 ] <= fetch_data[0][15:8 ];
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                pic_bits[15:8 ] <= fetch_data[0][ 7:0 ];
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                pic_bits[23:16] <= fetch_data[1][15:8 ];
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                pic_bits[31:24] <= fetch_data[1][ 7:0 ];
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                pic_bits[39:32] <= fetch_data[2][15:8 ];
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                pic_bits[47:40] <= fetch_data[2][ 7:0 ];
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                pic_bits[55:48] <= fetch_data[3][15:8 ];
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                pic_bits[63:56] <= fetch_data[3][ 7:0 ];
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        end
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endmodule
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