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668 lvd 1 
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
88 lvd 2 
//
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// wait generator for Z80
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668 lvd 5 
/*
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    This file is part of ZX-Evo Base Configuration firmware.
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    ZX-Evo Base Configuration firmware is free software:
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    you can redistribute it and/or modify it under the terms of
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    the GNU General Public License as published by
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    the Free Software Foundation, either version 3 of the License, or
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    (at your option) any later version.
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    ZX-Evo Base Configuration firmware is distributed in the hope that
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    it will be useful, but WITHOUT ANY WARRANTY; without even
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    the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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    See the GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
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    along with ZX-Evo Base Configuration firmware.
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    If not, see <http://www.gnu.org/licenses/>.
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*/
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200 lvd 24 
`include "../include/tune.v"
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module zwait(
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        input  wire rst_n,
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        input  wire wait_start_gluclock,
228 lvd 31 
        input  wire wait_start_comport,
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        input  wire wait_end,
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        output reg  [6:0] waits,
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        output wire wait_n,
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        output wire spiint_n
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);
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200 lvd 43 
`ifdef SIMULATE
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        initial
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        begin
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//              force waits = 7'd0;
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                waits <= 7'd0;
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        end
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`endif
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88 lvd 52 
        wire wait_off_n;
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        assign wait_off_n = (~wait_end) & rst_n;
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228 lvd 55 
        // RS-flipflops
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        //
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        always @(posedge wait_start_gluclock, negedge wait_off_n)
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        if( !wait_off_n )
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                waits[0] <= 1'b0;
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        else if( wait_start_gluclock )
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                waits[0] <= 1'b1;
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        //
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        always @(posedge wait_start_comport, negedge wait_off_n)
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        if( !wait_off_n )
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                waits[1] <= 1'b0;
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        else if( wait_start_comport )
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                waits[1] <= 1'b1;
88 lvd 68 
 
228 lvd 69 
 
88 lvd 70 
        always @(posedge wait_end) // just dummy for future extensions
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        begin
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                waits[6:2] <= 5'd0;
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        end
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684 lvd 77 
`ifndef SIMULATE
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        assign spiint_n = ~|waits;
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        assign wait_n = spiint_n ? 1'bZ : 1'b0;
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`else
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        assign spiint_n = 1'b1;
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        assign wait_n = 1'bZ;
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`endif
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endmodule
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