Rev 668 | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
668 | lvd | 1 | // ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014 |
323 | lvd | 2 | // |
3 | // mix up border and pixels, add palette and blanks |
||
4 | |||
668 | lvd | 5 | /* |
6 | This file is part of ZX-Evo Base Configuration firmware. |
||
7 | |||
8 | ZX-Evo Base Configuration firmware is free software: |
||
9 | you can redistribute it and/or modify it under the terms of |
||
10 | the GNU General Public License as published by |
||
11 | the Free Software Foundation, either version 3 of the License, or |
||
12 | (at your option) any later version. |
||
13 | |||
14 | ZX-Evo Base Configuration firmware is distributed in the hope that |
||
15 | it will be useful, but WITHOUT ANY WARRANTY; without even |
||
16 | the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
||
17 | See the GNU General Public License for more details. |
||
18 | |||
19 | You should have received a copy of the GNU General Public License |
||
20 | along with ZX-Evo Base Configuration firmware. |
||
21 | If not, see <http://www.gnu.org/licenses/>. |
||
22 | */ |
||
23 | |||
24 | `include "../include/tune.v" |
||
25 | |||
323 | lvd | 26 | module video_palframe( |
27 | |||
28 | input wire clk, // 28MHz clock |
||
29 | |||
30 | |||
31 | input wire hpix, |
||
32 | input wire vpix, |
||
33 | |||
34 | input wire hblank, |
||
35 | input wire vblank, |
||
36 | |||
668 | lvd | 37 | input wire hsync_start, |
38 | input wire vsync, |
||
39 | |||
323 | lvd | 40 | input wire [ 3:0] pixels, |
41 | input wire [ 3:0] border, |
||
42 | |||
684 | lvd | 43 | input wire border_sync, |
44 | input wire border_sync_ena, |
||
45 | |||
668 | lvd | 46 | // ulaplus related |
47 | input wire [ 1:0] up_palsel, |
||
48 | input wire [ 2:0] up_paper, |
||
49 | input wire [ 2:0] up_ink, |
||
50 | input wire up_pixel, |
||
323 | lvd | 51 | |
668 | lvd | 52 | input wire up_ena, |
53 | input wire up_palwr, |
||
54 | input wire [ 5:0] up_paladdr, |
||
55 | input wire [ 7:0] up_paldata, |
||
56 | |||
323 | lvd | 57 | input wire atm_palwr, |
58 | input wire [ 5:0] atm_paldata, |
||
59 | |||
60 | |||
668 | lvd | 61 | output wire [ 5:0] palcolor, // just for palette readback |
425 | lvd | 62 | |
325 | lvd | 63 | output wire [ 5:0] color |
323 | lvd | 64 | ); |
668 | lvd | 65 | reg [7:0] palette_read; |
323 | lvd | 66 | |
67 | wire [ 3:0] zxcolor; |
||
668 | lvd | 68 | wire [ 5:0] up_color; |
69 | wire [ 8:0] palette_color; |
||
323 | lvd | 70 | |
684 | lvd | 71 | reg [3:0] synced_border; |
72 | |||
668 | lvd | 73 | reg vsync_r; |
74 | reg [1:0] ctr_14; |
||
75 | reg ctr_h; |
||
76 | reg ctr_v; |
||
323 | lvd | 77 | |
78 | |||
684 | lvd | 79 | always @(posedge clk) |
80 | if( border_sync ) |
||
81 | synced_border <= border; |
||
82 | |||
83 | assign zxcolor = (hpix&vpix) ? pixels : (border_sync_ena ? synced_border : border); |
||
84 | |||
668 | lvd | 85 | assign up_color = (hpix&vpix) ? {up_palsel,~up_pixel,up_pixel?up_ink:up_paper} : {3'd0,border[2:0]}; |
323 | lvd | 86 | |
668 | lvd | 87 | assign palette_color = up_ena ? {3'b100,up_color} : {5'd0,zxcolor}; |
323 | lvd | 88 | |
337 | lvd | 89 | |
323 | lvd | 90 | // palette |
668 | lvd | 91 | reg [7:0] palette [0:511]; // let quartus instantiate it as RAM |
323 | lvd | 92 | |
93 | always @(posedge clk) |
||
94 | begin |
||
668 | lvd | 95 | if( atm_palwr || up_palwr ) |
96 | begin : palette_write |
||
97 | reg [8:0] pal_addr; |
||
98 | pal_addr = atm_palwr ? { 5'd0, zxcolor } : { 3'b100, up_paladdr }; |
||
339 | lvd | 99 | |
668 | lvd | 100 | palette[pal_addr] <= atm_palwr ? {atm_paldata[3:2],1'b0,atm_paldata[5:4],1'b0,atm_paldata[1:0]} : up_paldata; |
101 | end |
||
102 | |||
103 | palette_read <= palette[palette_color]; |
||
323 | lvd | 104 | end |
105 | |||
106 | |||
668 | lvd | 107 | assign palcolor = {palette_read[4:3],palette_read[7:6], palette_read[1:0]}; |
323 | lvd | 108 | |
109 | |||
668 | lvd | 110 | |
111 | |||
112 | // make 3bit palette |
||
113 | always @(posedge clk) |
||
114 | vsync_r <= vsync; |
||
115 | // |
||
116 | wire vsync_start = vsync && !vsync_r; |
||
117 | // |
||
118 | initial ctr_14 = 2'b00; |
||
119 | always @(posedge clk) |
||
120 | ctr_14 <= ctr_14+2'b01; |
||
121 | // |
||
122 | initial ctr_h = 1'b0; |
||
123 | always @(posedge clk) if( hsync_start ) |
||
124 | ctr_h <= ~ctr_h; |
||
125 | // |
||
126 | initial ctr_v = 1'b0; |
||
127 | always @(posedge clk) if( vsync_start ) |
||
128 | ctr_v <= ~ctr_v; |
||
129 | |||
130 | |||
131 | wire plus1 = ctr_14[1] ^ ctr_h ^ ctr_v; |
||
132 | |||
133 | |||
134 | |||
135 | wire [1:0] red; |
||
136 | wire [1:0] grn; |
||
137 | wire [1:0] blu; |
||
138 | |||
139 | video_palframe_mk3bit red_color |
||
140 | ( |
||
141 | .plus1 (plus1 ), |
||
142 | .color_in (palette_read[7:5]), |
||
143 | .color_out(red ) |
||
144 | ); |
||
145 | // |
||
146 | video_palframe_mk3bit grn_color |
||
147 | ( |
||
148 | .plus1 (plus1 ), |
||
149 | .color_in (palette_read[4:2]), |
||
150 | .color_out(grn ) |
||
151 | ); |
||
152 | // |
||
153 | assign blu = palette_read[1:0]; |
||
154 | |||
155 | assign color = (hblank | vblank) ? 6'd0 : {grn,red,blu}; |
||
156 | |||
157 | |||
323 | lvd | 158 | endmodule |
159 | |||
668 | lvd | 160 | module video_palframe_mk3bit |
161 | ( |
||
162 | input wire plus1, |
||
163 | |||
164 | input wire [2:0] color_in, |
||
165 | output reg [1:0] color_out |
||
166 | ); |
||
167 | |||
168 | always @* |
||
169 | case( color_in ) |
||
170 | 3'b000: color_out <= 2'b00; |
||
171 | 3'b001: color_out <= plus1 ? 2'b01 : 2'b00; |
||
172 | 3'b010: color_out <= 2'b01; |
||
173 | 3'b011: color_out <= plus1 ? 2'b10 : 2'b01; |
||
174 | 3'b100: color_out <= 2'b10; |
||
175 | 3'b101: color_out <= plus1 ? 2'b11 : 2'b10; |
||
176 | default: color_out <= 2'b11; |
||
177 | endcase |
||
178 | |||
179 | endmodule |
||
180 |