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1062 lvd 1 
// ZX-Evo SDLoad Configuration (c) NedoPC 2023
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//
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// fetch/display data from internal EABs
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/*
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    This file is part of ZX-Evo Base Configuration firmware.
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    ZX-Evo Base Configuration firmware is free software:
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    you can redistribute it and/or modify it under the terms of
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    the GNU General Public License as published by
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    the Free Software Foundation, either version 3 of the License, or
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    (at your option) any later version.
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    ZX-Evo Base Configuration firmware is distributed in the hope that
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    it will be useful, but WITHOUT ANY WARRANTY; without even
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    the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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    See the GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
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    along with ZX-Evo Base Configuration firmware.
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    If not, see <http://www.gnu.org/licenses/>.
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*/
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module video_fetch
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(
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        input  wire clk,
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        input  wire rst_n,
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        input  wire pix_stb,
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        input  wire i_hsync,
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        input  wire i_vsync,
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        input  wire i_hpix,
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        input  wire i_vpix,
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        input  wire v_init,
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        input  wire h_init,
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        input  wire h_step,
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        input  wire h_char,
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        // char/attr memory read
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        output wire        char_r_rdena, // marks valid char_r_addr
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        output wire [11:0] char_r_addr,
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        input  wire [ 7:0] char_r_data, // 1 cycle latency
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        // font memory read
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        output wire [ 9:0] font_r_addr,
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        input  wire [ 7:0] font_r_data, // 1 cycle latency
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);
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        localparam CHAR_ADDR_INIT = 12'h000;
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        localparam CHAR_LINE_ADD  = 12'd60;
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        localparam ATTR_ADDR_INIT = 12'h9C0;
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        localparam ATTR_LINE_ADD  = 12'd40;
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        reg [11:0] char_line_addr;
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        reg [11:0] attr_line_addr;
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        reg [11:0] char_addr;
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        reg [11:0] attr_addr;
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        reg [2:0] attr_phase;
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        always @(posedge clk)
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        if( pix_stb )
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        begin
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                if( v_init )
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                        char_line_addr <= CHAR_ADDR_INIT;
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                else if( h_step )
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                        char_line_addr <= char_line_addr + CHAR_LINE_ADD;
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        end
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        //
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        always @(posedge clk)
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        if( pix_stb )
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        begin
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                if( h_init )
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                        char_addr <= char_line_addr;
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                else if( h_char )
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                        char_addr <= char_addr + 12'd1;
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        end
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        always @(posedge clk)
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        if( pix_stb )
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        begin
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                if( v_init )
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                        attr_line_addr <= ATTR_ADDR_INIT;
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                else if( h_step )
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                        attr_line_addr <= attr_line_addr + ATTR_LINE_ADD;
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        end
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endmodule
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